cvmx-asm.h revision 232812
1/***********************license start*************** 2 * Copyright (c) 2003-2010 Cavium Inc. (support@cavium.com). All rights 3 * reserved. 4 * 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: 9 * 10 * * Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 13 * * Redistributions in binary form must reproduce the above 14 * copyright notice, this list of conditions and the following 15 * disclaimer in the documentation and/or other materials provided 16 * with the distribution. 17 18 * * Neither the name of Cavium Inc. nor the names of 19 * its contributors may be used to endorse or promote products 20 * derived from this software without specific prior written 21 * permission. 22 23 * This Software, including technical data, may be subject to U.S. export control 24 * laws, including the U.S. Export Administration Act and its associated 25 * regulations, and may be subject to export or import regulations in other 26 * countries. 27 28 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29 * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR 30 * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31 * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32 * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33 * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34 * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35 * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36 * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37 * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38 ***********************license end**************************************/ 39 40 41 42 43 44 45 46/** 47 * @file 48 * 49 * This is file defines ASM primitives for the executive. 50 51 * <hr>$Revision: 70030 $<hr> 52 * 53 * 54 */ 55#ifndef __CVMX_ASM_H__ 56#define __CVMX_ASM_H__ 57 58#define CVMX_MAX_CORES (32) 59 60#define COP0_INDEX $0,0 /* TLB read/write index */ 61#define COP0_RANDOM $1,0 /* TLB random index */ 62#define COP0_ENTRYLO0 $2,0 /* TLB entryLo0 */ 63#define COP0_ENTRYLO1 $3,0 /* TLB entryLo1 */ 64#define COP0_CONTEXT $4,0 /* Context */ 65#define COP0_PAGEMASK $5,0 /* TLB pagemask */ 66#define COP0_PAGEGRAIN $5,1 /* TLB config for max page sizes */ 67#define COP0_WIRED $6,0 /* TLB number of wired entries */ 68#define COP0_HWRENA $7,0 /* rdhw instruction enable per register */ 69#define COP0_BADVADDR $8,0 /* Bad virtual address */ 70#define COP0_COUNT $9,0 /* Mips count register */ 71#define COP0_CVMCOUNT $9,6 /* Cavium count register */ 72#define COP0_CVMCTL $9,7 /* Cavium control */ 73#define COP0_ENTRYHI $10,0 /* TLB entryHi */ 74#define COP0_COMPARE $11,0 /* Mips compare register */ 75#define COP0_POWTHROTTLE $11,6 /* Power throttle register */ 76#define COP0_CVMMEMCTL $11,7 /* Cavium memory control */ 77#define COP0_STATUS $12,0 /* Mips status register */ 78#define COP0_INTCTL $12,1 /* Useless (Vectored interrupts) */ 79#define COP0_SRSCTL $12,2 /* Useless (Shadow registers) */ 80#define COP0_CAUSE $13,0 /* Mips cause register */ 81#define COP0_EPC $14,0 /* Exception program counter */ 82#define COP0_PRID $15,0 /* Processor ID */ 83#define COP0_EBASE $15,1 /* Exception base */ 84#define COP0_CONFIG $16,0 /* Misc config options */ 85#define COP0_CONFIG1 $16,1 /* Misc config options */ 86#define COP0_CONFIG2 $16,2 /* Misc config options */ 87#define COP0_CONFIG3 $16,3 /* Misc config options */ 88#define COP0_WATCHLO0 $18,0 /* Address watch registers */ 89#define COP0_WATCHLO1 $18,1 /* Address watch registers */ 90#define COP0_WATCHHI0 $19,0 /* Address watch registers */ 91#define COP0_WATCHHI1 $19,1 /* Address watch registers */ 92#define COP0_XCONTEXT $20,0 /* OS context */ 93#define COP0_MULTICOREDEBUG $22,0 /* Cavium debug */ 94#define COP0_DEBUG $23,0 /* Debug status */ 95#define COP0_DEPC $24,0 /* Debug PC */ 96#define COP0_PERFCONTROL0 $25,0 /* Performance counter control */ 97#define COP0_PERFCONTROL1 $25,2 /* Performance counter control */ 98#define COP0_PERFVALUE0 $25,1 /* Performance counter */ 99#define COP0_PERFVALUE1 $25,3 /* Performance counter */ 100#define COP0_CACHEERRI $27,0 /* I cache error status */ 101#define COP0_CACHEERRD $27,1 /* D cache error status */ 102#define COP0_TAGLOI $28,0 /* I cache tagLo */ 103#define COP0_TAGLOD $28,2 /* D cache tagLo */ 104#define COP0_DATALOI $28,1 /* I cache dataLo */ 105#define COP0_DATALOD $28,3 /* D cahce dataLo */ 106#define COP0_TAGHI $29,2 /* ? */ 107#define COP0_DATAHII $29,1 /* ? */ 108#define COP0_DATAHID $29,3 /* ? */ 109#define COP0_ERROREPC $30,0 /* Error PC */ 110#define COP0_DESAVE $31,0 /* Debug scratch area */ 111 112/* This header file can be included from a .S file. Keep non-preprocessor 113 things under !__ASSEMBLER__. */ 114#ifndef __ASSEMBLER__ 115 116#ifdef __cplusplus 117extern "C" { 118#endif 119 120/* turn the variable name into a string */ 121#define CVMX_TMP_STR(x) CVMX_TMP_STR2(x) 122#define CVMX_TMP_STR2(x) #x 123 124/* Since sync is required for Octeon2. */ 125#ifdef _MIPS_ARCH_OCTEON2 126#define CVMX_CAVIUM_OCTEON2 1 127#endif 128 129/* other useful stuff */ 130#define CVMX_BREAK asm volatile ("break") 131#define CVMX_SYNC asm volatile ("sync" : : :"memory") 132/* String version of SYNCW macro for using in inline asm constructs */ 133#define CVMX_SYNCW_STR_OCTEON2 "syncw\n" 134#ifdef CVMX_CAVIUM_OCTEON2 135 #define CVMX_SYNCW_STR CVMX_SYNCW_STR_OCTEON2 136#else 137 #define CVMX_SYNCW_STR "syncw\nsyncw\n" 138#endif /* CVMX_CAVIUM_OCTEON2 */ 139 140#ifdef __OCTEON__ 141 #define CVMX_SYNCIOBDMA asm volatile ("synciobdma" : : :"memory") 142 /* We actually use two syncw instructions in a row when we need a write 143 memory barrier. This is because the CN3XXX series of Octeons have 144 errata Core-401. This can cause a single syncw to not enforce 145 ordering under very rare conditions. Even if it is rare, better safe 146 than sorry */ 147 #define CVMX_SYNCW_OCTEON2 asm volatile ("syncw\n" : : :"memory") 148 #ifdef CVMX_CAVIUM_OCTEON2 149 #define CVMX_SYNCW CVMX_SYNCW_OCTEON2 150 #else 151 #define CVMX_SYNCW asm volatile ("syncw\nsyncw\n" : : :"memory") 152 #endif /* CVMX_CAVIUM_OCTEON2 */ 153#if defined(VXWORKS) || defined(__linux__) 154 /* Define new sync instructions to be normal SYNC instructions for 155 operating systems that use threads */ 156 #define CVMX_SYNCWS CVMX_SYNCW 157 #define CVMX_SYNCS CVMX_SYNC 158 #define CVMX_SYNCWS_STR CVMX_SYNCW_STR 159 #define CVMX_SYNCWS_OCTEON2 CVMX_SYNCW_OCTEON2 160 #define CVMX_SYNCWS_STR_OCTEON2 CVMX_SYNCW_STR_OCTEON2 161#else 162 #if defined(CVMX_BUILD_FOR_TOOLCHAIN) 163 /* While building simple exec toolchain, always use syncw to 164 support all Octeon models. */ 165 #define CVMX_SYNCWS CVMX_SYNCW 166 #define CVMX_SYNCS CVMX_SYNC 167 #define CVMX_SYNCWS_STR CVMX_SYNCW_STR 168 #define CVMX_SYNCWS_OCTEON2 CVMX_SYNCW_OCTEON2 169 #define CVMX_SYNCWS_STR_OCTEON2 CVMX_SYNCW_STR_OCTEON2 170 #else 171 /* Again, just like syncw, we may need two syncws instructions in a row due 172 errata Core-401. Only one syncws is required for Octeon2 models */ 173 #define CVMX_SYNCS asm volatile ("syncs" : : :"memory") 174 #define CVMX_SYNCWS_OCTEON2 asm volatile ("syncws\n" : : :"memory") 175 #define CVMX_SYNCWS_STR_OCTEON2 "syncws\n" 176 #ifdef CVMX_CAVIUM_OCTEON2 177 #define CVMX_SYNCWS CVMX_SYNCWS_OCTEON2 178 #define CVMX_SYNCWS_STR CVMX_SYNCWS_STR_OCTEON2 179 #else 180 #define CVMX_SYNCWS asm volatile ("syncws\nsyncws\n" : : :"memory") 181 #define CVMX_SYNCWS_STR "syncws\nsyncws\n" 182 #endif /* CVMX_CAVIUM_OCTEON2 */ 183 #endif 184#endif 185#else /* !__OCTEON__ */ 186 /* Not using a Cavium compiler, always use the slower sync so the assembler stays happy */ 187 #define CVMX_SYNCIOBDMA asm volatile ("sync" : : :"memory") 188 #define CVMX_SYNCW asm volatile ("sync" : : :"memory") 189 #define CVMX_SYNCWS CVMX_SYNCW 190 #define CVMX_SYNCS CVMX_SYNC 191 #define CVMX_SYNCWS_STR CVMX_SYNCW_STR 192 #define CVMX_SYNCWS_OCTEON2 CVMX_SYNCW 193 #define CVMX_SYNCWS_STR_OCTEON2 CVMX_SYNCW_STR 194#endif 195#define CVMX_SYNCI(address, offset) asm volatile ("synci " CVMX_TMP_STR(offset) "(%[rbase])" : : [rbase] "d" (address) ) 196#define CVMX_PREFETCH0(address) CVMX_PREFETCH(address, 0) 197#define CVMX_PREFETCH128(address) CVMX_PREFETCH(address, 128) 198// a normal prefetch 199#define CVMX_PREFETCH(address, offset) CVMX_PREFETCH_PREF0(address, offset) 200// normal prefetches that use the pref instruction 201#define CVMX_PREFETCH_PREFX(X, address, offset) asm volatile ("pref %[type], %[off](%[rbase])" : : [rbase] "d" (address), [off] "I" (offset), [type] "n" (X)) 202#define CVMX_PREFETCH_PREF0(address, offset) CVMX_PREFETCH_PREFX(0, address, offset) 203#define CVMX_PREFETCH_PREF1(address, offset) CVMX_PREFETCH_PREFX(1, address, offset) 204#define CVMX_PREFETCH_PREF6(address, offset) CVMX_PREFETCH_PREFX(6, address, offset) 205#define CVMX_PREFETCH_PREF7(address, offset) CVMX_PREFETCH_PREFX(7, address, offset) 206// prefetch into L1, do not put the block in the L2 207#define CVMX_PREFETCH_NOTL2(address, offset) CVMX_PREFETCH_PREFX(4, address, offset) 208#define CVMX_PREFETCH_NOTL22(address, offset) CVMX_PREFETCH_PREFX(5, address, offset) 209// prefetch into L2, do not put the block in the L1 210#define CVMX_PREFETCH_L2(address, offset) CVMX_PREFETCH_PREFX(28, address, offset) 211// CVMX_PREPARE_FOR_STORE makes each byte of the block unpredictable (actually old value or zero) until 212// that byte is stored to (by this or another processor. Note that the value of each byte is not only 213// unpredictable, but may also change again - up until the point when one of the cores stores to the 214// byte. 215#define CVMX_PREPARE_FOR_STORE(address, offset) CVMX_PREFETCH_PREFX(30, address, offset) 216// This is a command headed to the L2 controller to tell it to clear its dirty bit for a 217// block. Basically, SW is telling HW that the current version of the block will not be 218// used. 219#define CVMX_DONT_WRITE_BACK(address, offset) CVMX_PREFETCH_PREFX(29, address, offset) 220 221#define CVMX_ICACHE_INVALIDATE { CVMX_SYNC; asm volatile ("synci 0($0)" : : ); } // flush stores, invalidate entire icache 222#define CVMX_ICACHE_INVALIDATE2 { CVMX_SYNC; asm volatile ("cache 0, 0($0)" : : ); } // flush stores, invalidate entire icache 223#define CVMX_DCACHE_INVALIDATE { CVMX_SYNC; asm volatile ("cache 9, 0($0)" : : ); } // complete prefetches, invalidate entire dcache 224 225#define CVMX_CACHE(op, address, offset) asm volatile ("cache " CVMX_TMP_STR(op) ", " CVMX_TMP_STR(offset) "(%[rbase])" : : [rbase] "d" (address) ) 226#define CVMX_CACHE_LCKL2(address, offset) CVMX_CACHE(31, address, offset) // fetch and lock the state. 227#define CVMX_CACHE_WBIL2(address, offset) CVMX_CACHE(23, address, offset) // unlock the state. 228#define CVMX_CACHE_WBIL2I(address, offset) CVMX_CACHE(3, address, offset) // invalidate the cache block and clear the USED bits for the block 229#define CVMX_CACHE_LTGL2I(address, offset) CVMX_CACHE(7, address, offset) // load virtual tag and data for the L2 cache block into L2C_TAD0_TAG register 230 231/* new instruction to make RC4 run faster */ 232#define CVMX_BADDU(result, input1, input2) asm ("baddu %[rd],%[rs],%[rt]" : [rd] "=d" (result) : [rs] "d" (input1) , [rt] "d" (input2)) 233 234// misc v2 stuff 235#define CVMX_ROTR(result, input1, shiftconst) asm ("rotr %[rd],%[rs]," CVMX_TMP_STR(shiftconst) : [rd] "=d" (result) : [rs] "d" (input1)) 236#define CVMX_ROTRV(result, input1, input2) asm ("rotrv %[rd],%[rt],%[rs]" : [rd] "=d" (result) : [rt] "d" (input1) , [rs] "d" (input2)) 237#define CVMX_DROTR(result, input1, shiftconst) asm ("drotr %[rd],%[rs]," CVMX_TMP_STR(shiftconst) : [rd] "=d" (result) : [rs] "d" (input1)) 238#define CVMX_DROTRV(result, input1, input2) asm ("drotrv %[rd],%[rt],%[rs]" : [rd] "=d" (result) : [rt] "d" (input1) , [rs] "d" (input2)) 239#define CVMX_SEB(result, input1) asm ("seb %[rd],%[rt]" : [rd] "=d" (result) : [rt] "d" (input1)) 240#define CVMX_SEH(result, input1) asm ("seh %[rd],%[rt]" : [rd] "=d" (result) : [rt] "d" (input1)) 241#define CVMX_DSBH(result, input1) asm ("dsbh %[rd],%[rt]" : [rd] "=d" (result) : [rt] "d" (input1)) 242#define CVMX_DSHD(result, input1) asm ("dshd %[rd],%[rt]" : [rd] "=d" (result) : [rt] "d" (input1)) 243#define CVMX_WSBH(result, input1) asm ("wsbh %[rd],%[rt]" : [rd] "=d" (result) : [rt] "d" (input1)) 244 245// Endian swap 246#define CVMX_ES64(result, input) \ 247 do {\ 248 CVMX_DSBH(result, input); \ 249 CVMX_DSHD(result, result); \ 250 } while (0) 251#define CVMX_ES32(result, input) \ 252 do {\ 253 CVMX_WSBH(result, input); \ 254 CVMX_ROTR(result, result, 16); \ 255 } while (0) 256 257 258/* extract and insert - NOTE that pos and len variables must be constants! */ 259/* the P variants take len rather than lenm1 */ 260/* the M1 variants take lenm1 rather than len */ 261#define CVMX_EXTS(result,input,pos,lenm1) asm ("exts %[rt],%[rs]," CVMX_TMP_STR(pos) "," CVMX_TMP_STR(lenm1) : [rt] "=d" (result) : [rs] "d" (input)) 262#define CVMX_EXTSP(result,input,pos,len) CVMX_EXTS(result,input,pos,(len)-1) 263 264#define CVMX_DEXT(result,input,pos,len) asm ("dext %[rt],%[rs]," CVMX_TMP_STR(pos) "," CVMX_TMP_STR(len) : [rt] "=d" (result) : [rs] "d" (input)) 265#define CVMX_DEXTM1(result,input,pos,lenm1) CVMX_DEXT(result,input,pos,(lenm1)+1) 266 267#define CVMX_EXT(result,input,pos,len) asm ("ext %[rt],%[rs]," CVMX_TMP_STR(pos) "," CVMX_TMP_STR(len) : [rt] "=d" (result) : [rs] "d" (input)) 268#define CVMX_EXTM1(result,input,pos,lenm1) CVMX_EXT(result,input,pos,(lenm1)+1) 269 270// removed 271// #define CVMX_EXTU(result,input,pos,lenm1) asm ("extu %[rt],%[rs]," CVMX_TMP_STR(pos) "," CVMX_TMP_STR(lenm1) : [rt] "=d" (result) : [rs] "d" (input)) 272// #define CVMX_EXTUP(result,input,pos,len) CVMX_EXTU(result,input,pos,(len)-1) 273 274#define CVMX_CINS(result,input,pos,lenm1) asm ("cins %[rt],%[rs]," CVMX_TMP_STR(pos) "," CVMX_TMP_STR(lenm1) : [rt] "=d" (result) : [rs] "d" (input)) 275#define CVMX_CINSP(result,input,pos,len) CVMX_CINS(result,input,pos,(len)-1) 276 277#define CVMX_DINS(result,input,pos,len) asm ("dins %[rt],%[rs]," CVMX_TMP_STR(pos) "," CVMX_TMP_STR(len): [rt] "=d" (result): [rs] "d" (input), "[rt]" (result)) 278#define CVMX_DINSM1(result,input,pos,lenm1) CVMX_DINS(result,input,pos,(lenm1)+1) 279#define CVMX_DINSC(result,pos,len) asm ("dins %[rt],$0," CVMX_TMP_STR(pos) "," CVMX_TMP_STR(len): [rt] "=d" (result): "[rt]" (result)) 280#define CVMX_DINSCM1(result,pos,lenm1) CVMX_DINSC(result,pos,(lenm1)+1) 281 282#define CVMX_INS(result,input,pos,len) asm ("ins %[rt],%[rs]," CVMX_TMP_STR(pos) "," CVMX_TMP_STR(len): [rt] "=d" (result): [rs] "d" (input), "[rt]" (result)) 283#define CVMX_INSM1(result,input,pos,lenm1) CVMX_INS(result,input,pos,(lenm1)+1) 284#define CVMX_INSC(result,pos,len) asm ("ins %[rt],$0," CVMX_TMP_STR(pos) "," CVMX_TMP_STR(len): [rt] "=d" (result): "[rt]" (result)) 285#define CVMX_INSCM1(result,pos,lenm1) CVMX_INSC(result,pos,(lenm1)+1) 286 287// removed 288// #define CVMX_INS0(result,input,pos,lenm1) asm("ins0 %[rt],%[rs]," CVMX_TMP_STR(pos) "," CVMX_TMP_STR(lenm1): [rt] "=d" (result): [rs] "d" (input), "[rt]" (result)) 289// #define CVMX_INS0P(result,input,pos,len) CVMX_INS0(result,input,pos,(len)-1) 290// #define CVMX_INS0C(result,pos,lenm1) asm ("ins0 %[rt],$0," CVMX_TMP_STR(pos) "," CVMX_TMP_STR(lenm1) : [rt] "=d" (result) : "[rt]" (result)) 291// #define CVMX_INS0CP(result,pos,len) CVMX_INS0C(result,pos,(len)-1) 292 293#define CVMX_CLZ(result, input) asm ("clz %[rd],%[rs]" : [rd] "=d" (result) : [rs] "d" (input)) 294#define CVMX_DCLZ(result, input) asm ("dclz %[rd],%[rs]" : [rd] "=d" (result) : [rs] "d" (input)) 295#define CVMX_CLO(result, input) asm ("clo %[rd],%[rs]" : [rd] "=d" (result) : [rs] "d" (input)) 296#define CVMX_DCLO(result, input) asm ("dclo %[rd],%[rs]" : [rd] "=d" (result) : [rs] "d" (input)) 297#define CVMX_POP(result, input) asm ("pop %[rd],%[rs]" : [rd] "=d" (result) : [rs] "d" (input)) 298#define CVMX_DPOP(result, input) asm ("dpop %[rd],%[rs]" : [rd] "=d" (result) : [rs] "d" (input)) 299 300#ifdef CVMX_ABI_O32 301 302 /* rdhwr $31 is the 64 bit cmvcount register, it needs to be split 303 into one or two (depending on the width of the result) properly 304 sign extended registers. All other registers are 32 bits wide 305 and already properly sign extended. */ 306# define CVMX_RDHWRX(result, regstr, ASM_STMT) ({ \ 307 if (regstr == 31) { \ 308 if (sizeof(result) == 8) { \ 309 ASM_STMT (".set\tpush\n" \ 310 "\t.set\tmips64r2\n" \ 311 "\trdhwr\t%L0,$31\n" \ 312 "\tdsra\t%M0,%L0,32\n" \ 313 "\tsll\t%L0,%L0,0\n" \ 314 "\t.set\tpop": "=d"(result)); \ 315 } else { \ 316 unsigned long _v; \ 317 ASM_STMT ("rdhwr\t%0,$31\n" \ 318 "\tsll\t%0,%0,0" : "=d"(_v)); \ 319 result = (__typeof(result))_v; \ 320 } \ 321 } else { \ 322 unsigned long _v; \ 323 ASM_STMT ("rdhwr\t%0,$" CVMX_TMP_STR(regstr) : "=d"(_v)); \ 324 result = (__typeof(result))_v; \ 325 }}) 326 327 328 329# define CVMX_RDHWR(result, regstr) CVMX_RDHWRX(result, regstr, asm volatile) 330# define CVMX_RDHWRNV(result, regstr) CVMX_RDHWRX(result, regstr, asm) 331#else 332# define CVMX_RDHWR(result, regstr) asm volatile ("rdhwr %[rt],$" CVMX_TMP_STR(regstr) : [rt] "=d" (result)) 333# define CVMX_RDHWRNV(result, regstr) asm ("rdhwr %[rt],$" CVMX_TMP_STR(regstr) : [rt] "=d" (result)) 334#endif 335 336// some new cop0-like stuff 337#define CVMX_DI(result) asm volatile ("di %[rt]" : [rt] "=d" (result)) 338#define CVMX_DI_NULL asm volatile ("di") 339#define CVMX_EI(result) asm volatile ("ei %[rt]" : [rt] "=d" (result)) 340#define CVMX_EI_NULL asm volatile ("ei") 341#define CVMX_EHB asm volatile ("ehb") 342 343/* mul stuff */ 344#define CVMX_MTM0(m) asm volatile ("mtm0 %[rs]" : : [rs] "d" (m)) 345#define CVMX_MTM1(m) asm volatile ("mtm1 %[rs]" : : [rs] "d" (m)) 346#define CVMX_MTM2(m) asm volatile ("mtm2 %[rs]" : : [rs] "d" (m)) 347#define CVMX_MTP0(p) asm volatile ("mtp0 %[rs]" : : [rs] "d" (p)) 348#define CVMX_MTP1(p) asm volatile ("mtp1 %[rs]" : : [rs] "d" (p)) 349#define CVMX_MTP2(p) asm volatile ("mtp2 %[rs]" : : [rs] "d" (p)) 350#define CVMX_VMULU(dest,mpcand,accum) asm volatile ("vmulu %[rd],%[rs],%[rt]" : [rd] "=d" (dest) : [rs] "d" (mpcand), [rt] "d" (accum)) 351#define CVMX_VMM0(dest,mpcand,accum) asm volatile ("vmm0 %[rd],%[rs],%[rt]" : [rd] "=d" (dest) : [rs] "d" (mpcand), [rt] "d" (accum)) 352#define CVMX_V3MULU(dest,mpcand,accum) asm volatile ("v3mulu %[rd],%[rs],%[rt]" : [rd] "=d" (dest) : [rs] "d" (mpcand), [rt] "d" (accum)) 353 354/* branch stuff */ 355// these are hard to make work because the compiler does not realize that the 356// instruction is a branch so may optimize away the label 357// the labels to these next two macros must not include a ":" at the end 358#define CVMX_BBIT1(var, pos, label) asm volatile ("bbit1 %[rs]," CVMX_TMP_STR(pos) "," CVMX_TMP_STR(label) : : [rs] "d" (var)) 359#define CVMX_BBIT0(var, pos, label) asm volatile ("bbit0 %[rs]," CVMX_TMP_STR(pos) "," CVMX_TMP_STR(label) : : [rs] "d" (var)) 360// the label to this macro must include a ":" at the end 361#define CVMX_ASM_LABEL(label) label \ 362 asm volatile (CVMX_TMP_STR(label) : : ) 363 364// 365// Low-latency memory stuff 366// 367// set can be 0-1 368#define CVMX_MT_LLM_READ_ADDR(set,val) asm volatile ("dmtc2 %[rt],0x0400+(8*(" CVMX_TMP_STR(set) "))" : : [rt] "d" (val)) 369#define CVMX_MT_LLM_WRITE_ADDR_INTERNAL(set,val) asm volatile ("dmtc2 %[rt],0x0401+(8*(" CVMX_TMP_STR(set) "))" : : [rt] "d" (val)) 370#define CVMX_MT_LLM_READ64_ADDR(set,val) asm volatile ("dmtc2 %[rt],0x0404+(8*(" CVMX_TMP_STR(set) "))" : : [rt] "d" (val)) 371#define CVMX_MT_LLM_WRITE64_ADDR_INTERNAL(set,val) asm volatile ("dmtc2 %[rt],0x0405+(8*(" CVMX_TMP_STR(set) "))" : : [rt] "d" (val)) 372#define CVMX_MT_LLM_DATA(set,val) asm volatile ("dmtc2 %[rt],0x0402+(8*(" CVMX_TMP_STR(set) "))" : : [rt] "d" (val)) 373#define CVMX_MF_LLM_DATA(set,val) asm volatile ("dmfc2 %[rt],0x0402+(8*(" CVMX_TMP_STR(set) "))" : [rt] "=d" (val) : ) 374 375 376// load linked, store conditional 377#define CVMX_LL(dest, address, offset) asm volatile ("ll %[rt], " CVMX_TMP_STR(offset) "(%[rbase])" : [rt] "=d" (dest) : [rbase] "d" (address) ) 378#define CVMX_LLD(dest, address, offset) asm volatile ("lld %[rt], " CVMX_TMP_STR(offset) "(%[rbase])" : [rt] "=d" (dest) : [rbase] "d" (address) ) 379#define CVMX_SC(srcdest, address, offset) asm volatile ("sc %[rt], " CVMX_TMP_STR(offset) "(%[rbase])" : [rt] "=d" (srcdest) : [rbase] "d" (address), "[rt]" (srcdest) ) 380#define CVMX_SCD(srcdest, address, offset) asm volatile ("scd %[rt], " CVMX_TMP_STR(offset) "(%[rbase])" : [rt] "=d" (srcdest) : [rbase] "d" (address), "[rt]" (srcdest) ) 381 382// load/store word left/right 383#define CVMX_LWR(srcdest, address, offset) asm volatile ("lwr %[rt], " CVMX_TMP_STR(offset) "(%[rbase])" : [rt] "=d" (srcdest) : [rbase] "d" (address), "[rt]" (srcdest) ) 384#define CVMX_LWL(srcdest, address, offset) asm volatile ("lwl %[rt], " CVMX_TMP_STR(offset) "(%[rbase])" : [rt] "=d" (srcdest) : [rbase] "d" (address), "[rt]" (srcdest) ) 385#define CVMX_LDR(srcdest, address, offset) asm volatile ("ldr %[rt], " CVMX_TMP_STR(offset) "(%[rbase])" : [rt] "=d" (srcdest) : [rbase] "d" (address), "[rt]" (srcdest) ) 386#define CVMX_LDL(srcdest, address, offset) asm volatile ("ldl %[rt], " CVMX_TMP_STR(offset) "(%[rbase])" : [rt] "=d" (srcdest) : [rbase] "d" (address), "[rt]" (srcdest) ) 387 388#define CVMX_SWR(src, address, offset) asm volatile ("swr %[rt], " CVMX_TMP_STR(offset) "(%[rbase])" : : [rbase] "d" (address), [rt] "d" (src) ) 389#define CVMX_SWL(src, address, offset) asm volatile ("swl %[rt], " CVMX_TMP_STR(offset) "(%[rbase])" : : [rbase] "d" (address), [rt] "d" (src) ) 390#define CVMX_SDR(src, address, offset) asm volatile ("sdr %[rt], " CVMX_TMP_STR(offset) "(%[rbase])" : : [rbase] "d" (address), [rt] "d" (src) ) 391#define CVMX_SDL(src, address, offset) asm volatile ("sdl %[rt], " CVMX_TMP_STR(offset) "(%[rbase])" : : [rbase] "d" (address), [rt] "d" (src) ) 392 393 394 395// 396// Useful crypto ASM's 397// 398 399// CRC 400 401#define CVMX_MT_CRC_POLYNOMIAL(val) asm volatile ("dmtc2 %[rt],0x4200" : : [rt] "d" (val)) 402#define CVMX_MT_CRC_IV(val) asm volatile ("dmtc2 %[rt],0x0201" : : [rt] "d" (val)) 403#define CVMX_MT_CRC_LEN(val) asm volatile ("dmtc2 %[rt],0x1202" : : [rt] "d" (val)) 404#define CVMX_MT_CRC_BYTE(val) asm volatile ("dmtc2 %[rt],0x0204" : : [rt] "d" (val)) 405#define CVMX_MT_CRC_HALF(val) asm volatile ("dmtc2 %[rt],0x0205" : : [rt] "d" (val)) 406#define CVMX_MT_CRC_WORD(val) asm volatile ("dmtc2 %[rt],0x0206" : : [rt] "d" (val)) 407#define CVMX_MT_CRC_DWORD(val) asm volatile ("dmtc2 %[rt],0x1207" : : [rt] "d" (val)) 408#define CVMX_MT_CRC_VAR(val) asm volatile ("dmtc2 %[rt],0x1208" : : [rt] "d" (val)) 409#define CVMX_MT_CRC_POLYNOMIAL_REFLECT(val) asm volatile ("dmtc2 %[rt],0x4210" : : [rt] "d" (val)) 410#define CVMX_MT_CRC_IV_REFLECT(val) asm volatile ("dmtc2 %[rt],0x0211" : : [rt] "d" (val)) 411#define CVMX_MT_CRC_BYTE_REFLECT(val) asm volatile ("dmtc2 %[rt],0x0214" : : [rt] "d" (val)) 412#define CVMX_MT_CRC_HALF_REFLECT(val) asm volatile ("dmtc2 %[rt],0x0215" : : [rt] "d" (val)) 413#define CVMX_MT_CRC_WORD_REFLECT(val) asm volatile ("dmtc2 %[rt],0x0216" : : [rt] "d" (val)) 414#define CVMX_MT_CRC_DWORD_REFLECT(val) asm volatile ("dmtc2 %[rt],0x1217" : : [rt] "d" (val)) 415#define CVMX_MT_CRC_VAR_REFLECT(val) asm volatile ("dmtc2 %[rt],0x1218" : : [rt] "d" (val)) 416 417#define CVMX_MF_CRC_POLYNOMIAL(val) asm volatile ("dmfc2 %[rt],0x0200" : [rt] "=d" (val) : ) 418#define CVMX_MF_CRC_IV(val) asm volatile ("dmfc2 %[rt],0x0201" : [rt] "=d" (val) : ) 419#define CVMX_MF_CRC_IV_REFLECT(val) asm volatile ("dmfc2 %[rt],0x0203" : [rt] "=d" (val) : ) 420#define CVMX_MF_CRC_LEN(val) asm volatile ("dmfc2 %[rt],0x0202" : [rt] "=d" (val) : ) 421 422// MD5 and SHA-1 423 424// pos can be 0-6 425#define CVMX_MT_HSH_DAT(val,pos) asm volatile ("dmtc2 %[rt],0x0040+" CVMX_TMP_STR(pos) : : [rt] "d" (val)) 426#define CVMX_MT_HSH_DATZ(pos) asm volatile ("dmtc2 $0,0x0040+" CVMX_TMP_STR(pos) : : ) 427// pos can be 0-14 428#define CVMX_MT_HSH_DATW(val,pos) asm volatile ("dmtc2 %[rt],0x0240+" CVMX_TMP_STR(pos) : : [rt] "d" (val)) 429#define CVMX_MT_HSH_DATWZ(pos) asm volatile ("dmtc2 $0,0x0240+" CVMX_TMP_STR(pos) : : ) 430#define CVMX_MT_HSH_STARTMD5(val) asm volatile ("dmtc2 %[rt],0x4047" : : [rt] "d" (val)) 431#define CVMX_MT_HSH_STARTSHA(val) asm volatile ("dmtc2 %[rt],0x4057" : : [rt] "d" (val)) 432#define CVMX_MT_HSH_STARTSHA256(val) asm volatile ("dmtc2 %[rt],0x404f" : : [rt] "d" (val)) 433#define CVMX_MT_HSH_STARTSHA512(val) asm volatile ("dmtc2 %[rt],0x424f" : : [rt] "d" (val)) 434// pos can be 0-3 435#define CVMX_MT_HSH_IV(val,pos) asm volatile ("dmtc2 %[rt],0x0048+" CVMX_TMP_STR(pos) : : [rt] "d" (val)) 436// pos can be 0-7 437#define CVMX_MT_HSH_IVW(val,pos) asm volatile ("dmtc2 %[rt],0x0250+" CVMX_TMP_STR(pos) : : [rt] "d" (val)) 438 439// pos can be 0-6 440#define CVMX_MF_HSH_DAT(val,pos) asm volatile ("dmfc2 %[rt],0x0040+" CVMX_TMP_STR(pos) : [rt] "=d" (val) : ) 441// pos can be 0-14 442#define CVMX_MF_HSH_DATW(val,pos) asm volatile ("dmfc2 %[rt],0x0240+" CVMX_TMP_STR(pos) : [rt] "=d" (val) : ) 443// pos can be 0-3 444#define CVMX_MF_HSH_IV(val,pos) asm volatile ("dmfc2 %[rt],0x0048+" CVMX_TMP_STR(pos) : [rt] "=d" (val) : ) 445// pos can be 0-7 446#define CVMX_MF_HSH_IVW(val,pos) asm volatile ("dmfc2 %[rt],0x0250+" CVMX_TMP_STR(pos) : [rt] "=d" (val) : ) 447 448// 3DES 449 450// pos can be 0-2 451#define CVMX_MT_3DES_KEY(val,pos) asm volatile ("dmtc2 %[rt],0x0080+" CVMX_TMP_STR(pos) : : [rt] "d" (val)) 452#define CVMX_MT_3DES_IV(val) asm volatile ("dmtc2 %[rt],0x0084" : : [rt] "d" (val)) 453#define CVMX_MT_3DES_ENC_CBC(val) asm volatile ("dmtc2 %[rt],0x4088" : : [rt] "d" (val)) 454#define CVMX_MT_3DES_ENC(val) asm volatile ("dmtc2 %[rt],0x408a" : : [rt] "d" (val)) 455#define CVMX_MT_3DES_DEC_CBC(val) asm volatile ("dmtc2 %[rt],0x408c" : : [rt] "d" (val)) 456#define CVMX_MT_3DES_DEC(val) asm volatile ("dmtc2 %[rt],0x408e" : : [rt] "d" (val)) 457#define CVMX_MT_3DES_RESULT(val) asm volatile ("dmtc2 %[rt],0x0098" : : [rt] "d" (val)) 458 459// pos can be 0-2 460#define CVMX_MF_3DES_KEY(val,pos) asm volatile ("dmfc2 %[rt],0x0080+" CVMX_TMP_STR(pos) : [rt] "=d" (val) : ) 461#define CVMX_MF_3DES_IV(val) asm volatile ("dmfc2 %[rt],0x0084" : [rt] "=d" (val) : ) 462#define CVMX_MF_3DES_RESULT(val) asm volatile ("dmfc2 %[rt],0x0088" : [rt] "=d" (val) : ) 463 464// KASUMI 465 466// pos can be 0-1 467#define CVMX_MT_KAS_KEY(val,pos) CVMX_MT_3DES_KEY(val,pos) 468#define CVMX_MT_KAS_ENC_CBC(val) asm volatile ("dmtc2 %[rt],0x4089" : : [rt] "d" (val)) 469#define CVMX_MT_KAS_ENC(val) asm volatile ("dmtc2 %[rt],0x408b" : : [rt] "d" (val)) 470#define CVMX_MT_KAS_RESULT(val) CVMX_MT_3DES_RESULT(val) 471 472// pos can be 0-1 473#define CVMX_MF_KAS_KEY(val,pos) CVMX_MF_3DES_KEY(val,pos) 474#define CVMX_MF_KAS_RESULT(val) CVMX_MF_3DES_RESULT(val) 475 476// AES 477 478#define CVMX_MT_AES_ENC_CBC0(val) asm volatile ("dmtc2 %[rt],0x0108" : : [rt] "d" (val)) 479#define CVMX_MT_AES_ENC_CBC1(val) asm volatile ("dmtc2 %[rt],0x3109" : : [rt] "d" (val)) 480#define CVMX_MT_AES_ENC0(val) asm volatile ("dmtc2 %[rt],0x010a" : : [rt] "d" (val)) 481#define CVMX_MT_AES_ENC1(val) asm volatile ("dmtc2 %[rt],0x310b" : : [rt] "d" (val)) 482#define CVMX_MT_AES_DEC_CBC0(val) asm volatile ("dmtc2 %[rt],0x010c" : : [rt] "d" (val)) 483#define CVMX_MT_AES_DEC_CBC1(val) asm volatile ("dmtc2 %[rt],0x310d" : : [rt] "d" (val)) 484#define CVMX_MT_AES_DEC0(val) asm volatile ("dmtc2 %[rt],0x010e" : : [rt] "d" (val)) 485#define CVMX_MT_AES_DEC1(val) asm volatile ("dmtc2 %[rt],0x310f" : : [rt] "d" (val)) 486// pos can be 0-3 487#define CVMX_MT_AES_KEY(val,pos) asm volatile ("dmtc2 %[rt],0x0104+" CVMX_TMP_STR(pos) : : [rt] "d" (val)) 488// pos can be 0-1 489#define CVMX_MT_AES_IV(val,pos) asm volatile ("dmtc2 %[rt],0x0102+" CVMX_TMP_STR(pos) : : [rt] "d" (val)) 490#define CVMX_MT_AES_KEYLENGTH(val) asm volatile ("dmtc2 %[rt],0x0110" : : [rt] "d" (val)) // write the keylen 491// pos can be 0-1 492#define CVMX_MT_AES_RESULT(val,pos) asm volatile ("dmtc2 %[rt],0x0100+" CVMX_TMP_STR(pos) : : [rt] "d" (val)) 493 494// pos can be 0-1 495#define CVMX_MF_AES_RESULT(val,pos) asm volatile ("dmfc2 %[rt],0x0100+" CVMX_TMP_STR(pos) : [rt] "=d" (val) : ) 496// pos can be 0-1 497#define CVMX_MF_AES_IV(val,pos) asm volatile ("dmfc2 %[rt],0x0102+" CVMX_TMP_STR(pos) : [rt] "=d" (val) : ) 498// pos can be 0-3 499#define CVMX_MF_AES_KEY(val,pos) asm volatile ("dmfc2 %[rt],0x0104+" CVMX_TMP_STR(pos) : [rt] "=d" (val) : ) 500#define CVMX_MF_AES_KEYLENGTH(val) asm volatile ("dmfc2 %[rt],0x0110" : [rt] "=d" (val) : ) // read the keylen 501#define CVMX_MF_AES_DAT0(val) asm volatile ("dmfc2 %[rt],0x0111" : [rt] "=d" (val) : ) // first piece of input data 502 503// GFM 504 505// pos can be 0-1 506#define CVMX_MF_GFM_MUL(val,pos) asm volatile ("dmfc2 %[rt],0x0258+" CVMX_TMP_STR(pos) : [rt] "=d" (val) : ) 507#define CVMX_MF_GFM_POLY(val) asm volatile ("dmfc2 %[rt],0x025e" : [rt] "=d" (val) : ) 508// pos can be 0-1 509#define CVMX_MF_GFM_RESINP(val,pos) asm volatile ("dmfc2 %[rt],0x025a+" CVMX_TMP_STR(pos) : [rt] "=d" (val) : ) 510// pos can be 0-1 511#define CVMX_MF_GFM_RESINP_REFLECT(val,pos) asm volatile ("dmfc2 %[rt],0x005a+" CVMX_TMP_STR(pos) : [rt] "=d" (val) : ) 512 513// pos can be 0-1 514#define CVMX_MT_GFM_MUL(val,pos) asm volatile ("dmtc2 %[rt],0x0258+" CVMX_TMP_STR(pos) : : [rt] "d" (val)) 515#define CVMX_MT_GFM_POLY(val) asm volatile ("dmtc2 %[rt],0x025e" : : [rt] "d" (val)) 516// pos can be 0-1 517#define CVMX_MT_GFM_RESINP(val,pos) asm volatile ("dmtc2 %[rt],0x025a+" CVMX_TMP_STR(pos) : : [rt] "d" (val)) 518#define CVMX_MT_GFM_XOR0(val) asm volatile ("dmtc2 %[rt],0x025c" : : [rt] "d" (val)) 519#define CVMX_MT_GFM_XORMUL1(val) asm volatile ("dmtc2 %[rt],0x425d" : : [rt] "d" (val)) 520// pos can be 0-1 521#define CVMX_MT_GFM_MUL_REFLECT(val,pos) asm volatile ("dmtc2 %[rt],0x0058+" CVMX_TMP_STR(pos) : [rt] "=d" (val) : ) 522#define CVMX_MT_GFM_XOR0_REFLECT(val) asm volatile ("dmtc2 %[rt],0x005c" : : [rt] "d" (val)) 523#define CVMX_MT_GFM_XORMUL1_REFLECT(val) asm volatile ("dmtc2 %[rt],0x405d" : : [rt] "d" (val)) 524 525// SNOW 3G 526 527// pos can be 0-7 528#define CVMX_MF_SNOW3G_LFSR(val,pos) asm volatile ("dmfc2 %[rt],0x0240+" CVMX_TMP_STR(pos) : [rt] "=d" (val) : ) 529// pos can be 0-2 530#define CVMX_MF_SNOW3G_FSM(val,pos) asm volatile ("dmfc2 %[rt],0x0251+" CVMX_TMP_STR(pos) : [rt] "=d" (val) : ) 531#define CVMX_MF_SNOW3G_RESULT(val) asm volatile ("dmfc2 %[rt],0x0250" : [rt] "=d" (val) : ) 532 533// pos can be 0-7 534#define CVMX_MT_SNOW3G_LFSR(val,pos) asm volatile ("dmtc2 %[rt],0x0240+" CVMX_TMP_STR(pos) : : [rt] "d" (val)) 535// pos can be 0-2 536#define CVMX_MT_SNOW3G_FSM(val,pos) asm volatile ("dmtc2 %[rt],0x0251+" CVMX_TMP_STR(pos) : : [rt] "d" (val)) 537#define CVMX_MT_SNOW3G_RESULT(val) asm volatile ("dmtc2 %[rt],0x0250" : : [rt] "d" (val)) 538#define CVMX_MT_SNOW3G_START(val) asm volatile ("dmtc2 %[rt],0x404d" : : [rt] "d" (val)) 539#define CVMX_MT_SNOW3G_MORE(val) asm volatile ("dmtc2 %[rt],0x404e" : : [rt] "d" (val)) 540 541// SMS4 542 543// pos can be 0-1 544#define CVMX_MF_SMS4_IV(val,pos) asm volatile ("dmfc2 %[rt],0x0102+"CVMX_TMP_STR(pos) : [rt] "=d" (val) : ) 545// pos can be 0-1 546#define CVMX_MF_SMS4_KEY(val,pos) asm volatile ("dmfc2 %[rt],0x0104+"CVMX_TMP_STR(pos) : [rt] "=d" (val) : ) 547// pos can be 0-1 548#define CVMX_MF_SMS4_RESINP(val,pos) asm volatile ("dmfc2 %[rt],0x0100+"CVMX_TMP_STR(pos) : [rt] "=d" (val) : ) 549#define CVMX_MT_SMS4_DEC_CBC0(val) asm volatile ("dmtc2 %[rt],0x010c" : : [rt] "d" (val)) 550#define CVMX_MT_SMS4_DEC_CBC1(val) asm volatile ("dmtc2 %[rt],0x311d" : : [rt] "d" (val)) 551#define CVMX_MT_SMS4_DEC0(val) asm volatile ("dmtc2 %[rt],0x010e" : : [rt] "d" (val)) 552#define CVMX_MT_SMS4_DEC1(val) asm volatile ("dmtc2 %[rt],0x311f" : : [rt] "d" (val)) 553#define CVMX_MT_SMS4_ENC_CBC0(val) asm volatile ("dmtc2 %[rt],0x0108" : : [rt] "d" (val)) 554#define CVMX_MT_SMS4_ENC_CBC1(val) asm volatile ("dmtc2 %[rt],0x3119" : : [rt] "d" (val)) 555#define CVMX_MT_SMS4_ENC0(val) asm volatile ("dmtc2 %[rt],0x010a" : : [rt] "d" (val)) 556#define CVMX_MT_SMS4_ENC1(val) asm volatile ("dmtc2 %[rt],0x311b" : : [rt] "d" (val)) 557// pos can be 0-1 558#define CVMX_MT_SMS4_IV(val,pos) asm volatile ("dmtc2 %[rt],0x0102+"CVMX_TMP_STR(pos) : : [rt] "d" (val)) 559// pos can be 0-1 560#define CVMX_MT_SMS4_KEY(val,pos) asm volatile ("dmtc2 %[rt],0x0104+"CVMX_TMP_STR(pos) : : [rt] "d" (val)) 561// pos can be 0-1 562#define CVMX_MT_SMS4_RESINP(val,pos) asm volatile ("dmtc2 %[rt],0x0100+"CVMX_TMP_STR(pos) : : [rt] "d" (val)) 563 564/* check_ordering stuff */ 565#if 0 566#define CVMX_MF_CHORD(dest) asm volatile ("dmfc2 %[rt],0x400" : [rt] "=d" (dest) : ) 567#else 568#define CVMX_MF_CHORD(dest) CVMX_RDHWR(dest, 30) 569#endif 570 571#if 0 572#define CVMX_MF_CYCLE(dest) asm volatile ("dmfc0 %[rt],$9,6" : [rt] "=d" (dest) : ) // Use (64-bit) CvmCount register rather than Count 573#else 574#define CVMX_MF_CYCLE(dest) CVMX_RDHWR(dest, 31) /* reads the current (64-bit) CvmCount value */ 575#endif 576 577#define CVMX_MT_CYCLE(src) asm volatile ("dmtc0 %[rt],$9,6" :: [rt] "d" (src)) 578 579#define VASTR(...) #__VA_ARGS__ 580 581#define CVMX_MF_COP0(val, cop0) asm volatile ("dmfc0 %[rt]," VASTR(cop0) : [rt] "=d" (val)); 582#define CVMX_MT_COP0(val, cop0) asm volatile ("dmtc0 %[rt]," VASTR(cop0) : : [rt] "d" (val)); 583 584#define CVMX_MF_CACHE_ERR(val) CVMX_MF_COP0(val, COP0_CACHEERRI) 585#define CVMX_MF_DCACHE_ERR(val) CVMX_MF_COP0(val, COP0_CACHEERRD) 586#define CVMX_MF_CVM_MEM_CTL(val) CVMX_MF_COP0(val, COP0_CVMMEMCTL) 587#define CVMX_MF_CVM_CTL(val) CVMX_MF_COP0(val, COP0_CVMCTL) 588#define CVMX_MT_CACHE_ERR(val) CVMX_MT_COP0(val, COP0_CACHEERRI) 589#define CVMX_MT_DCACHE_ERR(val) CVMX_MT_COP0(val, COP0_CACHEERRD) 590#define CVMX_MT_CVM_MEM_CTL(val) CVMX_MT_COP0(val, COP0_CVMMEMCTL) 591#define CVMX_MT_CVM_CTL(val) CVMX_MT_COP0(val, COP0_CVMCTL) 592 593/* Macros for TLB */ 594#define CVMX_TLBWI asm volatile ("tlbwi" : : ) 595#define CVMX_TLBWR asm volatile ("tlbwr" : : ) 596#define CVMX_TLBR asm volatile ("tlbr" : : ) 597#define CVMX_TLBP asm volatile ("tlbp" : : ) 598#define CVMX_MT_ENTRY_HIGH(val) asm volatile ("dmtc0 %[rt],$10,0" : : [rt] "d" (val)) 599#define CVMX_MT_ENTRY_LO_0(val) asm volatile ("dmtc0 %[rt],$2,0" : : [rt] "d" (val)) 600#define CVMX_MT_ENTRY_LO_1(val) asm volatile ("dmtc0 %[rt],$3,0" : : [rt] "d" (val)) 601#define CVMX_MT_PAGEMASK(val) asm volatile ("mtc0 %[rt],$5,0" : : [rt] "d" (val)) 602#define CVMX_MT_PAGEGRAIN(val) asm volatile ("mtc0 %[rt],$5,1" : : [rt] "d" (val)) 603#define CVMX_MT_TLB_INDEX(val) asm volatile ("mtc0 %[rt],$0,0" : : [rt] "d" (val)) 604#define CVMX_MT_TLB_CONTEXT(val) asm volatile ("dmtc0 %[rt],$4,0" : : [rt] "d" (val)) 605#define CVMX_MT_TLB_WIRED(val) asm volatile ("mtc0 %[rt],$6,0" : : [rt] "d" (val)) 606#define CVMX_MT_TLB_RANDOM(val) asm volatile ("mtc0 %[rt],$1,0" : : [rt] "d" (val)) 607#define CVMX_MF_ENTRY_LO_0(val) asm volatile ("dmfc0 %[rt],$2,0" : [rt] "=d" (val):) 608#define CVMX_MF_ENTRY_LO_1(val) asm volatile ("dmfc0 %[rt],$3,0" : [rt] "=d" (val):) 609#define CVMX_MF_ENTRY_HIGH(val) asm volatile ("dmfc0 %[rt],$10,0" : [rt] "=d" (val):) 610#define CVMX_MF_PAGEMASK(val) asm volatile ("mfc0 %[rt],$5,0" : [rt] "=d" (val):) 611#define CVMX_MF_PAGEGRAIN(val) asm volatile ("mfc0 %[rt],$5,1" : [rt] "=d" (val):) 612#define CVMX_MF_TLB_WIRED(val) asm volatile ("mfc0 %[rt],$6,0" : [rt] "=d" (val):) 613#define CVMX_MF_TLB_INDEX(val) asm volatile ("mfc0 %[rt],$0,0" : [rt] "=d" (val):) 614#define CVMX_MF_TLB_RANDOM(val) asm volatile ("mfc0 %[rt],$1,0" : [rt] "=d" (val):) 615#define TLB_DIRTY (0x1ULL<<2) 616#define TLB_VALID (0x1ULL<<1) 617#define TLB_GLOBAL (0x1ULL<<0) 618 619 620#if !defined(__FreeBSD__) || !defined(_KERNEL) 621/* Macros to PUSH and POP Octeon2 ISA. */ 622#define CVMX_PUSH_OCTEON2 asm volatile (".set push\n.set arch=octeon2") 623#define CVMX_POP_OCTEON2 asm volatile (".set pop") 624#endif 625 626/* assembler macros to guarantee byte loads/stores are used */ 627/* for an unaligned 16-bit access (these use AT register) */ 628/* we need the hidden argument (__a) so that GCC gets the dependencies right */ 629#define CVMX_LOADUNA_INT16(result, address, offset) \ 630 { char *__a = (char *)(address); \ 631 asm ("ulh %[rdest], " CVMX_TMP_STR(offset) "(%[rbase])" : [rdest] "=d" (result) : [rbase] "d" (__a), "m"(__a[offset]), "m"(__a[offset + 1])); } 632#define CVMX_LOADUNA_UINT16(result, address, offset) \ 633 { char *__a = (char *)(address); \ 634 asm ("ulhu %[rdest], " CVMX_TMP_STR(offset) "(%[rbase])" : [rdest] "=d" (result) : [rbase] "d" (__a), "m"(__a[offset + 0]), "m"(__a[offset + 1])); } 635#define CVMX_STOREUNA_INT16(data, address, offset) \ 636 { char *__a = (char *)(address); \ 637 asm ("ush %[rsrc], " CVMX_TMP_STR(offset) "(%[rbase])" : "=m"(__a[offset + 0]), "=m"(__a[offset + 1]): [rsrc] "d" (data), [rbase] "d" (__a)); } 638 639#define CVMX_LOADUNA_INT32(result, address, offset) \ 640 { char *__a = (char *)(address); \ 641 asm ("ulw %[rdest], " CVMX_TMP_STR(offset) "(%[rbase])" : [rdest] "=d" (result) : \ 642 [rbase] "d" (__a), "m"(__a[offset + 0]), "m"(__a[offset + 1]), "m"(__a[offset + 2]), "m"(__a[offset + 3])); } 643#define CVMX_STOREUNA_INT32(data, address, offset) \ 644 { char *__a = (char *)(address); \ 645 asm ("usw %[rsrc], " CVMX_TMP_STR(offset) "(%[rbase])" : \ 646 "=m"(__a[offset + 0]), "=m"(__a[offset + 1]), "=m"(__a[offset + 2]), "=m"(__a[offset + 3]) : \ 647 [rsrc] "d" (data), [rbase] "d" (__a)); } 648 649#define CVMX_LOADUNA_INT64(result, address, offset) \ 650 { char *__a = (char *)(address); \ 651 asm ("uld %[rdest], " CVMX_TMP_STR(offset) "(%[rbase])" : [rdest] "=d" (result) : \ 652 [rbase] "d" (__a), "m"(__a[offset + 0]), "m"(__a[offset + 1]), "m"(__a[offset + 2]), "m"(__a[offset + 3]), \ 653 "m"(__a[offset + 4]), "m"(__a[offset + 5]), "m"(__a[offset + 6]), "m"(__a[offset + 7])); } 654#define CVMX_STOREUNA_INT64(data, address, offset) \ 655 { char *__a = (char *)(address); \ 656 asm ("usd %[rsrc], " CVMX_TMP_STR(offset) "(%[rbase])" : \ 657 "=m"(__a[offset + 0]), "=m"(__a[offset + 1]), "=m"(__a[offset + 2]), "=m"(__a[offset + 3]), \ 658 "=m"(__a[offset + 4]), "=m"(__a[offset + 5]), "=m"(__a[offset + 6]), "=m"(__a[offset + 7]) : \ 659 [rsrc] "d" (data), [rbase] "d" (__a)); } 660 661#ifdef __cplusplus 662} 663#endif 664 665#endif /* __ASSEMBLER__ */ 666 667#endif /* __CVMX_ASM_H__ */ 668