cvmx-access.h revision 210284 
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38
39/**
40 * @file
41 * Function prototypes for accessing memory and CSRs on Octeon.
42 *
43 * <hr>$Revision: 38306 $<hr>
44*/
45#ifndef __CVMX_ACCESS_H__
46#define __CVMX_ACCESS_H__
47
48#ifdef	__cplusplus
49extern "C" {
50#endif
51
52/* We're going to assume that if we are compiling for Mips then we must be
53    running natively on Octoen. It is possible that this code could be
54    compiled on a non Octeon Mips that is acting as a PCI/PCIe host. In this
55    case this assumption will be wrong and cause issues We can't key off of
56    __octeon__ since some people use stock gcc toolchains */
57#if defined(__mips__) && !defined(CVMX_BUILD_FOR_LINUX_HOST)
58    #define CVMX_FUNCTION static inline
59#else
60    #define CVMX_FUNCTION extern
61#endif
62
63/**
64 * simprintf uses simulator tricks to speed up printouts.  The format
65 * and args are passed to the simulator and processed natively on the host.
66 * Simprintf is limited to 7 arguments, and they all must use %ll (long long)
67 * format specifiers to be displayed correctly.
68 *
69 * @param format
70 *
71 * @return
72 */
73EXTERN_ASM void simprintf(const char *format, ...);
74
75/**
76 * This function performs some default initialization of the Octeon executive.
77 * It initializes the cvmx_bootmem memory allocator with the list of physical
78 * memory provided by the bootloader, and creates 1-1 TLB mappings for this
79 * memory. This function should be called on all cores that will use either the
80 * bootmem allocator or the 1-1 TLB mappings. Applications which require a
81 * different configuration can replace this function with a suitable application
82 * specific one.
83 *
84 * @return 0 on success
85 *         -1 on failure
86 */
87extern int cvmx_user_app_init(void);
88
89/**
90 * Returns the Octeon processor ID.
91 *
92 * @return Octeon processor ID from COP0
93 */
94CVMX_FUNCTION uint32_t cvmx_get_proc_id(void) __attribute__ ((pure));
95
96/**
97 * Convert a memory pointer (void*) into a hardware compatable
98 * memory address (uint64_t). Octeon hardware widgets don't
99 * understand logical addresses.
100 *
101 * @param ptr    C style memory pointer
102 * @return Hardware physical address
103 */
104CVMX_FUNCTION uint64_t cvmx_ptr_to_phys(void *ptr);
105
106/**
107 * Convert a hardware physical address (uint64_t) into a
108 * memory pointer (void *).
109 *
110 * @param physical_address
111 *               Hardware physical address to memory
112 * @return Pointer to memory
113 */
114CVMX_FUNCTION void *cvmx_phys_to_ptr(uint64_t physical_address);
115
116CVMX_FUNCTION void cvmx_write64_int64(uint64_t address, int64_t value);
117CVMX_FUNCTION void cvmx_write64_uint64(uint64_t address, uint64_t value);
118CVMX_FUNCTION void cvmx_write64_int32(uint64_t address, int32_t value);
119CVMX_FUNCTION void cvmx_write64_uint32(uint64_t address, uint32_t value);
120CVMX_FUNCTION void cvmx_write64_int16(uint64_t address, int16_t value);
121CVMX_FUNCTION void cvmx_write64_uint16(uint64_t address, uint16_t value);
122CVMX_FUNCTION void cvmx_write64_int8(uint64_t address, int8_t value);
123CVMX_FUNCTION void cvmx_write64_uint8(uint64_t address, uint8_t value);
124CVMX_FUNCTION void cvmx_write_csr(uint64_t csr_addr, uint64_t val);
125CVMX_FUNCTION void cvmx_write_io(uint64_t io_addr, uint64_t val);
126
127CVMX_FUNCTION int64_t cvmx_read64_int64(uint64_t address);
128CVMX_FUNCTION uint64_t cvmx_read64_uint64(uint64_t address);
129CVMX_FUNCTION int32_t cvmx_read64_int32(uint64_t address);
130CVMX_FUNCTION uint32_t cvmx_read64_uint32(uint64_t address);
131CVMX_FUNCTION int16_t cvmx_read64_int16(uint64_t address);
132CVMX_FUNCTION uint16_t cvmx_read64_uint16(uint64_t address);
133CVMX_FUNCTION int8_t cvmx_read64_int8(uint64_t address);
134CVMX_FUNCTION uint8_t cvmx_read64_uint8(uint64_t address);
135CVMX_FUNCTION uint64_t cvmx_read_csr(uint64_t csr_addr);
136
137CVMX_FUNCTION void cvmx_send_single(uint64_t data);
138CVMX_FUNCTION void cvmx_read_csr_async(uint64_t scraddr, uint64_t csr_addr);
139
140/**
141 * Number of the Core on which the program is currently running.
142 *
143 * @return Number of cores
144 */
145CVMX_FUNCTION unsigned int cvmx_get_core_num(void);
146
147/**
148 * Returns the number of bits set in the provided value.
149 * Simple wrapper for POP instruction.
150 *
151 * @param val    32 bit value to count set bits in
152 *
153 * @return Number of bits set
154 */
155CVMX_FUNCTION uint32_t cvmx_pop(uint32_t val);
156
157/**
158 * Returns the number of bits set in the provided value.
159 * Simple wrapper for DPOP instruction.
160 *
161 * @param val    64 bit value to count set bits in
162 *
163 * @return Number of bits set
164 */
165CVMX_FUNCTION int cvmx_dpop(uint64_t val);
166
167/**
168 * Provide current cycle counter as a return value
169 *
170 * @return current cycle counter
171 */
172CVMX_FUNCTION uint64_t cvmx_get_cycle(void);
173
174/**
175 * Reads a chip global cycle counter.  This counts CPU cycles since
176 * chip reset.  The counter is 64 bit.
177 * This register does not exist on CN38XX pass 1 silicion
178 *
179 * @return Global chip cycle count since chip reset.
180 */
181CVMX_FUNCTION uint64_t cvmx_get_cycle_global(void);
182
183/**
184 * Wait for the specified number of cycle
185 *
186 * @param cycles
187 */
188CVMX_FUNCTION void cvmx_wait(uint64_t cycles);
189
190/**
191 * Wait for the specified number of micro seconds
192 *
193 * @param usec   micro seconds to wait
194 */
195CVMX_FUNCTION void cvmx_wait_usec(uint64_t usec);
196
197/**
198 * Perform a soft reset of Octeon
199 *
200 * @return
201 */
202CVMX_FUNCTION void cvmx_reset_octeon(void);
203
204/**
205 * Read a byte of fuse data
206 * @param byte_addr   address to read
207 *
208 * @return fuse value: 0 or 1
209 */
210CVMX_FUNCTION uint8_t cvmx_fuse_read_byte(int byte_addr);
211
212/**
213 * Read a single fuse bit
214 *
215 * @param fuse   Fuse number (0-1024)
216 *
217 * @return fuse value: 0 or 1
218 */
219CVMX_FUNCTION int cvmx_fuse_read(int fuse);
220
221#undef CVMX_FUNCTION
222
223#ifdef	__cplusplus
224}
225#endif
226
227#endif /* __CVMX_ACCESS_H__ */
228
229