167754Smsmith/* 267754Smsmith * Copyright (c) 2013 Qualcomm Atheros, Inc. 367754Smsmith * 467754Smsmith * Permission to use, copy, modify, and/or distribute this software for any 567754Smsmith * purpose with or without fee is hereby granted, provided that the above 667754Smsmith * copyright notice and this permission notice appear in all copies. 767754Smsmith * 867754Smsmith * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH 967754Smsmith * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY 1067754Smsmith * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, 1167754Smsmith * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM 12193267Sjkim * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR 1370243Smsmith * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 1467754Smsmith * PERFORMANCE OF THIS SOFTWARE. 1567754Smsmith */ 1667754Smsmith 1767754Smsmith/* 1867754Smsmith * READ THIS NOTICE! 1967754Smsmith * 2067754Smsmith * Values defined in this file may only be changed under exceptional circumstances. 2167754Smsmith * 2267754Smsmith * Please ask Fiona Cain before making any changes. 2367754Smsmith */ 2467754Smsmith 2567754Smsmith#ifndef __ar9300templateXB112_h__ 2667754Smsmith#define __ar9300templateXB112_h__ 2767754Smsmith 2867754Smsmithstatic ar9300_eeprom_t ar9300_template_xb112= 2967754Smsmith{ 3067754Smsmith 3167754Smsmith 2, // eeprom_version; 3267754Smsmith 3367754Smsmith ar9300_eeprom_template_xb112, // template_version; 3467754Smsmith 3567754Smsmith {0x00,0x03,0x7f,0x0,0x0,0x0}, //mac_addr[6]; 3667754Smsmith 3767754Smsmith //static A_UINT8 custData[OSPREY_CUSTOMER_DATA_SIZE]= 3867754Smsmith 3967754Smsmith {"xb112-041-f0000"}, 4067754Smsmith// {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, 4167754Smsmith 4267754Smsmith //static OSPREY_BASE_EEP_HEADER base_eep_header= 4367754Smsmith 4467754Smsmith { 4567754Smsmith {0,0x1f}, // reg_dmn[2]; //Does this need to be outside of this structure, if it gets written after calibration 4667754Smsmith 0x77, // txrx_mask; //4 bits tx and 4 bits rx 4767754Smsmith {AR9300_OPFLAGS_11G | AR9300_OPFLAGS_11A, 0}, // op_cap_flags; 4867754Smsmith 0, // rf_silent; 4967754Smsmith 0, // blue_tooth_options; 5067754Smsmith 0, // device_cap; 5167754Smsmith 5, // device_type; // takes lower byte in eeprom location 5267754Smsmith OSPREY_PWR_TABLE_OFFSET, // pwrTableOffset; // offset in dB to be added to beginning of pdadc table in calibration 5367754Smsmith {0,0}, // params_for_tuning_caps[2]; //placeholder, get more details from Don 5467754Smsmith 0x0d, //feature_enable; //bit0 - enable tx temp comp 5567754Smsmith //bit1 - enable tx volt comp 5667754Smsmith //bit2 - enable fastClock - default to 1 5767754Smsmith //bit3 - enable doubling - default to 1 5867754Smsmith //bit4 - enable internal regulator - default to 0 5967754Smsmith //bit5 - enable paprd -- default to 0 6067754Smsmith 0, //misc_configuration: bit0 - turn down drivestrength 6167754Smsmith 6, // eeprom_write_enable_gpio 6267754Smsmith 0, // wlan_disable_gpio 6367754Smsmith 8, // wlan_led_gpio 6467754Smsmith 0xff, // rx_band_select_gpio 6567754Smsmith 0, // txrxgain 6667754Smsmith 0, // swreg 6767754Smsmith }, 6867754Smsmith 6967754Smsmith 7067754Smsmith //static OSPREY_MODAL_EEP_HEADER modal_header_2g= 7167754Smsmith { 7267754Smsmith 7367754Smsmith 0x110, // ant_ctrl_common; // 4 idle, t1, t2, b (4 bits per setting) 7467754Smsmith 0x22222, // ant_ctrl_common2; // 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 7567754Smsmith {0x10,0x10,0x10}, // ant_ctrl_chain[OSPREY_MAX_CHAINS]; // 6 idle, t, r, rx1, rx12, b (2 bits each) 7667754Smsmith {0x1b,0x1b,0x1b}, // xatten1_db[OSPREY_MAX_CHAINS]; // 3 //xatten1_db for merlin (0xa20c/b20c 5:0) 7767754Smsmith {0x15,0x15,0x15}, // xatten1_margin[OSPREY_MAX_CHAINS]; // 3 //xatten1_margin for merlin (0xa20c/b20c 16:12 7867754Smsmith 50, // temp_slope; 7967754Smsmith 0, // voltSlope; 8067754Smsmith {FREQ2FBIN(2464, 1),0,0,0,0}, // spur_chans[OSPREY_EEPROM_MODAL_SPURS]; // spur channels in usual fbin coding format 8167754Smsmith {-1,0,0}, // noise_floor_thresh_ch[OSPREY_MAX_CHAINS]; // 3 //Check if the register is per chain 8267754Smsmith {0, 0, 0, 0, 0, 0,0,0,0,0,0}, // reserved 8367754Smsmith 0, // quick drop 8467754Smsmith 0, // xpa_bias_lvl; // 1 8567754Smsmith 0x0e, // tx_frame_to_data_start; // 1 8667754Smsmith 0x0e, // tx_frame_to_pa_on; // 1 8767754Smsmith 3, // txClip; // 4 bits tx_clip, 4 bits dac_scale_cck 8867754Smsmith 0, // antenna_gain; // 1 8967754Smsmith 0x2c, // switchSettling; // 1 9067754Smsmith -30, // adcDesiredSize; // 1 9167754Smsmith 0, // txEndToXpaOff; // 1 9267754Smsmith 0x2, // txEndToRxOn; // 1 9367754Smsmith 0xe, // tx_frame_to_xpa_on; // 1 9467754Smsmith 28, // thresh62; // 1 9567754Smsmith 0x0c80C080, // paprd_rate_mask_ht20 // 4 9667754Smsmith 0x0080C080, // paprd_rate_mask_ht40 9767754Smsmith 0, // switchcomspdt; // 2 9867754Smsmith 0, // bit: 0,1:chain0, 2,3:chain1, 4,5:chain2 9967754Smsmith 0, // rf_gain_cap 10067754Smsmith 0, // tx_gain_cap 10167754Smsmith {0,0,0,0,0} //futureModal[5]; 10267754Smsmith }, 10367754Smsmith 10467754Smsmith { 10567754Smsmith 0, // ant_div_control 10667754Smsmith {0,0}, // base_ext1 10767754Smsmith 0, // misc_enable 10867754Smsmith {0,0,0,0,0,0,0,0}, // temp slop extension 10967754Smsmith 0, // quick drop low 11067754Smsmith 0, // quick drop high 11167754Smsmith }, 11267754Smsmith 11367754Smsmith //static A_UINT8 cal_freq_pier_2g[OSPREY_NUM_2G_CAL_PIERS]= 11467754Smsmith { 11567754Smsmith FREQ2FBIN(2412, 1), 11667754Smsmith FREQ2FBIN(2437, 1), 11767754Smsmith FREQ2FBIN(2462, 1) 11867754Smsmith }, 11967754Smsmith 120193341Sjkim //static OSP_CAL_DATA_PER_FREQ_OP_LOOP cal_pier_data_2g[OSPREY_MAX_CHAINS][OSPREY_NUM_2G_CAL_PIERS]= 121193341Sjkim 122193341Sjkim { {{0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}}, 12367754Smsmith {{0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}}, 12467754Smsmith {{0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}}, 12577424Smsmith }, 12691116Smsmith 12767754Smsmith //A_UINT8 cal_target_freqbin_cck[OSPREY_NUM_2G_CCK_TARGET_POWERS]; 12867754Smsmith 12967754Smsmith { 13067754Smsmith FREQ2FBIN(2412, 1), 13167754Smsmith FREQ2FBIN(2472, 1) 13267754Smsmith }, 133151937Sjkim 13467754Smsmith //static CAL_TARGET_POWER_LEG cal_target_freqbin_2g[OSPREY_NUM_2G_20_TARGET_POWERS] 13567754Smsmith { 13667754Smsmith FREQ2FBIN(2412, 1), 13767754Smsmith FREQ2FBIN(2437, 1), 13867754Smsmith FREQ2FBIN(2472, 1) 13967754Smsmith }, 14067754Smsmith 14167754Smsmith //static OSP_CAL_TARGET_POWER_HT cal_target_freqbin_2g_ht20[OSPREY_NUM_2G_20_TARGET_POWERS] 14267754Smsmith { 14367754Smsmith FREQ2FBIN(2412, 1), 14467754Smsmith FREQ2FBIN(2437, 1), 14567754Smsmith FREQ2FBIN(2472, 1) 14667754Smsmith }, 14791116Smsmith 14867754Smsmith //static OSP_CAL_TARGET_POWER_HT cal_target_freqbin_2g_ht40[OSPREY_NUM_2G_40_TARGET_POWERS] 14967754Smsmith { 15067754Smsmith FREQ2FBIN(2412, 1), 15167754Smsmith FREQ2FBIN(2437, 1), 15267754Smsmith FREQ2FBIN(2472, 1) 15367754Smsmith }, 15467754Smsmith 15567754Smsmith //static CAL_TARGET_POWER_LEG cal_target_power_cck[OSPREY_NUM_2G_CCK_TARGET_POWERS]= 15667754Smsmith { 15767754Smsmith //1L-5L,5S,11L,11S 15867754Smsmith {{38,38,38,38}}, 15967754Smsmith {{38,38,38,38}} 16067754Smsmith }, 16167754Smsmith 16267754Smsmith //static CAL_TARGET_POWER_LEG cal_target_power_2g[OSPREY_NUM_2G_20_TARGET_POWERS]= 16367754Smsmith { 16467754Smsmith //6-24,36,48,54 16567754Smsmith {{38,38,36,34}}, 16667754Smsmith {{38,38,36,34}}, 16791116Smsmith {{38,38,34,32}}, 16891116Smsmith }, 16991116Smsmith 17091116Smsmith //static OSP_CAL_TARGET_POWER_HT cal_target_power_2g_ht20[OSPREY_NUM_2G_20_TARGET_POWERS]= 17191116Smsmith { 17267754Smsmith //0_8_16,1-3_9-11_17-19, 17367754Smsmith // 4,5,6,7,12,13,14,15,20,21,22,23 17467754Smsmith {{36,36,36,36,36,34,34,32,30,28,28,28,28,26}}, 175200553Sjkim {{36,36,36,36,36,34,36,34,32,30,30,30,28,26}}, 17667754Smsmith {{36,36,36,36,36,34,34,32,30,28,28,28,28,26}}, 17767754Smsmith }, 17891116Smsmith 17967754Smsmith //static OSP_CAL_TARGET_POWER_HT cal_target_power_2g_ht40[OSPREY_NUM_2G_40_TARGET_POWERS]= 18067754Smsmith { 18167754Smsmith //0_8_16,1-3_9-11_17-19, 18267754Smsmith // 4,5,6,7,12,13,14,15,20,21,22,23 18367754Smsmith {{36,36,36,36,34,32,32,30,28,26,26,26,26,24}}, 18467754Smsmith {{36,36,36,36,34,32,34,32,30,28,28,28,28,24}}, 18591116Smsmith {{36,36,36,36,34,32,32,30,28,26,26,26,26,24}}, 18691116Smsmith }, 18767754Smsmith 18867754Smsmith//static A_UINT8 ctl_index_2g[OSPREY_NUM_CTLS_2G]= 189167802Sjkim 19067754Smsmith { 191167802Sjkim 19267754Smsmith 0x11, 19367754Smsmith 0x12, 19467754Smsmith 0x15, 19567754Smsmith 0x17, 19667754Smsmith 0x41, 19767754Smsmith 0x42, 19867754Smsmith 0x45, 19967754Smsmith 0x47, 20067754Smsmith 0x31, 20167754Smsmith 0x32, 20267754Smsmith 0x35, 20367754Smsmith 0x37 20467754Smsmith 20567754Smsmith }, 20667754Smsmith 20767754Smsmith//A_UINT8 ctl_freqbin_2G[OSPREY_NUM_CTLS_2G][OSPREY_NUM_BAND_EDGES_2G]; 20867754Smsmith 20967754Smsmith { 21067754Smsmith {FREQ2FBIN(2412, 1), 21167754Smsmith FREQ2FBIN(2417, 1), 212193267Sjkim FREQ2FBIN(2457, 1), 21391116Smsmith FREQ2FBIN(2462, 1)}, 21467754Smsmith 21567754Smsmith {FREQ2FBIN(2412, 1), 21667754Smsmith FREQ2FBIN(2417, 1), 21767754Smsmith FREQ2FBIN(2462, 1), 21867754Smsmith 0xFF}, 21967754Smsmith 22067754Smsmith {FREQ2FBIN(2412, 1), 22167754Smsmith FREQ2FBIN(2417, 1), 22267754Smsmith FREQ2FBIN(2462, 1), 22367754Smsmith 0xFF}, 22467754Smsmith 22567754Smsmith {FREQ2FBIN(2422, 1), 22667754Smsmith FREQ2FBIN(2427, 1), 22767754Smsmith FREQ2FBIN(2447, 1), 22891116Smsmith FREQ2FBIN(2452, 1)}, 22991116Smsmith 23091116Smsmith {/*Data[4].ctl_edges[0].bChannel*/FREQ2FBIN(2412, 1), 23191116Smsmith /*Data[4].ctl_edges[1].bChannel*/FREQ2FBIN(2417, 1), 23291116Smsmith /*Data[4].ctl_edges[2].bChannel*/FREQ2FBIN(2472, 1), 23367754Smsmith /*Data[4].ctl_edges[3].bChannel*/FREQ2FBIN(2484, 1)}, 23467754Smsmith 23567754Smsmith {/*Data[5].ctl_edges[0].bChannel*/FREQ2FBIN(2412, 1), 236200553Sjkim /*Data[5].ctl_edges[1].bChannel*/FREQ2FBIN(2417, 1), 23767754Smsmith /*Data[5].ctl_edges[2].bChannel*/FREQ2FBIN(2472, 1), 23867754Smsmith 0}, 23967754Smsmith 24067754Smsmith {/*Data[6].ctl_edges[0].bChannel*/FREQ2FBIN(2412, 1), 24167754Smsmith /*Data[6].ctl_edges[1].bChannel*/FREQ2FBIN(2417, 1), 24267754Smsmith FREQ2FBIN(2472, 1), 24367754Smsmith 0}, 24467754Smsmith 245193267Sjkim {/*Data[7].ctl_edges[0].bChannel*/FREQ2FBIN(2422, 1), 246200553Sjkim /*Data[7].ctl_edges[1].bChannel*/FREQ2FBIN(2427, 1), 24767754Smsmith /*Data[7].ctl_edges[2].bChannel*/FREQ2FBIN(2447, 1), 248114237Snjl /*Data[7].ctl_edges[3].bChannel*/FREQ2FBIN(2462, 1)}, 24967754Smsmith 250193267Sjkim {/*Data[8].ctl_edges[0].bChannel*/FREQ2FBIN(2412, 1), 25167754Smsmith /*Data[8].ctl_edges[1].bChannel*/FREQ2FBIN(2417, 1), 25267754Smsmith /*Data[8].ctl_edges[2].bChannel*/FREQ2FBIN(2472, 1), 25367754Smsmith 0}, 25467754Smsmith 25567754Smsmith {/*Data[9].ctl_edges[0].bChannel*/FREQ2FBIN(2412, 1), 25667754Smsmith /*Data[9].ctl_edges[1].bChannel*/FREQ2FBIN(2417, 1), 25767754Smsmith /*Data[9].ctl_edges[2].bChannel*/FREQ2FBIN(2472, 1), 25891116Smsmith 0}, 25967754Smsmith 26067754Smsmith {/*Data[10].ctl_edges[0].bChannel*/FREQ2FBIN(2412, 1), 26167754Smsmith /*Data[10].ctl_edges[1].bChannel*/FREQ2FBIN(2417, 1), 262167802Sjkim /*Data[10].ctl_edges[2].bChannel*/FREQ2FBIN(2472, 1), 26367754Smsmith 0}, 264167802Sjkim 26567754Smsmith {/*Data[11].ctl_edges[0].bChannel*/FREQ2FBIN(2422, 1), 26667754Smsmith /*Data[11].ctl_edges[1].bChannel*/FREQ2FBIN(2427, 1), 267100966Siwasaki /*Data[11].ctl_edges[2].bChannel*/FREQ2FBIN(2447, 1), 26867754Smsmith /*Data[11].ctl_edges[3].bChannel*/FREQ2FBIN(2462, 1)} 269100966Siwasaki }, 270100966Siwasaki 271100966Siwasaki 272100966Siwasaki//OSP_CAL_CTL_DATA_2G ctl_power_data_2g[OSPREY_NUM_CTLS_2G]; 273100966Siwasaki 27467754Smsmith#if AH_BYTE_ORDER == AH_BIG_ENDIAN 275100966Siwasaki { 27667754Smsmith 277100966Siwasaki {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, 278100966Siwasaki {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, 279100966Siwasaki {{{1, 60}, {0, 60}, {0, 60}, {1, 60}}}, 28067754Smsmith 28167754Smsmith {{{1, 60}, {0, 60}, {0, 60}, {0, 60}}}, 28267754Smsmith {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, 28367754Smsmith {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, 284100966Siwasaki 28567754Smsmith {{{0, 60}, {1, 60}, {1, 60}, {0, 60}}}, 286100966Siwasaki {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, 287100966Siwasaki {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, 288100966Siwasaki 28967754Smsmith {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, 29067754Smsmith {{{0, 60}, {1, 60}, {1, 60}, {1, 60}}}, 291100966Siwasaki {{{0, 60}, {1, 60}, {1, 60}, {1, 60}}}, 292100966Siwasaki 293100966Siwasaki }, 29467754Smsmith#else 29567754Smsmith { 29667754Smsmith {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, 29767754Smsmith {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, 298107325Siwasaki {{{60, 1}, {60, 0}, {60, 0}, {60, 1}}}, 29967754Smsmith 300100966Siwasaki {{{60, 1}, {60, 0}, {60, 0}, {60, 0}}}, 30167754Smsmith {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, 30267754Smsmith {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, 30391116Smsmith 30491116Smsmith {{{60, 0}, {60, 1}, {60, 1}, {60, 0}}}, 30591116Smsmith {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, 30691116Smsmith {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, 30791116Smsmith 30891116Smsmith {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, 309100966Siwasaki {{{60, 0}, {60, 1}, {60, 1}, {60, 1}}}, 31073561Smsmith {{{60, 0}, {60, 1}, {60, 1}, {60, 1}}}, 311100966Siwasaki }, 31267754Smsmith#endif 313100966Siwasaki 31467754Smsmith//static OSPREY_MODAL_EEP_HEADER modal_header_5g= 315200553Sjkim 316100966Siwasaki { 317100966Siwasaki 318100966Siwasaki 0x110, // ant_ctrl_common; // 4 idle, t1, t2, b (4 bits per setting) 319100966Siwasaki 0x22222, // ant_ctrl_common2; // 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 320100966Siwasaki {0x000,0x000,0x000}, // ant_ctrl_chain[OSPREY_MAX_CHAINS]; // 6 idle, t, r, rx1, rx12, b (2 bits each) 32167754Smsmith {0x13,0x19,0x17}, // xatten1_db[OSPREY_MAX_CHAINS]; // 3 //xatten1_db for merlin (0xa20c/b20c 5:0) 322100966Siwasaki {0x19,0x19,0x19}, // xatten1_margin[OSPREY_MAX_CHAINS]; // 3 //xatten1_margin for merlin (0xa20c/b20c 16:12 32367754Smsmith 70, // temp_slope; 324100966Siwasaki 15, // voltSlope; 325100966Siwasaki {0,0,0,0,0}, // spur_chans[OSPREY_EEPROM_MODAL_SPURS]; // spur channels in usual fbin coding format 32667754Smsmith {-1,0,0}, // noise_floor_thresh_ch[OSPREY_MAX_CHAINS]; // 3 //Check if the register is per chain 327200553Sjkim {0, 0, 0, 0, 0, 0,0,0,0,0,0}, // reserved 328100966Siwasaki 0, // quick drop 32967754Smsmith 0, // xpa_bias_lvl; // 1 330100966Siwasaki 0x0e, // tx_frame_to_data_start; // 1 331100966Siwasaki 0x0e, // tx_frame_to_pa_on; // 1 33267754Smsmith 3, // txClip; // 4 bits tx_clip, 4 bits dac_scale_cck 33367754Smsmith 0, // antenna_gain; // 1 33467754Smsmith 0x2d, // switchSettling; // 1 335100966Siwasaki -30, // adcDesiredSize; // 1 33667754Smsmith 0, // txEndToXpaOff; // 1 337193267Sjkim 0x2, // txEndToRxOn; // 1 33887031Smsmith 0xe, // tx_frame_to_xpa_on; // 1 33987031Smsmith 28, // thresh62; // 1 340100966Siwasaki 0x0cf0e0e0, // paprd_rate_mask_ht20 // 4 34187031Smsmith 0x6cf0e0e0, // paprd_rate_mask_ht40 // 4 34287031Smsmith 0, // switchcomspdt; // 2 34387031Smsmith 0, // bit: 0,1:chain0, 2,3:chain1, 4,5:chain2 344100966Siwasaki 0, // rf_gain_cap 34587031Smsmith 0, // tx_gain_cap 346200553Sjkim {0,0,0,0,0} //futureModal[5]; 34787031Smsmith }, 34887031Smsmith 34987031Smsmith { // base_ext2 35087031Smsmith 72, // tempSlopeL; 35187031Smsmith 105, // tempSlopeH; 35291116Smsmith {0x10,0x14,0x10}, // xatten1_db_low 35387031Smsmith {0x19,0x19,0x19}, // xatten1_margin_low 35487031Smsmith {0x1d,0x20,0x24}, // xatten1_db_high 35587031Smsmith {0x10,0x10,0x10} // xatten1_margin_high 356167802Sjkim }, 35787031Smsmith 358//static A_UINT8 cal_freq_pier_5g[OSPREY_NUM_5G_CAL_PIERS]= 359 { 360 //pPiers[0] = 361 FREQ2FBIN(5180, 0), 362 //pPiers[1] = 363 FREQ2FBIN(5220, 0), 364 //pPiers[2] = 365 FREQ2FBIN(5320, 0), 366 //pPiers[3] = 367 FREQ2FBIN(5400, 0), 368 //pPiers[4] = 369 FREQ2FBIN(5500, 0), 370 //pPiers[5] = 371 FREQ2FBIN(5600, 0), 372 //pPiers[6] = 373 FREQ2FBIN(5700, 0), 374 //pPiers[7] = 375 FREQ2FBIN(5785, 0) 376 }, 377 378//static OSP_CAL_DATA_PER_FREQ_OP_LOOP cal_pier_data_5g[OSPREY_MAX_CHAINS][OSPREY_NUM_5G_CAL_PIERS]= 379 380 { 381 {{0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}}, 382 {{0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}}, 383 {{0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}}, 384 385 }, 386 387//static CAL_TARGET_POWER_LEG cal_target_freqbin_5g[OSPREY_NUM_5G_20_TARGET_POWERS]= 388 389 { 390 FREQ2FBIN(5180, 0), 391 FREQ2FBIN(5220, 0), 392 FREQ2FBIN(5320, 0), 393 FREQ2FBIN(5400, 0), 394 FREQ2FBIN(5500, 0), 395 FREQ2FBIN(5600, 0), 396 FREQ2FBIN(5725, 0), 397 FREQ2FBIN(5825, 0) 398 }, 399 400//static OSP_CAL_TARGET_POWER_HT cal_target_power_5g_ht20[OSPREY_NUM_5G_20_TARGET_POWERS]= 401 402 { 403 FREQ2FBIN(5180, 0), 404 FREQ2FBIN(5220, 0), 405 FREQ2FBIN(5320, 0), 406 FREQ2FBIN(5400, 0), 407 FREQ2FBIN(5500, 0), 408 FREQ2FBIN(5600, 0), 409 FREQ2FBIN(5725, 0), 410 FREQ2FBIN(5825, 0) 411 }, 412 413//static OSP_CAL_TARGET_POWER_HT cal_target_power_5g_ht40[OSPREY_NUM_5G_40_TARGET_POWERS]= 414 415 { 416 FREQ2FBIN(5180, 0), 417 FREQ2FBIN(5220, 0), 418 FREQ2FBIN(5320, 0), 419 FREQ2FBIN(5400, 0), 420 FREQ2FBIN(5500, 0), 421 FREQ2FBIN(5600, 0), 422 FREQ2FBIN(5725, 0), 423 FREQ2FBIN(5825, 0) 424 }, 425 426 427//static CAL_TARGET_POWER_LEG cal_target_power_5g[OSPREY_NUM_5G_20_TARGET_POWERS]= 428 429 430 { 431 //6-24,36,48,54 432 {{32,32,28,26}}, 433 {{32,32,28,26}}, 434 {{32,32,28,26}}, 435 {{32,32,26,24}}, 436 {{32,32,26,24}}, 437 {{32,32,24,22}}, 438 {{30,30,24,22}}, 439 {{30,30,24,22}}, 440 }, 441 442//static OSP_CAL_TARGET_POWER_HT cal_target_power_5g_ht20[OSPREY_NUM_5G_20_TARGET_POWERS]= 443 444 { 445 //0_8_16,1-3_9-11_17-19, 446 // 4,5,6,7,12,13,14,15,20,21,22,23 447 {{32,32,32,32,28,26,32,28,26,24,24,24,22,22}}, 448 {{32,32,32,32,28,26,32,28,26,24,24,24,22,22}}, 449 {{32,32,32,32,28,26,32,28,26,24,24,24,22,22}}, 450 {{32,32,32,32,28,26,32,26,24,22,22,22,20,20}}, 451 {{32,32,32,32,28,26,32,26,24,22,20,18,16,16}}, 452 {{32,32,32,32,28,26,32,24,20,16,18,16,14,14}}, 453 {{30,30,30,30,28,26,30,24,20,16,18,16,14,14}}, 454 {{30,30,30,30,28,26,30,24,20,16,18,16,14,14}}, 455 }, 456 457//static OSP_CAL_TARGET_POWER_HT cal_target_power_5g_ht40[OSPREY_NUM_5G_40_TARGET_POWERS]= 458 { 459 //0_8_16,1-3_9-11_17-19, 460 // 4,5,6,7,12,13,14,15,20,21,22,23 461 {{32,32,32,30,28,26,30,28,26,24,24,24,22,22}}, 462 {{32,32,32,30,28,26,30,28,26,24,24,24,22,22}}, 463 {{32,32,32,30,28,26,30,28,26,24,24,24,22,22}}, 464 {{32,32,32,30,28,26,30,26,24,22,22,22,20,20}}, 465 {{32,32,32,30,28,26,30,26,24,22,20,18,16,16}}, 466 {{32,32,32,30,28,26,30,22,20,16,18,16,14,14}}, 467 {{30,30,30,30,28,26,30,22,20,16,18,16,14,14}}, 468 {{30,30,30,30,28,26,30,22,20,16,18,16,14,14}}, 469 }, 470 471//static A_UINT8 ctl_index_5g[OSPREY_NUM_CTLS_5G]= 472 473 { 474 //pCtlIndex[0] = 475 0x10, 476 //pCtlIndex[1] = 477 0x16, 478 //pCtlIndex[2] = 479 0x18, 480 //pCtlIndex[3] = 481 0x40, 482 //pCtlIndex[4] = 483 0x46, 484 //pCtlIndex[5] = 485 0x48, 486 //pCtlIndex[6] = 487 0x30, 488 //pCtlIndex[7] = 489 0x36, 490 //pCtlIndex[8] = 491 0x38 492 }, 493 494// A_UINT8 ctl_freqbin_5G[OSPREY_NUM_CTLS_5G][OSPREY_NUM_BAND_EDGES_5G]; 495 496 { 497 {/* Data[0].ctl_edges[0].bChannel*/FREQ2FBIN(5180, 0), 498 /* Data[0].ctl_edges[1].bChannel*/FREQ2FBIN(5260, 0), 499 /* Data[0].ctl_edges[2].bChannel*/FREQ2FBIN(5280, 0), 500 /* Data[0].ctl_edges[3].bChannel*/FREQ2FBIN(5500, 0), 501 /* Data[0].ctl_edges[4].bChannel*/FREQ2FBIN(5600, 0), 502 /* Data[0].ctl_edges[5].bChannel*/FREQ2FBIN(5700, 0), 503 /* Data[0].ctl_edges[6].bChannel*/FREQ2FBIN(5745, 0), 504 /* Data[0].ctl_edges[7].bChannel*/FREQ2FBIN(5825, 0)}, 505 506 {/* Data[1].ctl_edges[0].bChannel*/FREQ2FBIN(5180, 0), 507 /* Data[1].ctl_edges[1].bChannel*/FREQ2FBIN(5260, 0), 508 /* Data[1].ctl_edges[2].bChannel*/FREQ2FBIN(5280, 0), 509 /* Data[1].ctl_edges[3].bChannel*/FREQ2FBIN(5500, 0), 510 /* Data[1].ctl_edges[4].bChannel*/FREQ2FBIN(5520, 0), 511 /* Data[1].ctl_edges[5].bChannel*/FREQ2FBIN(5700, 0), 512 /* Data[1].ctl_edges[6].bChannel*/FREQ2FBIN(5745, 0), 513 /* Data[1].ctl_edges[7].bChannel*/FREQ2FBIN(5825, 0)}, 514 515 {/* Data[2].ctl_edges[0].bChannel*/FREQ2FBIN(5190, 0), 516 /* Data[2].ctl_edges[1].bChannel*/FREQ2FBIN(5230, 0), 517 /* Data[2].ctl_edges[2].bChannel*/FREQ2FBIN(5270, 0), 518 /* Data[2].ctl_edges[3].bChannel*/FREQ2FBIN(5310, 0), 519 /* Data[2].ctl_edges[4].bChannel*/FREQ2FBIN(5510, 0), 520 /* Data[2].ctl_edges[5].bChannel*/FREQ2FBIN(5550, 0), 521 /* Data[2].ctl_edges[6].bChannel*/FREQ2FBIN(5670, 0), 522 /* Data[2].ctl_edges[7].bChannel*/FREQ2FBIN(5755, 0)}, 523 524 {/* Data[3].ctl_edges[0].bChannel*/FREQ2FBIN(5180, 0), 525 /* Data[3].ctl_edges[1].bChannel*/FREQ2FBIN(5200, 0), 526 /* Data[3].ctl_edges[2].bChannel*/FREQ2FBIN(5260, 0), 527 /* Data[3].ctl_edges[3].bChannel*/FREQ2FBIN(5320, 0), 528 /* Data[3].ctl_edges[4].bChannel*/FREQ2FBIN(5500, 0), 529 /* Data[3].ctl_edges[5].bChannel*/FREQ2FBIN(5700, 0), 530 /* Data[3].ctl_edges[6].bChannel*/0xFF, 531 /* Data[3].ctl_edges[7].bChannel*/0xFF}, 532 533 {/* Data[4].ctl_edges[0].bChannel*/FREQ2FBIN(5180, 0), 534 /* Data[4].ctl_edges[1].bChannel*/FREQ2FBIN(5260, 0), 535 /* Data[4].ctl_edges[2].bChannel*/FREQ2FBIN(5500, 0), 536 /* Data[4].ctl_edges[3].bChannel*/FREQ2FBIN(5700, 0), 537 /* Data[4].ctl_edges[4].bChannel*/0xFF, 538 /* Data[4].ctl_edges[5].bChannel*/0xFF, 539 /* Data[4].ctl_edges[6].bChannel*/0xFF, 540 /* Data[4].ctl_edges[7].bChannel*/0xFF}, 541 542 {/* Data[5].ctl_edges[0].bChannel*/FREQ2FBIN(5190, 0), 543 /* Data[5].ctl_edges[1].bChannel*/FREQ2FBIN(5270, 0), 544 /* Data[5].ctl_edges[2].bChannel*/FREQ2FBIN(5310, 0), 545 /* Data[5].ctl_edges[3].bChannel*/FREQ2FBIN(5510, 0), 546 /* Data[5].ctl_edges[4].bChannel*/FREQ2FBIN(5590, 0), 547 /* Data[5].ctl_edges[5].bChannel*/FREQ2FBIN(5670, 0), 548 /* Data[5].ctl_edges[6].bChannel*/0xFF, 549 /* Data[5].ctl_edges[7].bChannel*/0xFF}, 550 551 {/* Data[6].ctl_edges[0].bChannel*/FREQ2FBIN(5180, 0), 552 /* Data[6].ctl_edges[1].bChannel*/FREQ2FBIN(5200, 0), 553 /* Data[6].ctl_edges[2].bChannel*/FREQ2FBIN(5220, 0), 554 /* Data[6].ctl_edges[3].bChannel*/FREQ2FBIN(5260, 0), 555 /* Data[6].ctl_edges[4].bChannel*/FREQ2FBIN(5500, 0), 556 /* Data[6].ctl_edges[5].bChannel*/FREQ2FBIN(5600, 0), 557 /* Data[6].ctl_edges[6].bChannel*/FREQ2FBIN(5700, 0), 558 /* Data[6].ctl_edges[7].bChannel*/FREQ2FBIN(5745, 0)}, 559 560 {/* Data[7].ctl_edges[0].bChannel*/FREQ2FBIN(5180, 0), 561 /* Data[7].ctl_edges[1].bChannel*/FREQ2FBIN(5260, 0), 562 /* Data[7].ctl_edges[2].bChannel*/FREQ2FBIN(5320, 0), 563 /* Data[7].ctl_edges[3].bChannel*/FREQ2FBIN(5500, 0), 564 /* Data[7].ctl_edges[4].bChannel*/FREQ2FBIN(5560, 0), 565 /* Data[7].ctl_edges[5].bChannel*/FREQ2FBIN(5700, 0), 566 /* Data[7].ctl_edges[6].bChannel*/FREQ2FBIN(5745, 0), 567 /* Data[7].ctl_edges[7].bChannel*/FREQ2FBIN(5825, 0)}, 568 569 {/* Data[8].ctl_edges[0].bChannel*/FREQ2FBIN(5190, 0), 570 /* Data[8].ctl_edges[1].bChannel*/FREQ2FBIN(5230, 0), 571 /* Data[8].ctl_edges[2].bChannel*/FREQ2FBIN(5270, 0), 572 /* Data[8].ctl_edges[3].bChannel*/FREQ2FBIN(5510, 0), 573 /* Data[8].ctl_edges[4].bChannel*/FREQ2FBIN(5550, 0), 574 /* Data[8].ctl_edges[5].bChannel*/FREQ2FBIN(5670, 0), 575 /* Data[8].ctl_edges[6].bChannel*/FREQ2FBIN(5755, 0), 576 /* Data[8].ctl_edges[7].bChannel*/FREQ2FBIN(5795, 0)} 577 }, 578 579//static OSP_CAL_CTL_DATA_5G ctlData_5G[OSPREY_NUM_CTLS_5G]= 580 581#if AH_BYTE_ORDER == AH_BIG_ENDIAN 582 { 583 {{{1, 60}, 584 {1, 60}, 585 {1, 60}, 586 {1, 60}, 587 {1, 60}, 588 {1, 60}, 589 {1, 60}, 590 {0, 60}}}, 591 592 {{{1, 60}, 593 {1, 60}, 594 {1, 60}, 595 {1, 60}, 596 {1, 60}, 597 {1, 60}, 598 {1, 60}, 599 {0, 60}}}, 600 601 {{{0, 60}, 602 {1, 60}, 603 {0, 60}, 604 {1, 60}, 605 {1, 60}, 606 {1, 60}, 607 {1, 60}, 608 {1, 60}}}, 609 610 {{{0, 60}, 611 {1, 60}, 612 {1, 60}, 613 {0, 60}, 614 {1, 60}, 615 {0, 60}, 616 {0, 60}, 617 {0, 60}}}, 618 619 {{{1, 60}, 620 {1, 60}, 621 {1, 60}, 622 {0, 60}, 623 {0, 60}, 624 {0, 60}, 625 {0, 60}, 626 {0, 60}}}, 627 628 {{{1, 60}, 629 {1, 60}, 630 {1, 60}, 631 {1, 60}, 632 {1, 60}, 633 {0, 60}, 634 {0, 60}, 635 {0, 60}}}, 636 637 {{{1, 60}, 638 {1, 60}, 639 {1, 60}, 640 {1, 60}, 641 {1, 60}, 642 {1, 60}, 643 {1, 60}, 644 {1, 60}}}, 645 646 {{{1, 60}, 647 {1, 60}, 648 {0, 60}, 649 {1, 60}, 650 {1, 60}, 651 {1, 60}, 652 {1, 60}, 653 {0, 60}}}, 654 655 {{{1, 60}, 656 {0, 60}, 657 {1, 60}, 658 {1, 60}, 659 {1, 60}, 660 {1, 60}, 661 {0, 60}, 662 {1, 60}}}, 663 } 664#else 665 { 666 {{{60, 1}, 667 {60, 1}, 668 {60, 1}, 669 {60, 1}, 670 {60, 1}, 671 {60, 1}, 672 {60, 1}, 673 {60, 0}}}, 674 675 {{{60, 1}, 676 {60, 1}, 677 {60, 1}, 678 {60, 1}, 679 {60, 1}, 680 {60, 1}, 681 {60, 1}, 682 {60, 0}}}, 683 684 {{{60, 0}, 685 {60, 1}, 686 {60, 0}, 687 {60, 1}, 688 {60, 1}, 689 {60, 1}, 690 {60, 1}, 691 {60, 1}}}, 692 693 {{{60, 0}, 694 {60, 1}, 695 {60, 1}, 696 {60, 0}, 697 {60, 1}, 698 {60, 0}, 699 {60, 0}, 700 {60, 0}}}, 701 702 {{{60, 1}, 703 {60, 1}, 704 {60, 1}, 705 {60, 0}, 706 {60, 0}, 707 {60, 0}, 708 {60, 0}, 709 {60, 0}}}, 710 711 {{{60, 1}, 712 {60, 1}, 713 {60, 1}, 714 {60, 1}, 715 {60, 1}, 716 {60, 0}, 717 {60, 0}, 718 {60, 0}}}, 719 720 {{{60, 1}, 721 {60, 1}, 722 {60, 1}, 723 {60, 1}, 724 {60, 1}, 725 {60, 1}, 726 {60, 1}, 727 {60, 1}}}, 728 729 {{{60, 1}, 730 {60, 1}, 731 {60, 0}, 732 {60, 1}, 733 {60, 1}, 734 {60, 1}, 735 {60, 1}, 736 {60, 0}}}, 737 738 {{{60, 1}, 739 {60, 0}, 740 {60, 1}, 741 {60, 1}, 742 {60, 1}, 743 {60, 1}, 744 {60, 0}, 745 {60, 1}}}, 746 } 747#endif 748}; 749 750#endif 751