ar9300desc.h revision 250007 
1/*
2 * Copyright (c) 2013 Qualcomm Atheros, Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH
9 * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
10 * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT,
11 * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM
12 * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
13 * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
14 * PERFORMANCE OF THIS SOFTWARE.
15 */
16
17
18 /* Contains descriptor definitions for Osprey */
19
20
21#ifndef _ATH_AR9300_DESC_H_
22#define _ATH_AR9300_DESC_H_
23
24
25/* Osprey Status Descriptor. */
26struct ar9300_txs {
27    u_int32_t   ds_info;
28    u_int32_t   status1;
29    u_int32_t   status2;
30    u_int32_t   status3;
31    u_int32_t   status4;
32    u_int32_t   status5;
33    u_int32_t   status6;
34    u_int32_t   status7;
35    u_int32_t   status8;
36};
37
38struct ar9300_rxs {
39    u_int32_t   ds_info;
40    u_int32_t   status1;
41    u_int32_t   status2;
42    u_int32_t   status3;
43    u_int32_t   status4;
44    u_int32_t   status5;
45    u_int32_t   status6;
46    u_int32_t   status7;
47    u_int32_t   status8;
48    u_int32_t   status9;
49    u_int32_t   status10;
50    u_int32_t   status11;
51};
52
53/* Transmit Control Descriptor */
54struct ar9300_txc {
55    u_int32_t   ds_info;   /* descriptor information */
56    u_int32_t   ds_link;   /* link pointer */
57    u_int32_t   ds_data0;  /* data pointer to 1st buffer */
58    u_int32_t   ds_ctl3;   /* DMA control 3  */
59    u_int32_t   ds_data1;  /* data pointer to 2nd buffer */
60    u_int32_t   ds_ctl5;   /* DMA control 5  */
61    u_int32_t   ds_data2;  /* data pointer to 3rd buffer */
62    u_int32_t   ds_ctl7;   /* DMA control 7  */
63    u_int32_t   ds_data3;  /* data pointer to 4th buffer */
64    u_int32_t   ds_ctl9;   /* DMA control 9  */
65    u_int32_t   ds_ctl10;  /* DMA control 10 */
66    u_int32_t   ds_ctl11;  /* DMA control 11 */
67    u_int32_t   ds_ctl12;  /* DMA control 12 */
68    u_int32_t   ds_ctl13;  /* DMA control 13 */
69    u_int32_t   ds_ctl14;  /* DMA control 14 */
70    u_int32_t   ds_ctl15;  /* DMA control 15 */
71    u_int32_t   ds_ctl16;  /* DMA control 16 */
72    u_int32_t   ds_ctl17;  /* DMA control 17 */
73    u_int32_t   ds_ctl18;  /* DMA control 18 */
74    u_int32_t   ds_ctl19;  /* DMA control 19 */
75    u_int32_t   ds_ctl20;  /* DMA control 20 */
76    u_int32_t   ds_ctl21;  /* DMA control 21 */
77    u_int32_t   ds_ctl22;  /* DMA control 22 */
78    u_int32_t   ds_pad[9]; /* pad to cache line (128 bytes/32 dwords) */
79};
80
81
82#define AR9300RXS(_rxs)        ((struct ar9300_rxs *)(_rxs))
83#define AR9300TXS(_txs)        ((struct ar9300_txs *)(_txs))
84#define AR9300TXC(_ds)         ((struct ar9300_txc *)(_ds))
85
86#define AR9300TXC_CONST(_ds)   ((const struct ar9300_txc *)(_ds))
87
88
89/* ds_info */
90#define AR_desc_len          0x000000ff
91#define AR_rx_priority       0x00000100
92#define AR_tx_qcu_num         0x00000f00
93#define AR_tx_qcu_num_S       8
94#define AR_ctrl_stat         0x00004000
95#define AR_ctrl_stat_S       14
96#define AR_tx_rx_desc         0x00008000
97#define AR_tx_rx_desc_S       15
98#define AR_desc_id           0xffff0000
99#define AR_desc_id_S         16
100
101/***********
102 * TX Desc *
103 ***********/
104
105/* ds_ctl3 */
106/* ds_ctl5 */
107/* ds_ctl7 */
108/* ds_ctl9 */
109#define AR_buf_len           0x0fff0000
110#define AR_buf_len_S         16
111
112/* ds_ctl10 */
113#define AR_tx_desc_id         0xffff0000
114#define AR_tx_desc_id_S       16
115#define AR_tx_ptr_chk_sum      0x0000ffff
116
117/* ds_ctl11 */
118#define AR_frame_len         0x00000fff
119#define AR_virt_more_frag     0x00001000
120#define AR_tx_ctl_rsvd00      0x00002000
121#define AR_low_rx_chain       0x00004000
122#define AR_tx_clear_retry     0x00008000
123#define AR_xmit_power0       0x003f0000
124#define AR_xmit_power0_S     16
125#define AR_rts_enable        0x00400000
126#define AR_veol             0x00800000
127#define AR_clr_dest_mask      0x01000000
128#define AR_tx_bf0            0x02000000
129#define AR_tx_bf1            0x04000000
130#define AR_tx_bf2            0x08000000
131#define AR_tx_bf3            0x10000000
132#define	AR_TxBfSteered		0x1e000000			/* for tx_bf*/
133#define AR_tx_intr_req        0x20000000
134#define AR_dest_idx_valid     0x40000000
135#define AR_cts_enable        0x80000000
136
137/* ds_ctl12 */
138#define AR_tx_ctl_rsvd02      0x000001ff
139#define AR_paprd_chain_mask   0x00000e00
140#define AR_paprd_chain_mask_S 9
141#define AR_tx_more           0x00001000
142#define AR_dest_idx          0x000fe000
143#define AR_dest_idx_S        13
144#define AR_frame_type        0x00f00000
145#define AR_frame_type_S      20
146#define AR_no_ack            0x01000000
147#define AR_insert_ts         0x02000000
148#define AR_corrupt_fcs       0x04000000
149#define AR_ext_only          0x08000000
150#define AR_ext_and_ctl        0x10000000
151#define AR_more_aggr         0x20000000
152#define AR_is_aggr           0x40000000
153#define AR_more_rifs         0x80000000
154#define AR_loc_mode          0x00000100 /* Positioning bit in TX desc */
155
156/* ds_ctl13 */
157#define AR_burst_dur         0x00007fff
158#define AR_burst_dur_S       0
159#define AR_dur_update_ena     0x00008000
160#define AR_xmit_data_tries0   0x000f0000
161#define AR_xmit_data_tries0_S 16
162#define AR_xmit_data_tries1   0x00f00000
163#define AR_xmit_data_tries1_S 20
164#define AR_xmit_data_tries2   0x0f000000
165#define AR_xmit_data_tries2_S 24
166#define AR_xmit_data_tries3   0xf0000000
167#define AR_xmit_data_tries3_S 28
168
169/* ds_ctl14 */
170#define AR_xmit_rate0        0x000000ff
171#define AR_xmit_rate0_S      0
172#define AR_xmit_rate1        0x0000ff00
173#define AR_xmit_rate1_S      8
174#define AR_xmit_rate2        0x00ff0000
175#define AR_xmit_rate2_S      16
176#define AR_xmit_rate3        0xff000000
177#define AR_xmit_rate3_S      24
178
179/* ds_ctl15 */
180#define AR_packet_dur0       0x00007fff
181#define AR_packet_dur0_S     0
182#define AR_rts_cts_qual0      0x00008000
183#define AR_packet_dur1       0x7fff0000
184#define AR_packet_dur1_S     16
185#define AR_rts_cts_qual1      0x80000000
186
187/* ds_ctl16 */
188#define AR_packet_dur2       0x00007fff
189#define AR_packet_dur2_S     0
190#define AR_rts_cts_qual2      0x00008000
191#define AR_packet_dur3       0x7fff0000
192#define AR_packet_dur3_S     16
193#define AR_rts_cts_qual3      0x80000000
194
195/* ds_ctl17 */
196#define AR_aggr_len          0x0000ffff
197#define AR_aggr_len_S        0
198#define AR_tx_ctl_rsvd60      0x00030000
199#define AR_pad_delim         0x03fc0000
200#define AR_pad_delim_S       18
201#define AR_encr_type         0x1c000000
202#define AR_encr_type_S       26
203#define AR_tx_dc_ap_sta_sel     0x40000000
204#define AR_tx_ctl_rsvd61      0xc0000000
205#define AR_calibrating      0x40000000
206#define AR_ldpc             0x80000000
207
208/* ds_ctl18 */
209#define AR_2040_0           0x00000001
210#define AR_gi0              0x00000002
211#define AR_chain_sel0        0x0000001c
212#define AR_chain_sel0_S      2
213#define AR_2040_1           0x00000020
214#define AR_gi1              0x00000040
215#define AR_chain_sel1        0x00000380
216#define AR_chain_sel1_S      7
217#define AR_2040_2           0x00000400
218#define AR_gi2              0x00000800
219#define AR_chain_sel2        0x00007000
220#define AR_chain_sel2_S      12
221#define AR_2040_3           0x00008000
222#define AR_gi3              0x00010000
223#define AR_chain_sel3        0x000e0000
224#define AR_chain_sel3_S      17
225#define AR_rts_cts_rate       0x0ff00000
226#define AR_rts_cts_rate_S     20
227#define AR_stbc0            0x10000000
228#define AR_stbc1            0x20000000
229#define AR_stbc2            0x40000000
230#define AR_stbc3            0x80000000
231
232/* ds_ctl19 */
233#define AR_tx_ant0           0x00ffffff
234#define AR_tx_ant_sel0        0x80000000
235#define	AR_RTS_HTC_TRQ      0x10000000	/* bit 28 for rts_htc_TRQ*/ /*for tx_bf*/
236#define AR_not_sounding     0x20000000
237#define AR_ness				0xc0000000
238#define AR_ness_S			30
239
240/* ds_ctl20 */
241#define AR_tx_ant1           0x00ffffff
242#define AR_xmit_power1       0x3f000000
243#define AR_xmit_power1_S     24
244#define AR_tx_ant_sel1        0x80000000
245#define AR_ness1			0xc0000000
246#define AR_ness1_S			30
247
248/* ds_ctl21 */
249#define AR_tx_ant2           0x00ffffff
250#define AR_xmit_power2       0x3f000000
251#define AR_xmit_power2_S     24
252#define AR_tx_ant_sel2        0x80000000
253#define AR_ness2			0xc0000000
254#define AR_ness2_S			30
255
256/* ds_ctl22 */
257#define AR_tx_ant3           0x00ffffff
258#define AR_xmit_power3       0x3f000000
259#define AR_xmit_power3_S     24
260#define AR_tx_ant_sel3        0x80000000
261#define AR_ness3			0xc0000000
262#define AR_ness3_S			30
263
264/*************
265 * TX Status *
266 *************/
267
268/* ds_status1 */
269#define AR_tx_status_rsvd     0x0000ffff
270
271/* ds_status2 */
272#define AR_tx_rssi_ant00      0x000000ff
273#define AR_tx_rssi_ant00_S    0
274#define AR_tx_rssi_ant01      0x0000ff00
275#define AR_tx_rssi_ant01_S    8
276#define AR_tx_rssi_ant02      0x00ff0000
277#define AR_tx_rssi_ant02_S    16
278#define AR_tx_status_rsvd00   0x3f000000
279#define AR_tx_ba_status       0x40000000
280#define AR_tx_status_rsvd01   0x80000000
281
282/* ds_status3 */
283#define AR_frm_xmit_ok        0x00000001
284#define AR_excessive_retries 0x00000002
285#define AR_fifounderrun     0x00000004
286#define AR_filtered         0x00000008
287#define AR_rts_fail_cnt       0x000000f0
288#define AR_rts_fail_cnt_S     4
289#define AR_data_fail_cnt      0x00000f00
290#define AR_data_fail_cnt_S    8
291#define AR_virt_retry_cnt     0x0000f000
292#define AR_virt_retry_cnt_S   12
293#define AR_tx_delim_underrun  0x00010000
294#define AR_tx_data_underrun   0x00020000
295#define AR_desc_cfg_err       0x00040000
296#define AR_tx_timer_expired   0x00080000
297#define AR_tx_status_rsvd10   0xfff00000
298
299/* ds_status7 */
300#define AR_tx_rssi_ant10      0x000000ff
301#define AR_tx_rssi_ant10_S    0
302#define AR_tx_rssi_ant11      0x0000ff00
303#define AR_tx_rssi_ant11_S    8
304#define AR_tx_rssi_ant12      0x00ff0000
305#define AR_tx_rssi_ant12_S    16
306#define AR_tx_rssi_combined   0xff000000
307#define AR_tx_rssi_combined_S 24
308
309/* ds_status8 */
310#define AR_tx_done           0x00000001
311#define AR_seq_num           0x00001ffe
312#define AR_seq_num_S         1
313#define AR_tx_status_rsvd80   0x0001e000
314#define AR_tx_op_exceeded     0x00020000
315#define AR_tx_status_rsvd81   0x001c0000
316#define	AR_TXBFStatus		0x001c0000
317#define	AR_TXBFStatus_S		18
318#define AR_tx_bf_bw_mismatch 0x00040000
319#define AR_tx_bf_stream_miss 0x00080000
320#define AR_final_tx_idx       0x00600000
321#define AR_final_tx_idx_S     21
322#define AR_tx_bf_dest_miss   0x00800000
323#define AR_tx_bf_expired     0x01000000
324#define AR_power_mgmt        0x02000000
325#define AR_tx_status_rsvd83   0x0c000000
326#define AR_tx_tid            0xf0000000
327#define AR_tx_tid_S          28
328#define AR_tx_fast_ts        0x08000000 /* 27th bit for locationing */
329
330
331/*************
332 * Rx Status *
333 *************/
334
335/* ds_status1 */
336#define AR_rx_rssi_ant00      0x000000ff
337#define AR_rx_rssi_ant00_S    0
338#define AR_rx_rssi_ant01      0x0000ff00
339#define AR_rx_rssi_ant01_S    8
340#define AR_rx_rssi_ant02      0x00ff0000
341#define AR_rx_rssi_ant02_S    16
342#define AR_rx_rate           0xff000000
343#define AR_rx_rate_S         24
344
345/* ds_status2 */
346#define AR_data_len          0x00000fff
347#define AR_rx_more           0x00001000
348#define AR_num_delim         0x003fc000
349#define AR_num_delim_S       14
350#define AR_hw_upload_data     0x00400000
351#define AR_hw_upload_data_S   22
352#define AR_rx_status_rsvd10   0xff800000
353
354
355/* ds_status4 */
356#define AR_gi               0x00000001
357#define AR_2040             0x00000002
358#define AR_parallel40       0x00000004
359#define AR_parallel40_S     2
360#define AR_rx_stbc           0x00000008
361#define AR_rx_not_sounding    0x00000010
362#define AR_rx_ness           0x00000060
363#define AR_rx_ness_S         5
364#define AR_hw_upload_data_valid    0x00000080
365#define AR_hw_upload_data_valid_S  7
366#define AR_rx_antenna	    0xffffff00
367#define AR_rx_antenna_S	    8
368
369/* ds_status5 */
370#define AR_rx_rssi_ant10            0x000000ff
371#define AR_rx_rssi_ant10_S          0
372#define AR_rx_rssi_ant11            0x0000ff00
373#define AR_rx_rssi_ant11_S          8
374#define AR_rx_rssi_ant12            0x00ff0000
375#define AR_rx_rssi_ant12_S          16
376#define AR_rx_rssi_combined         0xff000000
377#define AR_rx_rssi_combined_S       24
378
379/* ds_status6 */
380#define AR_rx_evm0           status6
381
382/* ds_status7 */
383#define AR_rx_evm1           status7
384
385/* ds_status8 */
386#define AR_rx_evm2           status8
387
388/* ds_status9 */
389#define AR_rx_evm3           status9
390
391/* ds_status11 */
392#define AR_rx_done           0x00000001
393#define AR_rx_frame_ok        0x00000002
394#define AR_crc_err           0x00000004
395#define AR_decrypt_crc_err    0x00000008
396#define AR_phyerr           0x00000010
397#define AR_michael_err       0x00000020
398#define AR_pre_delim_crc_err   0x00000040
399#define AR_apsd_trig         0x00000080
400#define AR_rx_key_idx_valid    0x00000100
401#define AR_key_idx           0x0000fe00
402#define AR_key_idx_S         9
403#define AR_phy_err_code       0x0000ff00
404#define AR_phy_err_code_S     8
405#define AR_rx_more_aggr       0x00010000
406#define AR_rx_aggr           0x00020000
407#define AR_post_delim_crc_err  0x00040000
408#define AR_rx_status_rsvd71   0x01f80000
409#define AR_hw_upload_data_type 0x06000000
410#define AR_hw_upload_data_type_S   25
411#define AR_position_bit      0x08000000 /* positioning bit */
412#define AR_hi_rx_chain        0x10000000
413#define AR_rx_first_aggr      0x20000000
414#define AR_decrypt_busy_err   0x40000000
415#define AR_key_miss          0x80000000
416
417#define TXCTL_OFFSET(ah)      11
418#define TXCTL_NUMWORDS(ah)    12
419#define TXSTATUS_OFFSET(ah)   2
420#define TXSTATUS_NUMWORDS(ah) 7
421
422#define RXCTL_OFFSET(ah)      0
423#define RXCTL_NUMWORDS(ah)    0
424#define RXSTATUS_OFFSET(ah)   1
425#define RXSTATUS_NUMWORDS(ah) 11
426
427
428#define TXC_INFO(_qcu) (ATHEROS_VENDOR_ID << AR_desc_id_S) \
429                        | (1 << AR_tx_rx_desc_S) \
430                        | (1 << AR_ctrl_stat_S) \
431                        | (_qcu << AR_tx_qcu_num_S) \
432                        | (0x17)
433
434#define VALID_KEY_TYPES \
435        ((1 << HAL_KEY_TYPE_CLEAR) | (1 << HAL_KEY_TYPE_WEP)|\
436         (1 << HAL_KEY_TYPE_AES)   | (1 << HAL_KEY_TYPE_TKIP))
437#define is_valid_key_type(_t)      ((1 << (_t)) & VALID_KEY_TYPES)
438
439#define set_11n_tries(_series, _index) \
440        (SM((_series)[_index].Tries, AR_xmit_data_tries##_index))
441
442#define set_11n_rate(_series, _index) \
443        (SM((_series)[_index].Rate, AR_xmit_rate##_index))
444
445#define set_11n_pkt_dur_rts_cts(_series, _index) \
446        (SM((_series)[_index].PktDuration, AR_packet_dur##_index) |\
447         ((_series)[_index].RateFlags & HAL_RATESERIES_RTS_CTS   ?\
448         AR_rts_cts_qual##_index : 0))
449
450#define not_two_stream_rate(_rate) (((_rate) >0x8f) || ((_rate)<0x88))
451
452#define set_11n_tx_bf_ldpc( _series) \
453        ((( not_two_stream_rate((_series)[0].Rate) && (not_two_stream_rate((_series)[1].Rate)|| \
454        (!(_series)[1].Tries)) && (not_two_stream_rate((_series)[2].Rate)||(!(_series)[2].Tries)) \
455         && (not_two_stream_rate((_series)[3].Rate)||(!(_series)[3].Tries)))) \
456        ? AR_ldpc : 0)
457
458#define set_11n_rate_flags(_series, _index) \
459        ((_series)[_index].RateFlags & HAL_RATESERIES_2040 ? AR_2040_##_index : 0) \
460        |((_series)[_index].RateFlags & HAL_RATESERIES_HALFGI ? AR_gi##_index : 0) \
461        |((_series)[_index].RateFlags & HAL_RATESERIES_STBC ? AR_stbc##_index : 0) \
462        |SM((_series)[_index].ch_sel, AR_chain_sel##_index)
463
464#define set_11n_tx_power(_index, _txpower) \
465        SM(_txpower, AR_xmit_power##_index)
466
467
468#define IS_3CHAIN_TX(_ah) (AH9300(_ah)->ah_tx_chainmask == 7)
469/*
470 * Descriptor Access Functions
471 */
472/* XXX valid Tx rates will change for 3 stream support */
473#define VALID_PKT_TYPES \
474        ((1<<HAL_PKT_TYPE_NORMAL)|(1<<HAL_PKT_TYPE_ATIM)|\
475         (1<<HAL_PKT_TYPE_PSPOLL)|(1<<HAL_PKT_TYPE_PROBE_RESP)|\
476         (1<<HAL_PKT_TYPE_BEACON))
477#define is_valid_pkt_type(_t)      ((1<<(_t)) & VALID_PKT_TYPES)
478#define VALID_TX_RATES \
479        ((1<<0x0b)|(1<<0x0f)|(1<<0x0a)|(1<<0x0e)|(1<<0x09)|(1<<0x0d)|\
480         (1<<0x08)|(1<<0x0c)|(1<<0x1b)|(1<<0x1a)|(1<<0x1e)|(1<<0x19)|\
481         (1<<0x1d)|(1<<0x18)|(1<<0x1c))
482#define is_valid_tx_rate(_r)       ((1<<(_r)) & VALID_TX_RATES)
483
484        /* TX common functions */
485
486extern  HAL_BOOL ar9300_update_tx_trig_level(struct ath_hal *,
487        HAL_BOOL IncTrigLevel);
488extern  u_int16_t ar9300_get_tx_trig_level(struct ath_hal *);
489extern  HAL_BOOL ar9300_set_tx_queue_props(struct ath_hal *ah, int q,
490        const HAL_TXQ_INFO *q_info);
491extern  HAL_BOOL ar9300_get_tx_queue_props(struct ath_hal *ah, int q,
492        HAL_TXQ_INFO *q_info);
493extern  int ar9300_setup_tx_queue(struct ath_hal *ah, HAL_TX_QUEUE type,
494        const HAL_TXQ_INFO *q_info);
495extern  HAL_BOOL ar9300_release_tx_queue(struct ath_hal *ah, u_int q);
496extern  HAL_BOOL ar9300_reset_tx_queue(struct ath_hal *ah, u_int q);
497extern  u_int32_t ar9300_get_tx_dp(struct ath_hal *ah, u_int q);
498extern  HAL_BOOL ar9300_set_tx_dp(struct ath_hal *ah, u_int q, u_int32_t txdp);
499extern  HAL_BOOL ar9300_start_tx_dma(struct ath_hal *ah, u_int q);
500extern  u_int32_t ar9300_num_tx_pending(struct ath_hal *ah, u_int q);
501extern  HAL_BOOL ar9300_stop_tx_dma(struct ath_hal *ah, u_int q, u_int timeout);
502extern HAL_BOOL ar9300_stop_tx_dma_indv_que(struct ath_hal *ah, u_int q, u_int timeout);
503extern  HAL_BOOL ar9300_abort_tx_dma(struct ath_hal *ah);
504extern  void ar9300_get_tx_intr_queue(struct ath_hal *ah, u_int32_t *);
505
506extern  void ar9300_tx_req_intr_desc(struct ath_hal *ah, void *ds);
507extern  HAL_BOOL ar9300_fill_tx_desc(struct ath_hal *ah, void *ds, dma_addr_t *buf_addr,
508        u_int32_t *seg_len, u_int desc_id, u_int qcu, HAL_KEY_TYPE key_type, HAL_BOOL first_seg,
509        HAL_BOOL last_seg, const void *ds0);
510extern  void ar9300_set_desc_link(struct ath_hal *, void *ds, u_int32_t link);
511extern  void ar9300_get_desc_link_ptr(struct ath_hal *, void *ds, u_int32_t **link);
512extern  void ar9300_clear_tx_desc_status(struct ath_hal *ah, void *ds);
513#ifdef ATH_SWRETRY
514extern void ar9300_clear_dest_mask(struct ath_hal *ah, void *ds);
515#endif
516extern  HAL_STATUS ar9300_proc_tx_desc(struct ath_hal *ah, void *);
517extern  void ar9300_get_raw_tx_desc(struct ath_hal *ah, u_int32_t *);
518extern  void ar9300_get_tx_rate_code(struct ath_hal *ah, void *, struct ath_tx_status *);
519extern  u_int32_t ar9300_calc_tx_airtime(struct ath_hal *ah, void *, struct ath_tx_status *,
520        HAL_BOOL comp_wastedt, u_int8_t nbad, u_int8_t nframes);
521extern  void ar9300_setup_tx_status_ring(struct ath_hal *ah, void *, u_int32_t , u_int16_t);
522extern void ar9300_set_paprd_tx_desc(struct ath_hal *ah, void *ds, int chain_num);
523HAL_STATUS ar9300_is_tx_done(struct ath_hal *ah);
524extern void ar9300_set_11n_tx_desc(struct ath_hal *ah, void *ds,
525       u_int pkt_len, HAL_PKT_TYPE type, u_int tx_power,
526       u_int key_ix, HAL_KEY_TYPE key_type, u_int flags);
527extern void ar9300_set_rx_chainmask(struct ath_hal *ah, int rxchainmask);
528extern void ar9300_update_loc_ctl_reg(struct ath_hal *ah, int pos_bit);
529
530/* for tx_bf*/
531#define ar9300_set_11n_txbf_cal(ah, ds, cal_pos, code_rate, cec, opt)
532/* for tx_bf*/
533
534extern void ar9300_set_11n_rate_scenario(struct ath_hal *ah, void *ds,
535        void *lastds, u_int dur_update_en, u_int rts_cts_rate, u_int rts_cts_duration, HAL_11N_RATE_SERIES series[],
536       u_int nseries, u_int flags, u_int32_t smartAntenna);
537extern void ar9300_set_11n_aggr_first(struct ath_hal *ah, void *ds,
538       u_int aggr_len);
539extern void ar9300_set_11n_aggr_middle(struct ath_hal *ah, void *ds,
540       u_int num_delims);
541extern void ar9300_set_11n_aggr_last(struct ath_hal *ah, void *ds);
542extern void ar9300_clr_11n_aggr(struct ath_hal *ah, void *ds);
543extern void ar9300_set_11n_burst_duration(struct ath_hal *ah, void *ds,
544       u_int burst_duration);
545extern void ar9300_set_11n_rifs_burst_middle(struct ath_hal *ah, void *ds);
546extern void ar9300_set_11n_rifs_burst_last(struct ath_hal *ah, void *ds);
547extern void ar9300_clr_11n_rifs_burst(struct ath_hal *ah, void *ds);
548extern void ar9300_set_11n_aggr_rifs_burst(struct ath_hal *ah, void *ds);
549extern void ar9300_set_11n_virtual_more_frag(struct ath_hal *ah, void *ds,
550       u_int vmf);
551#ifdef AH_PRIVATE_DIAG
552extern void ar9300__cont_tx_mode(struct ath_hal *ah, void *ds, int mode);
553#endif
554
555	/* RX common functions */
556
557extern  u_int32_t ar9300_get_rx_dp(struct ath_hal *ath, HAL_RX_QUEUE qtype);
558extern  void ar9300_set_rx_dp(struct ath_hal *ah, u_int32_t rxdp, HAL_RX_QUEUE qtype);
559extern  void ar9300_enable_receive(struct ath_hal *ah);
560extern  HAL_BOOL ar9300_stop_dma_receive(struct ath_hal *ah, u_int timeout);
561extern  void ar9300_start_pcu_receive(struct ath_hal *ah, HAL_BOOL is_scanning);
562extern  void ar9300_stop_pcu_receive(struct ath_hal *ah);
563extern  void ar9300_set_multicast_filter(struct ath_hal *ah,
564        u_int32_t filter0, u_int32_t filter1);
565extern  u_int32_t ar9300_get_rx_filter(struct ath_hal *ah);
566extern  void ar9300_set_rx_filter(struct ath_hal *ah, u_int32_t bits);
567extern  HAL_BOOL ar9300_set_rx_sel_evm(struct ath_hal *ah, HAL_BOOL, HAL_BOOL);
568extern	bool ar9300_set_rx_abort(struct ath_hal *ah, HAL_BOOL);
569
570extern  HAL_STATUS ar9300_proc_rx_desc(struct ath_hal *ah,
571        struct ath_desc *, u_int32_t, struct ath_desc *, u_int64_t, struct ath_rx_status *);
572extern  HAL_STATUS ar9300_get_rx_key_idx(struct ath_hal *ah,
573        struct ath_desc *, u_int8_t *, u_int8_t *);
574extern  HAL_STATUS ar9300_proc_rx_desc_fast(struct ath_hal *ah, struct ath_desc *,
575        u_int32_t, struct ath_desc *, struct ath_rx_status *, void *);
576
577extern  void ar9300_promisc_mode(struct ath_hal *ah, HAL_BOOL enable);
578extern  void ar9300_read_pktlog_reg(struct ath_hal *ah, u_int32_t *, u_int32_t *, u_int32_t *, u_int32_t *);
579extern  void ar9300_write_pktlog_reg(struct ath_hal *ah, HAL_BOOL , u_int32_t , u_int32_t , u_int32_t , u_int32_t );
580
581
582#endif
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