1242723Sjhibbits/* 2242723Sjhibbits * CDDL HEADER START 3242723Sjhibbits * 4242723Sjhibbits * The contents of this file are subject to the terms of the 5242723Sjhibbits * Common Development and Distribution License, Version 1.0 only 6242723Sjhibbits * (the "License"). You may not use this file except in compliance 7242723Sjhibbits * with the License. 8242723Sjhibbits * 9242723Sjhibbits * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10242723Sjhibbits * or http://www.opensolaris.org/os/licensing. 11242723Sjhibbits * See the License for the specific language governing permissions 12242723Sjhibbits * and limitations under the License. 13242723Sjhibbits * 14242723Sjhibbits * When distributing Covered Code, include this CDDL HEADER in each 15242723Sjhibbits * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16242723Sjhibbits * If applicable, add the following below this CDDL HEADER, with the 17242723Sjhibbits * fields enclosed by brackets "[]" replaced with your own identifying 18242723Sjhibbits * information: Portions Copyright [yyyy] [name of copyright owner] 19242723Sjhibbits * 20242723Sjhibbits * CDDL HEADER END 21242723Sjhibbits * 22246275Sjhibbits * Portions Copyright 2012,2013 Justin Hibbits <jhibbits@freebsd.org> 23246275Sjhibbits * 24242723Sjhibbits * $FreeBSD$ 25242723Sjhibbits */ 26242723Sjhibbits/* 27242723Sjhibbits * Copyright 2004 Sun Microsystems, Inc. All rights reserved. 28242723Sjhibbits * Use is subject to license terms. 29242723Sjhibbits */ 30242723Sjhibbits 31242723Sjhibbits#include "assym.s" 32242723Sjhibbits 33242723Sjhibbits#define _ASM 34242723Sjhibbits 35242723Sjhibbits#include <sys/cpuvar_defs.h> 36242723Sjhibbits#include <sys/dtrace.h> 37242723Sjhibbits 38242723Sjhibbits#include <machine/asm.h> 39242723Sjhibbits/* 40242723Sjhibbits#include <machine/cpu.h> 41242723Sjhibbits*/ 42242723Sjhibbits 43242723Sjhibbits/* 44242723Sjhibbits * Primitives 45242723Sjhibbits */ 46242723Sjhibbits 47242723Sjhibbits .text 48242723Sjhibbits 49242723Sjhibbits/* 50242723Sjhibbitsvoid dtrace_membar_producer(void) 51242723Sjhibbits*/ 52242723SjhibbitsASENTRY_NOPROF(dtrace_membar_producer) 53254509Sjhibbits sync 54242723Sjhibbits blr 55242723SjhibbitsEND(dtrace_membar_producer) 56242723Sjhibbits 57242723Sjhibbits/* 58242723Sjhibbitsvoid dtrace_membar_consumer(void) 59242723Sjhibbits*/ 60242723SjhibbitsASENTRY_NOPROF(dtrace_membar_consumer) 61254509Sjhibbits isync 62242723Sjhibbits blr 63242723SjhibbitsEND(dtrace_membar_consumer) 64242723Sjhibbits 65242723Sjhibbits/* 66242723Sjhibbitsdtrace_icookie_t dtrace_interrupt_disable(void) 67242723Sjhibbits*/ 68242723SjhibbitsASENTRY_NOPROF(dtrace_interrupt_disable) 69242723Sjhibbits mfmsr %r3 70242723Sjhibbits andi. %r0,%r3,~PSL_EE@l 71242723Sjhibbits mtmsr %r0 72242723Sjhibbits blr 73242723SjhibbitsEND(dtrace_interrupt_disable) 74242723Sjhibbits 75242723Sjhibbits/* 76242723Sjhibbitsvoid dtrace_interrupt_enable(dtrace_icookie_t cookie) 77242723Sjhibbits*/ 78242723SjhibbitsASENTRY_NOPROF(dtrace_interrupt_enable) 79242723Sjhibbits mtmsr %r3 80242723Sjhibbits blr 81242723SjhibbitsEND(dtrace_interrupt_enable) 82242723Sjhibbits 83242723Sjhibbits/* 84242723Sjhibbitsuint32_t dtrace_cas32(uint32_t *target, uint32_t cmp, uint32_t new) 85242723Sjhibbits*/ 86242723SjhibbitsASENTRY_NOPROF(dtrace_cas32) 87242723Sjhibbits1: 88242723Sjhibbits lwarx %r0,0,%r3 89242723Sjhibbits cmpw %r4,%r0 90248457Sjhibbits bne 2f 91242723Sjhibbits stwcx. %r5,0,%r3 92248457Sjhibbits bne 1b 93248457Sjhibbits2: mr %r3,%r0 94242723Sjhibbits blr 95242723SjhibbitsEND(dtrace_cas32) 96242723Sjhibbits 97242723Sjhibbits/* 98242723Sjhibbitsvoid * 99242723Sjhibbitsdtrace_casptr(void *target, void *cmp, void *new) 100242723Sjhibbits*/ 101242723SjhibbitsASENTRY_NOPROF(dtrace_casptr) 102254509Sjhibbits#ifdef __powerpc64__ 103242723Sjhibbits1: 104254509Sjhibbits ldarx %r0,0,%r3 105254509Sjhibbits cmpd %r4,%r0 106254509Sjhibbits bne 2f 107254509Sjhibbits stdcx. %r5,0,%r3 108254509Sjhibbits bne 1b 109254509Sjhibbits#else 110254509Sjhibbits1: 111242723Sjhibbits lwarx %r0,0,%r3 112242723Sjhibbits cmpw %r4,%r0 113248457Sjhibbits bne 2f 114242723Sjhibbits stwcx. %r5,0,%r3 115248457Sjhibbits bne 1b 116254509Sjhibbits#endif 117248457Sjhibbits2: mr %r3,%r0 118242723Sjhibbits blr 119242723SjhibbitsEND(dtrace_casptr) 120242723Sjhibbits 121242723Sjhibbits 122242723Sjhibbits/* 123242723SjhibbitsXXX: unoptimized 124242723Sjhibbitsvoid 125242723Sjhibbitsdtrace_copy(uintptr_t src, uintptr_t dest, size_t size) 126242723Sjhibbits*/ 127242723SjhibbitsASENTRY_NOPROF(dtrace_copy) 128254634Sjhibbits subi %r7,%r3,1 129254634Sjhibbits subi %r8,%r4,1 130254634Sjhibbits mtctr %r5 131242723Sjhibbits1: 132242723Sjhibbits lbzu %r3,1(%r7) 133242723Sjhibbits stbu %r3,1(%r8) 134254634Sjhibbits bdnz 1b 135242723Sjhibbits2: 136242723Sjhibbits blr 137242723SjhibbitsEND(dtrace_copy) 138242723Sjhibbits 139242723Sjhibbits/* 140242723Sjhibbitsvoid 141242723Sjhibbitsdtrace_copystr(uintptr_t uaddr, uintptr_t kaddr, size_t size, 142242723Sjhibbits volatile uint16_t *flags) 143242723Sjhibbits*/ 144242723SjhibbitsASENTRY_NOPROF(dtrace_copystr) 145242723Sjhibbits addme %r7,%r3 146242723Sjhibbits addme %r8,%r4 147242723Sjhibbits1: 148242723Sjhibbits lbzu %r3,1(%r7) 149242723Sjhibbits stbu %r3,1(%r8) 150242723Sjhibbits addme %r5,%r5 151248457Sjhibbits beq 2f 152248457Sjhibbits or %r3,%r3,%r3 153248457Sjhibbits beq 2f 154242723Sjhibbits andi. %r0,%r5,0x0fff 155248457Sjhibbits beq 2f 156248457Sjhibbits lwz %r0,0(%r6) 157242723Sjhibbits andi. %r0,%r0,CPU_DTRACE_BADADDR 158248457Sjhibbits beq 1b 159242723Sjhibbits2: 160242723Sjhibbits blr 161242723SjhibbitsEND(dtrace_copystr) 162242723Sjhibbits 163242723Sjhibbits/* 164242723Sjhibbits * The panic() and cmn_err() functions invoke vpanic() as a common entry point 165242723Sjhibbits * into the panic code implemented in panicsys(). vpanic() is responsible 166242723Sjhibbits * for passing through the format string and arguments, and constructing a 167242723Sjhibbits * regs structure on the stack into which it saves the current register 168242723Sjhibbits * values. If we are not dying due to a fatal trap, these registers will 169242723Sjhibbits * then be preserved in panicbuf as the current processor state. Before 170242723Sjhibbits * invoking panicsys(), vpanic() activates the first panic trigger (see 171242723Sjhibbits * common/os/panic.c) and switches to the panic_stack if successful. Note that 172242723Sjhibbits * DTrace takes a slightly different panic path if it must panic from probe 173242723Sjhibbits * context. Instead of calling panic, it calls into dtrace_vpanic(), which 174242723Sjhibbits * sets up the initial stack as vpanic does, calls dtrace_panic_trigger(), and 175242723Sjhibbits * branches back into vpanic(). 176242723Sjhibbits */ 177242723Sjhibbits 178242723Sjhibbits/* 179242723Sjhibbitsvoid 180242723Sjhibbitsvpanic(const char *format, va_list alist) 181242723Sjhibbits*/ 182242723SjhibbitsASENTRY_NOPROF(vpanic) /* Initial stack layout: */ 183242723Sjhibbits 184242723Sjhibbitsvpanic_common: 185242723Sjhibbits blr 186242723SjhibbitsEND(vpanic) 187242723Sjhibbits 188242723Sjhibbits 189242723Sjhibbits 190242723Sjhibbits/* 191242723Sjhibbitsvoid 192242723Sjhibbitsdtrace_vpanic(const char *format, va_list alist) 193242723Sjhibbits*/ 194242723SjhibbitsASENTRY_NOPROF(dtrace_vpanic) /* Initial stack layout: */ 195242723Sjhibbits 196242723Sjhibbits#if 0 197242723Sjhibbits bl dtrace_panic_trigger /* %eax = dtrace_panic_trigger() */ 198242723Sjhibbits#endif 199242723Sjhibbits b vpanic_common 200242723SjhibbitsEND(dtrace_vpanic) 201242723Sjhibbits 202242723Sjhibbits/* 203242723Sjhibbitsuintptr_t 204242723Sjhibbitsdtrace_caller(int aframes) 205242723Sjhibbits*/ 206242723SjhibbitsASENTRY_NOPROF(dtrace_caller) 207242723Sjhibbits li %r3, -1 208242723Sjhibbits blr 209242723SjhibbitsEND(dtrace_caller) 210242723Sjhibbits 211