p3041ds.dts revision 227506
1/* 2 * P3041DS Device Tree Source 3 * 4 * Copyright 2010-2011 Freescale Semiconductor Inc. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are met: 8 * * Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * * Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * * Neither the name of Freescale Semiconductor nor the 14 * names of its contributors may be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * 18 * ALTERNATIVELY, this software may be distributed under the terms of the 19 * GNU General Public License ("GPL") as published by the Free Software 20 * Foundation, either version 2 of that License or (at your option) any 21 * later version. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY 24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY 27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34/* $FreeBSD: head/sys/boot/fdt/dts/p3041ds.dts 227506 2011-11-14 18:51:39Z marcel $ */ 35 36/dts-v1/; 37 38/ { 39 model = "fsl,P3041DS"; 40 compatible = "fsl,P3041DS"; 41 #address-cells = <2>; 42 #size-cells = <2>; 43 interrupt-parent = <&mpic>; 44 45 aliases { 46 ccsr = &soc; 47 48 serial0 = &serial0; 49 serial1 = &serial1; 50 serial2 = &serial2; 51 serial3 = &serial3; 52 pci0 = &pci0; 53 pci1 = &pci1; 54 pci2 = &pci2; 55 pci3 = &pci3; 56 usb0 = &usb0; 57 usb1 = &usb1; 58 dma0 = &dma0; 59 dma1 = &dma1; 60 sdhc = &sdhc; 61 msi0 = &msi0; 62 msi1 = &msi1; 63 msi2 = &msi2; 64 65 crypto = &crypto; 66 sec_jr0 = &sec_jr0; 67 sec_jr1 = &sec_jr1; 68 sec_jr2 = &sec_jr2; 69 sec_jr3 = &sec_jr3; 70 rtic_a = &rtic_a; 71 rtic_b = &rtic_b; 72 rtic_c = &rtic_c; 73 rtic_d = &rtic_d; 74 sec_mon = &sec_mon; 75 }; 76 77 cpus { 78 #address-cells = <1>; 79 #size-cells = <0>; 80 81 cpu0: PowerPC,e500mc@0 { 82 device_type = "cpu"; 83 reg = <0>; 84 next-level-cache = <&L2_0>; 85 L2_0: l2-cache { 86 next-level-cache = <&cpc>; 87 }; 88 }; 89 cpu1: PowerPC,e500mc@1 { 90 device_type = "cpu"; 91 reg = <1>; 92 next-level-cache = <&L2_1>; 93 L2_1: l2-cache { 94 next-level-cache = <&cpc>; 95 }; 96 }; 97 cpu2: PowerPC,e500mc@2 { 98 device_type = "cpu"; 99 reg = <2>; 100 next-level-cache = <&L2_2>; 101 L2_2: l2-cache { 102 next-level-cache = <&cpc>; 103 }; 104 }; 105 cpu3: PowerPC,e500mc@3 { 106 device_type = "cpu"; 107 reg = <3>; 108 next-level-cache = <&L2_3>; 109 L2_3: l2-cache { 110 next-level-cache = <&cpc>; 111 }; 112 }; 113 }; 114 115 memory { 116 device_type = "memory"; 117 }; 118 119 soc: soc@ffe000000 { 120 #address-cells = <1>; 121 #size-cells = <1>; 122 device_type = "soc"; 123 compatible = "simple-bus"; 124 ranges = <0x00000000 0xf 0xfe000000 0x1000000>; 125 reg = <0xf 0xfe000000 0 0x00001000>; 126 127 soc-sram-error { 128 compatible = "fsl,soc-sram-error"; 129 interrupts = <16 2 1 29>; 130 }; 131 132 corenet-law@0 { 133 compatible = "fsl,corenet-law"; 134 reg = <0x0 0x1000>; 135 fsl,num-laws = <32>; 136 }; 137 138 memory-controller@8000 { 139 compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller"; 140 reg = <0x8000 0x1000>; 141 interrupts = <16 2 1 23>; 142 }; 143 144 cpc: l3-cache-controller@10000 { 145 compatible = "fsl,p3041-l3-cache-controller", "fsl,p4080-l3-cache-controller", "cache"; 146 reg = <0x10000 0x1000>; 147 interrupts = <16 2 1 27>; 148 }; 149 150 corenet-cf@18000 { 151 compatible = "fsl,corenet-cf"; 152 reg = <0x18000 0x1000>; 153 interrupts = <16 2 1 31>; 154 fsl,ccf-num-csdids = <32>; 155 fsl,ccf-num-snoopids = <32>; 156 }; 157 158 iommu@20000 { 159 compatible = "fsl,pamu-v1.0", "fsl,pamu"; 160 reg = <0x20000 0x4000>; 161 interrupts = < 162 24 2 0 0 163 16 2 1 30>; 164 }; 165 166 mpic: pic@40000 { 167 clock-frequency = <0>; 168 interrupt-controller; 169 #address-cells = <0>; 170 #interrupt-cells = <4>; 171 reg = <0x40000 0x40000>; 172 compatible = "fsl,mpic", "chrp,open-pic"; 173 device_type = "open-pic"; 174 }; 175 176 msi0: msi@41600 { 177 compatible = "fsl,mpic-msi"; 178 reg = <0x41600 0x200>; 179 msi-available-ranges = <0 0x100>; 180 interrupts = < 181 0xe0 0 0 0 182 0xe1 0 0 0 183 0xe2 0 0 0 184 0xe3 0 0 0 185 0xe4 0 0 0 186 0xe5 0 0 0 187 0xe6 0 0 0 188 0xe7 0 0 0>; 189 }; 190 191 msi1: msi@41800 { 192 compatible = "fsl,mpic-msi"; 193 reg = <0x41800 0x200>; 194 msi-available-ranges = <0 0x100>; 195 interrupts = < 196 0xe8 0 0 0 197 0xe9 0 0 0 198 0xea 0 0 0 199 0xeb 0 0 0 200 0xec 0 0 0 201 0xed 0 0 0 202 0xee 0 0 0 203 0xef 0 0 0>; 204 }; 205 206 msi2: msi@41a00 { 207 compatible = "fsl,mpic-msi"; 208 reg = <0x41a00 0x200>; 209 msi-available-ranges = <0 0x100>; 210 interrupts = < 211 0xf0 0 0 0 212 0xf1 0 0 0 213 0xf2 0 0 0 214 0xf3 0 0 0 215 0xf4 0 0 0 216 0xf5 0 0 0 217 0xf6 0 0 0 218 0xf7 0 0 0>; 219 }; 220 221 guts: global-utilities@e0000 { 222 compatible = "fsl,qoriq-device-config-1.0"; 223 reg = <0xe0000 0xe00>; 224 fsl,has-rstcr; 225 #sleep-cells = <1>; 226 fsl,liodn-bits = <12>; 227 }; 228 229 pins: global-utilities@e0e00 { 230 compatible = "fsl,qoriq-pin-control-1.0"; 231 reg = <0xe0e00 0x200>; 232 #sleep-cells = <2>; 233 }; 234 235 clockgen: global-utilities@e1000 { 236 compatible = "fsl,p3041-clockgen", "fsl,qoriq-clockgen-1.0"; 237 reg = <0xe1000 0x1000>; 238 clock-frequency = <0>; 239 }; 240 241 rcpm: global-utilities@e2000 { 242 compatible = "fsl,qoriq-rcpm-1.0"; 243 reg = <0xe2000 0x1000>; 244 #sleep-cells = <1>; 245 }; 246 247 sfp: sfp@e8000 { 248 compatible = "fsl,p3041-sfp", "fsl,qoriq-sfp-1.0"; 249 reg = <0xe8000 0x1000>; 250 }; 251 252 serdes: serdes@ea000 { 253 compatible = "fsl,p3041-serdes"; 254 reg = <0xea000 0x1000>; 255 }; 256 257 dma0: dma@100300 { 258 #address-cells = <1>; 259 #size-cells = <1>; 260 compatible = "fsl,p3041-dma", "fsl,eloplus-dma"; 261 reg = <0x100300 0x4>; 262 ranges = <0x0 0x100100 0x200>; 263 cell-index = <0>; 264 dma-channel@0 { 265 compatible = "fsl,p3041-dma-channel", 266 "fsl,eloplus-dma-channel"; 267 reg = <0x0 0x80>; 268 cell-index = <0>; 269 interrupts = <28 2 0 0>; 270 }; 271 dma-channel@80 { 272 compatible = "fsl,p3041-dma-channel", 273 "fsl,eloplus-dma-channel"; 274 reg = <0x80 0x80>; 275 cell-index = <1>; 276 interrupts = <29 2 0 0>; 277 }; 278 dma-channel@100 { 279 compatible = "fsl,p3041-dma-channel", 280 "fsl,eloplus-dma-channel"; 281 reg = <0x100 0x80>; 282 cell-index = <2>; 283 interrupts = <30 2 0 0>; 284 }; 285 dma-channel@180 { 286 compatible = "fsl,p3041-dma-channel", 287 "fsl,eloplus-dma-channel"; 288 reg = <0x180 0x80>; 289 cell-index = <3>; 290 interrupts = <31 2 0 0>; 291 }; 292 }; 293 294 dma1: dma@101300 { 295 #address-cells = <1>; 296 #size-cells = <1>; 297 compatible = "fsl,p3041-dma", "fsl,eloplus-dma"; 298 reg = <0x101300 0x4>; 299 ranges = <0x0 0x101100 0x200>; 300 cell-index = <1>; 301 dma-channel@0 { 302 compatible = "fsl,p3041-dma-channel", 303 "fsl,eloplus-dma-channel"; 304 reg = <0x0 0x80>; 305 cell-index = <0>; 306 interrupts = <32 2 0 0>; 307 }; 308 dma-channel@80 { 309 compatible = "fsl,p3041-dma-channel", 310 "fsl,eloplus-dma-channel"; 311 reg = <0x80 0x80>; 312 cell-index = <1>; 313 interrupts = <33 2 0 0>; 314 }; 315 dma-channel@100 { 316 compatible = "fsl,p3041-dma-channel", 317 "fsl,eloplus-dma-channel"; 318 reg = <0x100 0x80>; 319 cell-index = <2>; 320 interrupts = <34 2 0 0>; 321 }; 322 dma-channel@180 { 323 compatible = "fsl,p3041-dma-channel", 324 "fsl,eloplus-dma-channel"; 325 reg = <0x180 0x80>; 326 cell-index = <3>; 327 interrupts = <35 2 0 0>; 328 }; 329 }; 330 331 spi@110000 { 332 #address-cells = <1>; 333 #size-cells = <0>; 334 compatible = "fsl,p3041-espi", "fsl,mpc8536-espi"; 335 reg = <0x110000 0x1000>; 336 interrupts = <53 0x2 0 0>; 337 fsl,espi-num-chipselects = <4>; 338 339 flash@0 { 340 #address-cells = <1>; 341 #size-cells = <1>; 342 compatible = "spansion,s25sl12801"; 343 reg = <0>; 344 spi-max-frequency = <40000000>; /* input clock */ 345 partition@u-boot { 346 label = "u-boot"; 347 reg = <0x00000000 0x00100000>; 348 read-only; 349 }; 350 partition@kernel { 351 label = "kernel"; 352 reg = <0x00100000 0x00500000>; 353 read-only; 354 }; 355 partition@dtb { 356 label = "dtb"; 357 reg = <0x00600000 0x00100000>; 358 read-only; 359 }; 360 partition@fs { 361 label = "file system"; 362 reg = <0x00700000 0x00900000>; 363 }; 364 }; 365 }; 366 367 sdhc: sdhc@114000 { 368 compatible = "fsl,p3041-esdhc", "fsl,esdhc"; 369 reg = <0x114000 0x1000>; 370 interrupts = <48 2 0 0>; 371 sdhci,auto-cmd12; 372 clock-frequency = <0>; 373 }; 374 375 i2c@118000 { 376 #address-cells = <1>; 377 #size-cells = <0>; 378 cell-index = <0>; 379 compatible = "fsl-i2c"; 380 reg = <0x118000 0x100>; 381 interrupts = <38 2 0 0>; 382 dfsrr; 383 }; 384 385 i2c@118100 { 386 #address-cells = <1>; 387 #size-cells = <0>; 388 cell-index = <1>; 389 compatible = "fsl-i2c"; 390 reg = <0x118100 0x100>; 391 interrupts = <38 2 0 0>; 392 dfsrr; 393 eeprom@51 { 394 compatible = "at24,24c256"; 395 reg = <0x51>; 396 }; 397 eeprom@52 { 398 compatible = "at24,24c256"; 399 reg = <0x52>; 400 }; 401 }; 402 403 i2c@119000 { 404 #address-cells = <1>; 405 #size-cells = <0>; 406 cell-index = <2>; 407 compatible = "fsl-i2c"; 408 reg = <0x119000 0x100>; 409 interrupts = <39 2 0 0>; 410 dfsrr; 411 }; 412 413 i2c@119100 { 414 #address-cells = <1>; 415 #size-cells = <0>; 416 cell-index = <3>; 417 compatible = "fsl-i2c"; 418 reg = <0x119100 0x100>; 419 interrupts = <39 2 0 0>; 420 dfsrr; 421 rtc@68 { 422 compatible = "dallas,ds3232"; 423 reg = <0x68>; 424 interrupts = <0x1 0x1 0 0>; 425 }; 426 }; 427 428 serial0: serial@11c500 { 429 cell-index = <0>; 430 device_type = "serial"; 431 compatible = "ns16550"; 432 reg = <0x11c500 0x100>; 433 clock-frequency = <0>; 434 interrupts = <36 2 0 0>; 435 }; 436 437 serial1: serial@11c600 { 438 cell-index = <1>; 439 device_type = "serial"; 440 compatible = "ns16550"; 441 reg = <0x11c600 0x100>; 442 clock-frequency = <0>; 443 interrupts = <36 2 0 0>; 444 }; 445 446 serial2: serial@11d500 { 447 cell-index = <2>; 448 device_type = "serial"; 449 compatible = "ns16550"; 450 reg = <0x11d500 0x100>; 451 clock-frequency = <0>; 452 interrupts = <37 2 0 0>; 453 }; 454 455 serial3: serial@11d600 { 456 cell-index = <3>; 457 device_type = "serial"; 458 compatible = "ns16550"; 459 reg = <0x11d600 0x100>; 460 clock-frequency = <0>; 461 interrupts = <37 2 0 0>; 462 }; 463 464 gpio0: gpio@130000 { 465 compatible = "fsl,p3041-gpio", "fsl,qoriq-gpio"; 466 reg = <0x130000 0x1000>; 467 interrupts = <55 2 0 0>; 468 #gpio-cells = <2>; 469 gpio-controller; 470 }; 471 472 usb0: usb@210000 { 473 compatible = "fsl,p3041-usb2-mph", 474 "fsl,mpc85xx-usb2-mph", "fsl-usb2-mph"; 475 reg = <0x210000 0x1000>; 476 #address-cells = <1>; 477 #size-cells = <0>; 478 interrupts = <44 0x2 0 0>; 479 phy_type = "utmi"; 480 port0; 481 }; 482 483 usb1: usb@211000 { 484 compatible = "fsl,p3041-usb2-dr", 485 "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr"; 486 reg = <0x211000 0x1000>; 487 #address-cells = <1>; 488 #size-cells = <0>; 489 interrupts = <45 0x2 0 0>; 490 dr_mode = "host"; 491 phy_type = "utmi"; 492 }; 493 494 sata@220000 { 495 compatible = "fsl,p3041-sata", "fsl,pq-sata-v2"; 496 reg = <0x220000 0x1000>; 497 interrupts = <68 0x2 0 0>; 498 }; 499 500 sata@221000 { 501 compatible = "fsl,p3041-sata", "fsl,pq-sata-v2"; 502 reg = <0x221000 0x1000>; 503 interrupts = <69 0x2 0 0>; 504 }; 505 506 crypto: crypto@300000 { 507 compatible = "fsl,sec-v4.2", "fsl,sec-v4.0"; 508 #address-cells = <1>; 509 #size-cells = <1>; 510 reg = <0x300000 0x10000>; 511 ranges = <0 0x300000 0x10000>; 512 interrupts = <92 2 0 0>; 513 514 sec_jr0: jr@1000 { 515 compatible = "fsl,sec-v4.2-job-ring", 516 "fsl,sec-v4.0-job-ring"; 517 reg = <0x1000 0x1000>; 518 interrupts = <88 2 0 0>; 519 }; 520 521 sec_jr1: jr@2000 { 522 compatible = "fsl,sec-v4.2-job-ring", 523 "fsl,sec-v4.0-job-ring"; 524 reg = <0x2000 0x1000>; 525 interrupts = <89 2 0 0>; 526 }; 527 528 sec_jr2: jr@3000 { 529 compatible = "fsl,sec-v4.2-job-ring", 530 "fsl,sec-v4.0-job-ring"; 531 reg = <0x3000 0x1000>; 532 interrupts = <90 2 0 0>; 533 }; 534 535 sec_jr3: jr@4000 { 536 compatible = "fsl,sec-v4.2-job-ring", 537 "fsl,sec-v4.0-job-ring"; 538 reg = <0x4000 0x1000>; 539 interrupts = <91 2 0 0>; 540 }; 541 542 rtic@6000 { 543 compatible = "fsl,sec-v4.2-rtic", 544 "fsl,sec-v4.0-rtic"; 545 #address-cells = <1>; 546 #size-cells = <1>; 547 reg = <0x6000 0x100>; 548 ranges = <0x0 0x6100 0xe00>; 549 550 rtic_a: rtic-a@0 { 551 compatible = "fsl,sec-v4.2-rtic-memory", 552 "fsl,sec-v4.0-rtic-memory"; 553 reg = <0x00 0x20 0x100 0x80>; 554 }; 555 556 rtic_b: rtic-b@20 { 557 compatible = "fsl,sec-v4.2-rtic-memory", 558 "fsl,sec-v4.0-rtic-memory"; 559 reg = <0x20 0x20 0x200 0x80>; 560 }; 561 562 rtic_c: rtic-c@40 { 563 compatible = "fsl,sec-v4.2-rtic-memory", 564 "fsl,sec-v4.0-rtic-memory"; 565 reg = <0x40 0x20 0x300 0x80>; 566 }; 567 568 rtic_d: rtic-d@60 { 569 compatible = "fsl,sec-v4.2-rtic-memory", 570 "fsl,sec-v4.0-rtic-memory"; 571 reg = <0x60 0x20 0x500 0x80>; 572 }; 573 }; 574 }; 575 576 sec_mon: sec_mon@314000 { 577 compatible = "fsl,sec-v4.2-mon", "fsl,sec-v4.0-mon"; 578 reg = <0x314000 0x1000>; 579 interrupts = <93 2 0 0>; 580 }; 581 }; 582 583 localbus@ffe124000 { 584 compatible = "fsl,p3041-elbc", "fsl,elbc", "simple-bus"; 585 reg = <0xf 0xfe124000 0 0x1000>; 586 interrupts = <25 2 0 0>; 587 #address-cells = <2>; 588 #size-cells = <1>; 589 590 ranges = <0 0 0xf 0xe8000000 0x08000000 591 3 0 0xf 0xffdf0000 0x00008000>; 592 593 flash@0,0 { 594 compatible = "cfi-flash"; 595 reg = <0 0 0x08000000>; 596 bank-width = <2>; 597 device-width = <2>; 598 }; 599 600 board-control@3,0 { 601 compatible = "fsl,p3041ds-pixis"; 602 reg = <3 0 0x20>; 603 }; 604 }; 605 606 pci0: pcie@ffe200000 { 607 compatible = "fsl,p3041-pcie", "fsl,qoriq-pcie-v2.2"; 608 device_type = "pci"; 609 #size-cells = <2>; 610 #address-cells = <3>; 611 reg = <0xf 0xfe200000 0 0x1000>; 612 bus-range = <0x0 0xff>; 613 ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000 614 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>; 615 clock-frequency = <0x1fca055>; 616 fsl,msi = <&msi0>; 617 interrupts = <16 2 1 15>; 618 pcie@0 { 619 reg = <0 0 0 0 0>; 620 #interrupt-cells = <1>; 621 #size-cells = <2>; 622 #address-cells = <3>; 623 device_type = "pci"; 624 interrupts = <16 2 1 15>; 625 interrupt-map-mask = <0xf800 0 0 7>; 626 interrupt-map = < 627 /* IDSEL 0x0 */ 628 0000 0 0 1 &mpic 40 1 0 0 629 0000 0 0 2 &mpic 1 1 0 0 630 0000 0 0 3 &mpic 2 1 0 0 631 0000 0 0 4 &mpic 3 1 0 0 632 >; 633 ranges = <0x02000000 0 0xe0000000 634 0x02000000 0 0xe0000000 635 0 0x20000000 636 637 0x01000000 0 0x00000000 638 0x01000000 0 0x00000000 639 0 0x00010000>; 640 }; 641 }; 642 643 pci1: pcie@ffe201000 { 644 compatible = "fsl,p3041-pcie", "fsl,qoriq-pcie-v2.2"; 645 device_type = "pci"; 646 #size-cells = <2>; 647 #address-cells = <3>; 648 reg = <0xf 0xfe201000 0 0x1000>; 649 bus-range = <0 0xff>; 650 ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000 651 0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>; 652 clock-frequency = <0x1fca055>; 653 fsl,msi = <&msi1>; 654 interrupts = <16 2 1 14>; 655 pcie@0 { 656 reg = <0 0 0 0 0>; 657 #interrupt-cells = <1>; 658 #size-cells = <2>; 659 #address-cells = <3>; 660 device_type = "pci"; 661 interrupts = <16 2 1 14>; 662 interrupt-map-mask = <0xf800 0 0 7>; 663 interrupt-map = < 664 /* IDSEL 0x0 */ 665 0000 0 0 1 &mpic 41 1 0 0 666 0000 0 0 2 &mpic 5 1 0 0 667 0000 0 0 3 &mpic 6 1 0 0 668 0000 0 0 4 &mpic 7 1 0 0 669 >; 670 ranges = <0x02000000 0 0xe0000000 671 0x02000000 0 0xe0000000 672 0 0x20000000 673 674 0x01000000 0 0x00000000 675 0x01000000 0 0x00000000 676 0 0x00010000>; 677 }; 678 }; 679 680 pci2: pcie@ffe202000 { 681 compatible = "fsl,p3041-pcie", "fsl,qoriq-pcie-v2.2"; 682 device_type = "pci"; 683 #size-cells = <2>; 684 #address-cells = <3>; 685 reg = <0xf 0xfe202000 0 0x1000>; 686 bus-range = <0x0 0xff>; 687 ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000 688 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>; 689 clock-frequency = <0x1fca055>; 690 fsl,msi = <&msi2>; 691 interrupts = <16 2 1 13>; 692 pcie@0 { 693 reg = <0 0 0 0 0>; 694 #interrupt-cells = <1>; 695 #size-cells = <2>; 696 #address-cells = <3>; 697 device_type = "pci"; 698 interrupts = <16 2 1 13>; 699 interrupt-map-mask = <0xf800 0 0 7>; 700 interrupt-map = < 701 /* IDSEL 0x0 */ 702 0000 0 0 1 &mpic 42 1 0 0 703 0000 0 0 2 &mpic 9 1 0 0 704 0000 0 0 3 &mpic 10 1 0 0 705 0000 0 0 4 &mpic 11 1 0 0 706 >; 707 ranges = <0x02000000 0 0xe0000000 708 0x02000000 0 0xe0000000 709 0 0x20000000 710 711 0x01000000 0 0x00000000 712 0x01000000 0 0x00000000 713 0 0x00010000>; 714 }; 715 }; 716 717 pci3: pcie@ffe203000 { 718 compatible = "fsl,p3041-pcie", "fsl,qoriq-pcie-v2.2"; 719 device_type = "pci"; 720 #size-cells = <2>; 721 #address-cells = <3>; 722 reg = <0xf 0xfe203000 0 0x1000>; 723 bus-range = <0x0 0xff>; 724 ranges = <0x02000000 0 0xe0000000 0xc 0x60000000 0 0x20000000 725 0x01000000 0 0x00000000 0xf 0xf8030000 0 0x00010000>; 726 clock-frequency = <0x1fca055>; 727 fsl,msi = <&msi2>; 728 interrupts = <16 2 1 12>; 729 pcie@0 { 730 reg = <0 0 0 0 0>; 731 #interrupt-cells = <1>; 732 #size-cells = <2>; 733 #address-cells = <3>; 734 device_type = "pci"; 735 interrupts = <16 2 1 12>; 736 interrupt-map-mask = <0xf800 0 0 7>; 737 interrupt-map = < 738 /* IDSEL 0x0 */ 739 0000 0 0 1 &mpic 43 1 0 0 740 0000 0 0 2 &mpic 0 1 0 0 741 0000 0 0 3 &mpic 4 1 0 0 742 0000 0 0 4 &mpic 8 1 0 0 743 >; 744 ranges = <0x02000000 0 0xe0000000 745 0x02000000 0 0xe0000000 746 0 0x20000000 747 748 0x01000000 0 0x00000000 749 0x01000000 0 0x00000000 750 0 0x00010000>; 751 }; 752 }; 753}; 754