1256912Sbrooks/*- 2256912Sbrooks * Copyright (c) 2012-2013 Robert N. M. Watson 3256912Sbrooks * Copyright (c) 2013 SRI International 4256912Sbrooks * All rights reserved. 5256912Sbrooks * 6256912Sbrooks * This software was developed by SRI International and the University of 7256912Sbrooks * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237) 8256912Sbrooks * ("CTSRD"), as part of the DARPA CRASH research programme. 9256912Sbrooks * 10256912Sbrooks * Redistribution and use in source and binary forms, with or without 11256912Sbrooks * modification, are permitted provided that the following conditions 12256912Sbrooks * are met: 13256912Sbrooks * 1. Redistributions of source code must retain the above copyright 14256912Sbrooks * notice, this list of conditions and the following disclaimer. 15256912Sbrooks * 2. Redistributions in binary form must reproduce the above copyright 16256912Sbrooks * notice, this list of conditions and the following disclaimer in the 17256912Sbrooks * documentation and/or other materials provided with the distribution. 18256912Sbrooks * 19256912Sbrooks * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20256912Sbrooks * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21256912Sbrooks * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22256912Sbrooks * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 23256912Sbrooks * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24256912Sbrooks * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25256912Sbrooks * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26256912Sbrooks * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27256912Sbrooks * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28256912Sbrooks * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29256912Sbrooks * SUCH DAMAGE. 30256912Sbrooks * 31256912Sbrooks * $FreeBSD$ 32256912Sbrooks */ 33256912Sbrooks 34256912Sbrooks/dts-v1/; 35256912Sbrooks 36256912Sbrooks/* 37256912Sbrooks * Device names here have been largely made up on the spot, especially for the 38256912Sbrooks * "compatible" strings, and might want to be revised. 39256912Sbrooks * 40256912Sbrooks * For now, use 32-bit addressing as our Avalon bus is 32-bit. However, in 41256912Sbrooks * the future, we should likely change to 64-bit. 42256912Sbrooks */ 43256912Sbrooks 44256912Sbrooks/ { 45256912Sbrooks model = "SRI/Cambridge BERI simulation"; 46256912Sbrooks compatible = "sri-cambridge,beri-sim"; 47256912Sbrooks #address-cells = <1>; 48256912Sbrooks #size-cells = <1>; 49256912Sbrooks 50256912Sbrooks cpus { 51256912Sbrooks #address-cells = <1>; 52256912Sbrooks #size-cells = <1>; 53256912Sbrooks 54256912Sbrooks /* 55256912Sbrooks * Secondary CPUs all start disabled and use the 56256912Sbrooks * spin-table enable method. cpu-release-addr must be 57256912Sbrooks * specified for each cpu other than cpu@0. Values of 58256912Sbrooks * cpu-release-addr grow down from 0x100000 (kernel). 59256912Sbrooks */ 60256912Sbrooks status = "disabled"; 61256912Sbrooks enable-method = "spin-table"; 62256912Sbrooks 63256912Sbrooks cpu@0 { 64256912Sbrooks device-type = "cpu"; 65256912Sbrooks compatible = "sri-cambridge,beri"; 66256912Sbrooks 67256912Sbrooks reg = <0>; 68256912Sbrooks status = "okay"; 69256912Sbrooks }; 70256912Sbrooks 71256912Sbrooks/* 72256912Sbrooks cpu@1 { 73256912Sbrooks device-type = "cpu"; 74256912Sbrooks compatible = "sri-cambridge,beri"; 75256912Sbrooks 76256912Sbrooks reg = <1>; 77256912Sbrooks // XXX: should we need cached prefix? 78256912Sbrooks cpu-release-addr = <0xffffffff 0x800fffe0>; 79256912Sbrooks }; 80256912Sbrooks*/ 81256912Sbrooks }; 82256912Sbrooks 83256912Sbrooks soc { 84256912Sbrooks #address-cells = <1>; 85256912Sbrooks #size-cells = <1>; 86256912Sbrooks #interrupt-cells = <1>; 87256912Sbrooks 88256912Sbrooks /* 89256912Sbrooks * Declare mips,mips4k since BERI doesn't (yet) have a PIC, so 90256912Sbrooks * we use mips4k coprocessor 0 interrupt management directly. 91256912Sbrooks */ 92256912Sbrooks compatible = "simple-bus", "mips,mips4k"; 93256912Sbrooks ranges = <>; 94256912Sbrooks 95256912Sbrooks memory { 96256912Sbrooks device_type = "memory"; 97256912Sbrooks reg = <0x0 0x4000000>; // 64M at 0x0 98256912Sbrooks }; 99256912Sbrooks 100256912Sbrooks beripic: beripic@7f804000 { 101256912Sbrooks compatible = "sri-cambridge,beri-pic"; 102256912Sbrooks interrupt-controller; 103256912Sbrooks #address-cells = <0>; 104256912Sbrooks #interrupt-cells = <1>; 105256912Sbrooks reg = <0x7f804000 0x400 106256912Sbrooks 0x7f806000 0x10 107256912Sbrooks 0x7f806080 0x10 108256912Sbrooks 0x7f806100 0x10>; 109256912Sbrooks interrupts = <0 1 2 3 4>; 110256912Sbrooks hard-interrupt-sources = <64>; 111256912Sbrooks soft-interrupt-sources = <64>; 112256912Sbrooks }; 113256912Sbrooks 114256912Sbrooks serial@7f000000 { 115256912Sbrooks compatible = "altera,jtag_uart-11_0"; 116256912Sbrooks reg = <0x7f000000 0x40>; 117256912Sbrooks interrupts = <0>; 118256912Sbrooks interrupt-parent = <&beripic>; 119256912Sbrooks }; 120256912Sbrooks 121256912Sbrooks serial@7f001000 { 122256912Sbrooks compatible = "altera,jtag_uart-11_0"; 123256912Sbrooks reg = <0x7f001000 0x40>; 124256912Sbrooks }; 125256912Sbrooks 126256912Sbrooks serial@7f002000 { 127256912Sbrooks compatible = "altera,jtag_uart-11_0"; 128256912Sbrooks reg = <0x7f002000 0x40>; 129256912Sbrooks }; 130256912Sbrooks 131256912Sbrooks sdcard@7f008000 { 132256912Sbrooks compatible = "altera,sdcard_11_2011"; 133256912Sbrooks reg = <0x7f008000 0x400>; 134256912Sbrooks }; 135256912Sbrooks 136256912Sbrooks avgen@0x7f00a000 { 137256912Sbrooks compatible = "sri-cambridge,avgen"; 138256912Sbrooks reg = <0x7f00a000 0x14>; 139256912Sbrooks sri-cambridge,width = <4>; 140256912Sbrooks sri-cambridge,fileio = "rw"; 141256912Sbrooks sri-cambridge,devname = "berirom"; 142256912Sbrooks }; 143256912Sbrooks }; 144256912Sbrooks}; 145