1164426Ssam/* $NetBSD: ixp425_pci.c,v 1.5 2006/04/10 03:36:03 simonb Exp $ */ 2164426Ssam 3164426Ssam/* 4164426Ssam * Copyright (c) 2003 5164426Ssam * Ichiro FUKUHARA <ichiro@ichiro.org>. 6164426Ssam * All rights reserved. 7164426Ssam * 8164426Ssam * Redistribution and use in source and binary forms, with or without 9164426Ssam * modification, are permitted provided that the following conditions 10164426Ssam * are met: 11164426Ssam * 1. Redistributions of source code must retain the above copyright 12164426Ssam * notice, this list of conditions and the following disclaimer. 13164426Ssam * 2. Redistributions in binary form must reproduce the above copyright 14164426Ssam * notice, this list of conditions and the following disclaimer in the 15164426Ssam * documentation and/or other materials provided with the distribution. 16164426Ssam * 3. All advertising materials mentioning features or use of this software 17164426Ssam * must display the following acknowledgement: 18164426Ssam * This product includes software developed by Ichiro FUKUHARA. 19164426Ssam * 4. The name of the company nor the name of the author may be used to 20164426Ssam * endorse or promote products derived from this software without specific 21164426Ssam * prior written permission. 22164426Ssam * 23164426Ssam * THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR 24164426Ssam * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25164426Ssam * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26164426Ssam * IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR 27164426Ssam * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28164426Ssam * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 29164426Ssam * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30164426Ssam * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31164426Ssam * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32164426Ssam * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33164426Ssam * SUCH DAMAGE. 34164426Ssam */ 35164426Ssam 36164426Ssam#include <sys/cdefs.h> 37164426Ssam__FBSDID("$FreeBSD$"); 38164426Ssam 39164426Ssam#include <sys/param.h> 40164426Ssam#include <sys/systm.h> 41164426Ssam#include <sys/malloc.h> 42166064Scognet#define _ARM32_BUS_DMA_PRIVATE 43164426Ssam#include <sys/bus.h> 44164426Ssam#include <sys/kernel.h> 45164426Ssam#include <sys/module.h> 46164426Ssam#include <sys/rman.h> 47164426Ssam 48229125Smarius#include <dev/pci/pcivar.h> 49229125Smarius 50164426Ssam#include <machine/bus.h> 51164426Ssam#include <machine/cpu.h> 52164426Ssam#include <machine/pcb.h> 53229125Smarius 54164426Ssam#include <vm/vm.h> 55164426Ssam#include <vm/pmap.h> 56164426Ssam#include <vm/vm_extern.h> 57164426Ssam#include <machine/pmap.h> 58164426Ssam 59164426Ssam#include <arm/xscale/ixp425/ixp425reg.h> 60164426Ssam#include <arm/xscale/ixp425/ixp425var.h> 61164426Ssam 62164426Ssam#include <dev/pci/pcib_private.h> 63164426Ssam#include "pcib_if.h" 64164426Ssam 65164426Ssam#include <dev/pci/pcireg.h> 66164426Ssamextern struct ixp425_softc *ixp425_softc; 67164426Ssam 68164426Ssam#define PCI_CSR_WRITE_4(sc, reg, data) \ 69164426Ssam bus_write_4(sc->sc_csr, reg, data) 70164426Ssam 71164426Ssam#define PCI_CSR_READ_4(sc, reg) \ 72164426Ssam bus_read_4(sc->sc_csr, reg) 73164426Ssam 74164426Ssam#define PCI_CONF_LOCK(s) (s) = disable_interrupts(I32_bit) 75164426Ssam#define PCI_CONF_UNLOCK(s) restore_interrupts((s)) 76164426Ssam 77164426Ssamstatic device_probe_t ixppcib_probe; 78164426Ssamstatic device_attach_t ixppcib_attach; 79164426Ssamstatic bus_read_ivar_t ixppcib_read_ivar; 80164426Ssamstatic bus_write_ivar_t ixppcib_write_ivar; 81164426Ssamstatic bus_setup_intr_t ixppcib_setup_intr; 82164426Ssamstatic bus_teardown_intr_t ixppcib_teardown_intr; 83164426Ssamstatic bus_alloc_resource_t ixppcib_alloc_resource; 84164426Ssamstatic bus_activate_resource_t ixppcib_activate_resource; 85164426Ssamstatic bus_deactivate_resource_t ixppcib_deactivate_resource; 86164426Ssamstatic bus_release_resource_t ixppcib_release_resource; 87164426Ssamstatic pcib_maxslots_t ixppcib_maxslots; 88164426Ssamstatic pcib_read_config_t ixppcib_read_config; 89164426Ssamstatic pcib_write_config_t ixppcib_write_config; 90164426Ssamstatic pcib_route_interrupt_t ixppcib_route_interrupt; 91164426Ssam 92164426Ssamstatic int 93164426Ssamixppcib_probe(device_t dev) 94164426Ssam{ 95186352Ssam device_set_desc(dev, "IXP4XX PCI Bus"); 96164426Ssam return (0); 97164426Ssam} 98164426Ssam 99164426Ssamstatic void 100164426Ssamixp425_pci_conf_reg_write(struct ixppcib_softc *sc, uint32_t reg, 101164426Ssam uint32_t data) 102164426Ssam{ 103189548Ssam PCI_CSR_WRITE_4(sc, PCI_CRP_AD_CBE, ((reg & ~3) | COMMAND_CRP_WRITE)); 104189548Ssam PCI_CSR_WRITE_4(sc, PCI_CRP_AD_WDATA, data); 105164426Ssam} 106164426Ssam 107164426Ssamstatic int 108164426Ssamixppcib_attach(device_t dev) 109164426Ssam{ 110164426Ssam int rid; 111164426Ssam struct ixppcib_softc *sc; 112164426Ssam 113164426Ssam sc = device_get_softc(dev); 114164426Ssam 115164426Ssam rid = 0; 116164426Ssam sc->sc_csr = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 117164426Ssam IXP425_PCI_HWBASE, IXP425_PCI_HWBASE + IXP425_PCI_SIZE, 118164426Ssam IXP425_PCI_SIZE, RF_ACTIVE); 119164426Ssam if (sc->sc_csr == NULL) 120164426Ssam panic("cannot allocate PCI CSR registers"); 121164426Ssam 122164426Ssam ixp425_md_attach(dev); 123164426Ssam /* always setup the base, incase another OS messes w/ it */ 124164426Ssam PCI_CSR_WRITE_4(sc, PCI_PCIMEMBASE, 0x48494a4b); 125164426Ssam 126164426Ssam rid = 0; 127164426Ssam sc->sc_mem = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 128164426Ssam IXP425_PCI_MEM_HWBASE, IXP425_PCI_MEM_HWBASE + IXP425_PCI_MEM_SIZE, 129164426Ssam IXP425_PCI_MEM_SIZE, RF_ACTIVE); 130164426Ssam if (sc->sc_mem == NULL) 131164426Ssam panic("cannot allocate PCI MEM space"); 132164426Ssam 133186352Ssam /* NB: PCI dma window is 64M so anything above must be bounced */ 134186352Ssam if (bus_dma_tag_create(NULL, 1, 0, IXP425_AHB_OFFSET + 64 * 1024 * 1024, 135236987Simp BUS_SPACE_MAXADDR, NULL, NULL, 0xffffffff, 0xff, 0xffffffff, 0, 136166064Scognet NULL, NULL, &sc->sc_dmat)) 137166064Scognet panic("couldn't create the PCI dma tag !"); 138236987Simp /* 139166064Scognet * The PCI bus can only address 64MB. However, due to the way our 140166064Scognet * implementation of busdma works, busdma can't tell if a device 141166064Scognet * is a PCI device or not. So defaults to the PCI dma tag, which 142166064Scognet * restrict the DMA'able memory to the first 64MB, and explicitely 143166064Scognet * create less restrictive tags for non-PCI devices. 144166064Scognet */ 145166064Scognet arm_root_dma_tag = sc->sc_dmat; 146164426Ssam /* 147164426Ssam * Initialize the bus space tags. 148164426Ssam */ 149164426Ssam ixp425_io_bs_init(&sc->sc_pci_iot, sc); 150164426Ssam ixp425_mem_bs_init(&sc->sc_pci_memt, sc); 151164426Ssam 152164426Ssam sc->sc_dev = dev; 153164426Ssam 154164426Ssam /* Initialize memory and i/o rmans. */ 155164426Ssam sc->sc_io_rman.rm_type = RMAN_ARRAY; 156186352Ssam sc->sc_io_rman.rm_descr = "IXP4XX PCI I/O Ports"; 157164426Ssam if (rman_init(&sc->sc_io_rman) != 0 || 158236987Simp rman_manage_region(&sc->sc_io_rman, 0, 159164426Ssam IXP425_PCI_IO_SIZE) != 0) { 160164426Ssam panic("ixppcib_probe: failed to set up I/O rman"); 161164426Ssam } 162164426Ssam 163164426Ssam sc->sc_mem_rman.rm_type = RMAN_ARRAY; 164186352Ssam sc->sc_mem_rman.rm_descr = "IXP4XX PCI Memory"; 165164426Ssam if (rman_init(&sc->sc_mem_rman) != 0 || 166164426Ssam rman_manage_region(&sc->sc_mem_rman, IXP425_PCI_MEM_HWBASE, 167164426Ssam IXP425_PCI_MEM_HWBASE + IXP425_PCI_MEM_SIZE) != 0) { 168164426Ssam panic("ixppcib_probe: failed to set up memory rman"); 169164426Ssam } 170164426Ssam 171164426Ssam /* 172164426Ssam * PCI->AHB address translation 173164426Ssam * begin at the physical memory start + OFFSET 174164426Ssam */ 175164426Ssam PCI_CSR_WRITE_4(sc, PCI_AHBMEMBASE, 176186352Ssam (IXP425_AHB_OFFSET & 0xFF000000) + 177186352Ssam ((IXP425_AHB_OFFSET & 0xFF000000) >> 8) + 178186352Ssam ((IXP425_AHB_OFFSET & 0xFF000000) >> 16) + 179186352Ssam ((IXP425_AHB_OFFSET & 0xFF000000) >> 24) + 180164426Ssam 0x00010203); 181164426Ssam 182164426Ssam#define IXPPCIB_WRITE_CONF(sc, reg, val) \ 183164426Ssam ixp425_pci_conf_reg_write(sc, reg, val) 184164426Ssam /* Write Mapping registers PCI Configuration Registers */ 185164426Ssam /* Base Address 0 - 3 */ 186186352Ssam IXPPCIB_WRITE_CONF(sc, PCI_MAPREG_BAR0, IXP425_AHB_OFFSET + 0x00000000); 187186352Ssam IXPPCIB_WRITE_CONF(sc, PCI_MAPREG_BAR1, IXP425_AHB_OFFSET + 0x01000000); 188186352Ssam IXPPCIB_WRITE_CONF(sc, PCI_MAPREG_BAR2, IXP425_AHB_OFFSET + 0x02000000); 189186352Ssam IXPPCIB_WRITE_CONF(sc, PCI_MAPREG_BAR3, IXP425_AHB_OFFSET + 0x03000000); 190164426Ssam 191164426Ssam /* Base Address 4 */ 192164426Ssam IXPPCIB_WRITE_CONF(sc, PCI_MAPREG_BAR4, 0xffffffff); 193164426Ssam 194164426Ssam /* Base Address 5 */ 195164426Ssam IXPPCIB_WRITE_CONF(sc, PCI_MAPREG_BAR5, 0x00000000); 196164426Ssam 197164426Ssam /* Assert some PCI errors */ 198164426Ssam PCI_CSR_WRITE_4(sc, PCI_ISR, ISR_AHBE | ISR_PPE | ISR_PFE | ISR_PSE); 199164426Ssam 200164426Ssam#ifdef __ARMEB__ 201164426Ssam /* 202164426Ssam * Set up byte lane swapping between little-endian PCI 203164426Ssam * and the big-endian AHB bus 204164426Ssam */ 205164426Ssam PCI_CSR_WRITE_4(sc, PCI_CSR, CSR_IC | CSR_ABE | CSR_PDS); 206164426Ssam#else 207164426Ssam PCI_CSR_WRITE_4(sc, PCI_CSR, CSR_IC | CSR_ABE); 208164426Ssam#endif 209164426Ssam 210164426Ssam /* 211164426Ssam * Enable bus mastering and I/O,memory access 212164426Ssam */ 213164426Ssam IXPPCIB_WRITE_CONF(sc, PCIR_COMMAND, 214164426Ssam PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN); 215164426Ssam 216164426Ssam /* 217164426Ssam * Wait some more to ensure PCI devices have stabilised. 218164426Ssam */ 219164426Ssam DELAY(50000); 220164426Ssam 221164426Ssam device_add_child(dev, "pci", -1); 222164426Ssam return (bus_generic_attach(dev)); 223164426Ssam} 224164426Ssam 225164426Ssamstatic int 226164426Ssamixppcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 227164426Ssam{ 228164426Ssam struct ixppcib_softc *sc; 229164426Ssam 230164426Ssam sc = device_get_softc(dev); 231164426Ssam switch (which) { 232172394Smarius case PCIB_IVAR_DOMAIN: 233172394Smarius *result = 0; 234172394Smarius return (0); 235164426Ssam case PCIB_IVAR_BUS: 236164426Ssam *result = sc->sc_bus; 237164426Ssam return (0); 238164426Ssam } 239164426Ssam 240164426Ssam return (ENOENT); 241164426Ssam} 242164426Ssam 243164426Ssamstatic int 244164426Ssamixppcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 245164426Ssam{ 246164426Ssam struct ixppcib_softc *sc; 247164426Ssam 248164426Ssam sc = device_get_softc(dev); 249164426Ssam switch (which) { 250172394Smarius case PCIB_IVAR_DOMAIN: 251172394Smarius return (EINVAL); 252164426Ssam case PCIB_IVAR_BUS: 253164426Ssam sc->sc_bus = value; 254164426Ssam return (0); 255164426Ssam } 256164426Ssam 257164426Ssam return (ENOENT); 258164426Ssam} 259164426Ssam 260164426Ssamstatic int 261164426Ssamixppcib_setup_intr(device_t dev, device_t child, struct resource *ires, 262236987Simp int flags, driver_filter_t *filt, driver_intr_t *intr, void *arg, 263167263Spiso void **cookiep) 264164426Ssam{ 265164426Ssam 266164426Ssam return (BUS_SETUP_INTR(device_get_parent(dev), child, ires, flags, 267166901Spiso filt, intr, arg, cookiep)); 268164426Ssam} 269164426Ssam 270164426Ssamstatic int 271164426Ssamixppcib_teardown_intr(device_t dev, device_t child, struct resource *vec, 272164426Ssam void *cookie) 273164426Ssam{ 274164426Ssam 275164426Ssam return (BUS_TEARDOWN_INTR(device_get_parent(dev), child, vec, cookie)); 276164426Ssam} 277164426Ssam 278164426Ssamstatic struct resource * 279164426Ssamixppcib_alloc_resource(device_t bus, device_t child, int type, int *rid, 280164426Ssam u_long start, u_long end, u_long count, u_int flags) 281164426Ssam{ 282164426Ssam struct ixppcib_softc *sc = device_get_softc(bus); 283164426Ssam struct rman *rmanp; 284164426Ssam struct resource *rv; 285164426Ssam 286164426Ssam rv = NULL; 287164426Ssam switch (type) { 288164426Ssam case SYS_RES_IRQ: 289164426Ssam rmanp = &sc->sc_irq_rman; 290164426Ssam break; 291164426Ssam 292164426Ssam case SYS_RES_IOPORT: 293164426Ssam rmanp = &sc->sc_io_rman; 294164426Ssam break; 295164426Ssam 296164426Ssam case SYS_RES_MEMORY: 297164426Ssam rmanp = &sc->sc_mem_rman; 298164426Ssam break; 299164426Ssam 300164426Ssam default: 301164426Ssam return (rv); 302164426Ssam } 303164426Ssam 304189630Ssam rv = rman_reserve_resource(rmanp, start, end, count, flags & ~RF_ACTIVE, 305189630Ssam child); 306189630Ssam if (rv == NULL) 307189630Ssam return (NULL); 308189630Ssam rman_set_rid(rv, *rid); 309189630Ssam if (flags & RF_ACTIVE) { 310189630Ssam if (bus_activate_resource(child, type, *rid, rv)) { 311189630Ssam rman_release_resource(rv); 312189630Ssam return (NULL); 313164426Ssam } 314164426Ssam } 315164426Ssam 316164426Ssam return (rv); 317164426Ssam} 318164426Ssam 319164426Ssamstatic int 320164426Ssamixppcib_activate_resource(device_t bus, device_t child, int type, int rid, 321236987Simp struct resource *r) 322164426Ssam{ 323164426Ssam 324189630Ssam struct ixppcib_softc *sc = device_get_softc(bus); 325236987Simp 326189630Ssam switch (type) { 327189630Ssam case SYS_RES_IOPORT: 328189630Ssam rman_set_bustag(r, &sc->sc_pci_iot); 329189630Ssam rman_set_bushandle(r, rman_get_start(r)); 330189630Ssam break; 331189630Ssam case SYS_RES_MEMORY: 332189630Ssam rman_set_bustag(r, &sc->sc_pci_memt); 333189630Ssam rman_set_bushandle(r, rman_get_bushandle(sc->sc_mem) + 334189630Ssam (rman_get_start(r) - IXP425_PCI_MEM_HWBASE)); 335189630Ssam break; 336189630Ssam } 337189630Ssam 338189630Ssam return (rman_activate_resource(r)); 339164426Ssam} 340164426Ssam 341164426Ssamstatic int 342164426Ssamixppcib_deactivate_resource(device_t bus, device_t child, int type, int rid, 343236987Simp struct resource *r) 344164426Ssam{ 345164426Ssam 346189548Ssam device_printf(bus, "%s called deactivate_resource (unexpected)\n", 347189548Ssam device_get_nameunit(child)); 348164426Ssam return (ENXIO); 349164426Ssam} 350164426Ssam 351164426Ssamstatic int 352164426Ssamixppcib_release_resource(device_t bus, device_t child, int type, int rid, 353164426Ssam struct resource *r) 354164426Ssam{ 355164426Ssam 356189548Ssam device_printf(bus, "%s called release_resource (unexpected)\n", 357189548Ssam device_get_nameunit(child)); 358164426Ssam return (ENXIO); 359164426Ssam} 360164426Ssam 361164426Ssamstatic void 362164426Ssamixppcib_conf_setup(struct ixppcib_softc *sc, int bus, int slot, int func, 363164426Ssam int reg) 364164426Ssam{ 365164426Ssam if (bus == 0) { 366189456Ssam /* configuration type 0 */ 367189456Ssam PCI_CSR_WRITE_4(sc, PCI_NP_AD, 368189456Ssam (1U << (32 - (slot & 0x1f))) | 369189456Ssam ((func & 0x7) << 8) | (reg & ~3)); 370164426Ssam } else { 371189456Ssam /* configuration type 1 */ 372164426Ssam PCI_CSR_WRITE_4(sc, PCI_NP_AD, 373189456Ssam (bus << 16) | (slot << 11) | 374189456Ssam (func << 8) | (reg & ~3) | 1); 375164426Ssam } 376164426Ssam 377164426Ssam} 378164426Ssam 379164426Ssamstatic int 380164426Ssamixppcib_maxslots(device_t dev) 381164426Ssam{ 382164426Ssam 383164426Ssam return (PCI_SLOTMAX); 384164426Ssam} 385164426Ssam 386164426Ssamstatic u_int32_t 387164426Ssamixppcib_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, 388164426Ssam int bytes) 389164426Ssam{ 390164426Ssam struct ixppcib_softc *sc = device_get_softc(dev); 391164426Ssam u_int32_t data, ret; 392164426Ssam 393164426Ssam ixppcib_conf_setup(sc, bus, slot, func, reg & ~3); 394164426Ssam 395164426Ssam PCI_CSR_WRITE_4(sc, PCI_NP_CBE, COMMAND_NP_CONF_READ); 396164426Ssam ret = PCI_CSR_READ_4(sc, PCI_NP_RDATA); 397164426Ssam ret >>= (reg & 3) * 8; 398164426Ssam ret &= 0xffffffff >> ((4 - bytes) * 8); 399164426Ssam#if 0 400189456Ssam device_printf(dev, "%s: %u:%u:%u %#x(%d) = %#x\n", 401189456Ssam __func__, bus, slot, func, reg, bytes, ret); 402164426Ssam#endif 403164426Ssam /* check & clear PCI abort */ 404164426Ssam data = PCI_CSR_READ_4(sc, PCI_ISR); 405164426Ssam if (data & ISR_PFE) { 406164426Ssam PCI_CSR_WRITE_4(sc, PCI_ISR, ISR_PFE); 407164426Ssam return (-1); 408164426Ssam } 409164426Ssam return (ret); 410164426Ssam} 411164426Ssam 412164426Ssamstatic const int byteenables[] = { 0, 0x10, 0x30, 0x70, 0xf0 }; 413164426Ssam 414164426Ssamstatic void 415164426Ssamixppcib_write_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, 416164426Ssam u_int32_t val, int bytes) 417164426Ssam{ 418164426Ssam struct ixppcib_softc *sc = device_get_softc(dev); 419164426Ssam u_int32_t data; 420164426Ssam 421164426Ssam#if 0 422189456Ssam device_printf(dev, "%s: %u:%u:%u %#x(%d) = %#x\n", 423189456Ssam __func__, bus, slot, func, reg, bytes, val); 424164426Ssam#endif 425164426Ssam ixppcib_conf_setup(sc, bus, slot, func, reg & ~3); 426164426Ssam 427164426Ssam /* Byte enables are active low, so not them first */ 428164426Ssam PCI_CSR_WRITE_4(sc, PCI_NP_CBE, COMMAND_NP_CONF_WRITE | 429164426Ssam (~(byteenables[bytes] << (reg & 3)) & 0xf0)); 430164426Ssam PCI_CSR_WRITE_4(sc, PCI_NP_WDATA, val << ((reg & 3) * 8)); 431164426Ssam 432164426Ssam /* check & clear PCI abort */ 433164426Ssam data = PCI_CSR_READ_4(sc, PCI_ISR); 434164426Ssam if (data & ISR_PFE) 435164426Ssam PCI_CSR_WRITE_4(sc, PCI_ISR, ISR_PFE); 436164426Ssam} 437164426Ssam 438164426Ssamstatic int 439164426Ssamixppcib_route_interrupt(device_t bridge, device_t device, int pin) 440164426Ssam{ 441164426Ssam 442164426Ssam return (ixp425_md_route_interrupt(bridge, device, pin)); 443164426Ssam} 444164426Ssam 445164426Ssamstatic device_method_t ixppcib_methods[] = { 446164426Ssam /* Device interface */ 447164426Ssam DEVMETHOD(device_probe, ixppcib_probe), 448164426Ssam DEVMETHOD(device_attach, ixppcib_attach), 449164426Ssam 450164426Ssam /* Bus interface */ 451164426Ssam DEVMETHOD(bus_read_ivar, ixppcib_read_ivar), 452164426Ssam DEVMETHOD(bus_write_ivar, ixppcib_write_ivar), 453164426Ssam DEVMETHOD(bus_setup_intr, ixppcib_setup_intr), 454164426Ssam DEVMETHOD(bus_teardown_intr, ixppcib_teardown_intr), 455164426Ssam DEVMETHOD(bus_alloc_resource, ixppcib_alloc_resource), 456164426Ssam DEVMETHOD(bus_activate_resource, ixppcib_activate_resource), 457164426Ssam DEVMETHOD(bus_deactivate_resource, ixppcib_deactivate_resource), 458164426Ssam DEVMETHOD(bus_release_resource, ixppcib_release_resource), 459164426Ssam /* DEVMETHOD(bus_get_dma_tag, ixppcib_get_dma_tag), */ 460164426Ssam 461164426Ssam /* pcib interface */ 462164426Ssam DEVMETHOD(pcib_maxslots, ixppcib_maxslots), 463164426Ssam DEVMETHOD(pcib_read_config, ixppcib_read_config), 464164426Ssam DEVMETHOD(pcib_write_config, ixppcib_write_config), 465164426Ssam DEVMETHOD(pcib_route_interrupt, ixppcib_route_interrupt), 466164426Ssam 467227843Smarius DEVMETHOD_END 468164426Ssam}; 469164426Ssam 470164426Ssamstatic driver_t ixppcib_driver = { 471164426Ssam "pcib", 472164426Ssam ixppcib_methods, 473164426Ssam sizeof(struct ixppcib_softc), 474164426Ssam}; 475164426Ssamstatic devclass_t ixppcib_devclass; 476164426Ssam 477164426SsamDRIVER_MODULE(ixppcib, ixp, ixppcib_driver, ixppcib_devclass, 0, 0); 478