1239281Sgonzo/*- 2239281Sgonzo * Copyright (c) 2011 3239281Sgonzo * Ben Gray <ben.r.gray@gmail.com>. 4239281Sgonzo * All rights reserved. 5239281Sgonzo * 6239281Sgonzo * Redistribution and use in source and binary forms, with or without 7239281Sgonzo * modification, are permitted provided that the following conditions 8239281Sgonzo * are met: 9239281Sgonzo * 1. Redistributions of source code must retain the above copyright 10239281Sgonzo * notice, this list of conditions and the following disclaimer. 11239281Sgonzo * 2. Redistributions in binary form must reproduce the above copyright 12239281Sgonzo * notice, this list of conditions and the following disclaimer in the 13239281Sgonzo * documentation and/or other materials provided with the distribution. 14239281Sgonzo * 15239281Sgonzo * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16239281Sgonzo * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17239281Sgonzo * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18239281Sgonzo * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 19239281Sgonzo * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20239281Sgonzo * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21239281Sgonzo * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22239281Sgonzo * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23239281Sgonzo * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24239281Sgonzo * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25239281Sgonzo * SUCH DAMAGE. 26239281Sgonzo * 27239281Sgonzo * $FreeBSD$ 28239281Sgonzo */ 29239281Sgonzo#ifndef __TI_SDMAREG_H__ 30239281Sgonzo#define __TI_SDMAREG_H__ 31239281Sgonzo 32239281Sgonzo/** 33239281Sgonzo * The number of DMA channels possible on the controller. 34239281Sgonzo */ 35239281Sgonzo#define NUM_DMA_CHANNELS 32 36239281Sgonzo#define NUM_DMA_IRQS 4 37239281Sgonzo 38239281Sgonzo/** 39239281Sgonzo * Register offsets 40239281Sgonzo */ 41239281Sgonzo#define DMA4_REVISION 0x0000 42239281Sgonzo#define DMA4_IRQSTATUS_L(j) (0x0008 + ((j) * 0x4)) 43239281Sgonzo#define DMA4_IRQENABLE_L(j) (0x0018 + ((j) * 0x4)) 44239281Sgonzo#define DMA4_SYSSTATUS 0x0028 45239281Sgonzo#define DMA4_OCP_SYSCONFIG 0x002C 46239281Sgonzo#define DMA4_CAPS_0 0x0064 47239281Sgonzo#define DMA4_CAPS_2 0x006C 48239281Sgonzo#define DMA4_CAPS_3 0x0070 49239281Sgonzo#define DMA4_CAPS_4 0x0074 50239281Sgonzo#define DMA4_GCR 0x0078 51239281Sgonzo#define DMA4_CCR(i) (0x0080 + ((i) * 0x60)) 52239281Sgonzo#define DMA4_CLNK_CTRL(i) (0x0084 + ((i) * 0x60)) 53239281Sgonzo#define DMA4_CICR(i) (0x0088 + ((i) * 0x60)) 54239281Sgonzo#define DMA4_CSR(i) (0x008C + ((i) * 0x60)) 55239281Sgonzo#define DMA4_CSDP(i) (0x0090 + ((i) * 0x60)) 56239281Sgonzo#define DMA4_CEN(i) (0x0094 + ((i) * 0x60)) 57239281Sgonzo#define DMA4_CFN(i) (0x0098 + ((i) * 0x60)) 58239281Sgonzo#define DMA4_CSSA(i) (0x009C + ((i) * 0x60)) 59239281Sgonzo#define DMA4_CDSA(i) (0x00A0 + ((i) * 0x60)) 60239281Sgonzo#define DMA4_CSE(i) (0x00A4 + ((i) * 0x60)) 61239281Sgonzo#define DMA4_CSF(i) (0x00A8 + ((i) * 0x60)) 62239281Sgonzo#define DMA4_CDE(i) (0x00AC + ((i) * 0x60)) 63239281Sgonzo#define DMA4_CDF(i) (0x00B0 + ((i) * 0x60)) 64239281Sgonzo#define DMA4_CSAC(i) (0x00B4 + ((i) * 0x60)) 65239281Sgonzo#define DMA4_CDAC(i) (0x00B8 + ((i) * 0x60)) 66239281Sgonzo#define DMA4_CCEN(i) (0x00BC + ((i) * 0x60)) 67239281Sgonzo#define DMA4_CCFN(i) (0x00C0 + ((i) * 0x60)) 68239281Sgonzo#define DMA4_COLOR(i) (0x00C4 + ((i) * 0x60)) 69239281Sgonzo 70239281Sgonzo/* The following register are only defined on OMAP44xx (and newer?) */ 71239281Sgonzo#define DMA4_CDP(i) (0x00D0 + ((i) * 0x60)) 72239281Sgonzo#define DMA4_CNDP(i) (0x00D4 + ((i) * 0x60)) 73239281Sgonzo#define DMA4_CCDN(i) (0x00D8 + ((i) * 0x60)) 74239281Sgonzo 75239281Sgonzo/** 76239281Sgonzo * Various register field settings 77239281Sgonzo */ 78239281Sgonzo#define DMA4_CSDP_DATA_TYPE(x) (((x) & 0x3) << 0) 79239281Sgonzo#define DMA4_CSDP_SRC_BURST_MODE(x) (((x) & 0x3) << 7) 80239281Sgonzo#define DMA4_CSDP_DST_BURST_MODE(x) (((x) & 0x3) << 14) 81239281Sgonzo#define DMA4_CSDP_SRC_ENDIANISM(x) (((x) & 0x1) << 21) 82239281Sgonzo#define DMA4_CSDP_DST_ENDIANISM(x) (((x) & 0x1) << 19) 83239281Sgonzo#define DMA4_CSDP_WRITE_MODE(x) (((x) & 0x3) << 16) 84239281Sgonzo#define DMA4_CSDP_SRC_PACKED(x) (((x) & 0x1) << 6) 85239281Sgonzo#define DMA4_CSDP_DST_PACKED(x) (((x) & 0x1) << 13) 86239281Sgonzo 87239281Sgonzo#define DMA4_CCR_DST_ADDRESS_MODE(x) (((x) & 0x3) << 14) 88239281Sgonzo#define DMA4_CCR_SRC_ADDRESS_MODE(x) (((x) & 0x3) << 12) 89239281Sgonzo#define DMA4_CCR_READ_PRIORITY(x) (((x) & 0x1) << 6) 90239281Sgonzo#define DMA4_CCR_WRITE_PRIORITY(x) (((x) & 0x1) << 26) 91239281Sgonzo#define DMA4_CCR_SYNC_TRIGGER(x) ((((x) & 0x60) << 14) \ 92239281Sgonzo | ((x) & 0x1f)) 93239281Sgonzo#define DMA4_CCR_FRAME_SYNC(x) (((x) & 0x1) << 5) 94239281Sgonzo#define DMA4_CCR_BLOCK_SYNC(x) (((x) & 0x1) << 18) 95239281Sgonzo#define DMA4_CCR_SEL_SRC_DST_SYNC(x) (((x) & 0x1) << 24) 96239281Sgonzo 97239281Sgonzo#define DMA4_CCR_PACKET_TRANS (DMA4_CCR_FRAME_SYNC(1) | \ 98239281Sgonzo DMA4_CCR_BLOCK_SYNC(1) ) 99239281Sgonzo 100239281Sgonzo#define DMA4_CSR_DROP (1UL << 1) 101239281Sgonzo#define DMA4_CSR_HALF (1UL << 2) 102239281Sgonzo#define DMA4_CSR_FRAME (1UL << 3) 103239281Sgonzo#define DMA4_CSR_LAST (1UL << 4) 104239281Sgonzo#define DMA4_CSR_BLOCK (1UL << 5) 105239281Sgonzo#define DMA4_CSR_SYNC (1UL << 6) 106239281Sgonzo#define DMA4_CSR_PKT (1UL << 7) 107239281Sgonzo#define DMA4_CSR_TRANS_ERR (1UL << 8) 108239281Sgonzo#define DMA4_CSR_SECURE_ERR (1UL << 9) 109239281Sgonzo#define DMA4_CSR_SUPERVISOR_ERR (1UL << 10) 110239281Sgonzo#define DMA4_CSR_MISALIGNED_ADRS_ERR (1UL << 11) 111239281Sgonzo#define DMA4_CSR_DRAIN_END (1UL << 12) 112239281Sgonzo#define DMA4_CSR_CLEAR_MASK (0xffe) 113239281Sgonzo 114239281Sgonzo#define DMA4_CICR_DROP_IE (1UL << 1) 115239281Sgonzo#define DMA4_CICR_HALF_IE (1UL << 2) 116239281Sgonzo#define DMA4_CICR_FRAME_IE (1UL << 3) 117239281Sgonzo#define DMA4_CICR_LAST_IE (1UL << 4) 118239281Sgonzo#define DMA4_CICR_BLOCK_IE (1UL << 5) 119239281Sgonzo#define DMA4_CICR_PKT_IE (1UL << 7) 120239281Sgonzo#define DMA4_CICR_TRANS_ERR_IE (1UL << 8) 121239281Sgonzo#define DMA4_CICR_SECURE_ERR_IE (1UL << 9) 122239281Sgonzo#define DMA4_CICR_SUPERVISOR_ERR_IE (1UL << 10) 123239281Sgonzo#define DMA4_CICR_MISALIGNED_ADRS_ERR_IE (1UL << 11) 124239281Sgonzo#define DMA4_CICR_DRAIN_IE (1UL << 12) 125239281Sgonzo 126239281Sgonzo/** 127239281Sgonzo * The following H/W revision values were found be experimentation, TI don't 128239281Sgonzo * publish the revision numbers. The TRM says "TI internal Data". 129239281Sgonzo */ 130239281Sgonzo#define DMA4_OMAP3_REV 0x00000040 131239281Sgonzo#define DMA4_OMAP4_REV 0x00010900 132239281Sgonzo 133239281Sgonzo#endif /* __TI_SDMAREG_H__ */ 134