1239281Sgonzo/*- 2239281Sgonzo * Copyright (c) 2011 3239281Sgonzo * Ben Gray <ben.r.gray@gmail.com>. 4239281Sgonzo * All rights reserved. 5239281Sgonzo * 6239281Sgonzo * Redistribution and use in source and binary forms, with or without 7239281Sgonzo * modification, are permitted provided that the following conditions 8239281Sgonzo * are met: 9239281Sgonzo * 1. Redistributions of source code must retain the above copyright 10239281Sgonzo * notice, this list of conditions and the following disclaimer. 11239281Sgonzo * 2. Redistributions in binary form must reproduce the above copyright 12239281Sgonzo * notice, this list of conditions and the following disclaimer in the 13239281Sgonzo * documentation and/or other materials provided with the distribution. 14239281Sgonzo * 15239281Sgonzo * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16239281Sgonzo * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17239281Sgonzo * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18239281Sgonzo * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 19239281Sgonzo * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20239281Sgonzo * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21239281Sgonzo * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22239281Sgonzo * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23239281Sgonzo * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24239281Sgonzo * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25239281Sgonzo * SUCH DAMAGE. 26239281Sgonzo * 27239281Sgonzo * $FreeBSD$ 28239281Sgonzo */ 29239281Sgonzo 30239281Sgonzo/** 31239281Sgonzo * sDMA device driver interface for the TI SoC 32239281Sgonzo * 33239281Sgonzo * See the ti_sdma.c file for implementation details. 34239281Sgonzo * 35239281Sgonzo * Reference: 36239281Sgonzo * OMAP35x Applications Processor 37239281Sgonzo * Technical Reference Manual 38239281Sgonzo * (omap35xx_techref.pdf) 39239281Sgonzo */ 40239281Sgonzo#ifndef _TI_DMA_H_ 41239281Sgonzo#define _TI_DMA_H_ 42239281Sgonzo 43239281Sgonzo#define TI_SDMA_ENDIAN_BIG 0x1 44239281Sgonzo#define TI_SDMA_ENDIAN_LITTLE 0x0 45239281Sgonzo 46239281Sgonzo#define TI_SDMA_BURST_NONE 0x0 47239281Sgonzo#define TI_SDMA_BURST_16 0x1 48239281Sgonzo#define TI_SDMA_BURST_32 0x2 49239281Sgonzo#define TI_SDMA_BURST_64 0x3 50239281Sgonzo 51239281Sgonzo#define TI_SDMA_DATA_8BITS_SCALAR 0x0 52239281Sgonzo#define TI_SDMA_DATA_16BITS_SCALAR 0x1 53239281Sgonzo#define TI_SDMA_DATA_32BITS_SCALAR 0x2 54239281Sgonzo 55239281Sgonzo#define TI_SDMA_ADDR_CONSTANT 0x0 56239281Sgonzo#define TI_SDMA_ADDR_POST_INCREMENT 0x1 57239281Sgonzo#define TI_SDMA_ADDR_SINGLE_INDEX 0x2 58239281Sgonzo#define TI_SDMA_ADDR_DOUBLE_INDEX 0x3 59239281Sgonzo 60239281Sgonzo/** 61239281Sgonzo * Status flags for the DMA callback 62239281Sgonzo * 63239281Sgonzo */ 64239281Sgonzo#define TI_SDMA_STATUS_DROP (1UL << 1) 65239281Sgonzo#define TI_SDMA_STATUS_HALF (1UL << 2) 66239281Sgonzo#define TI_SDMA_STATUS_FRAME (1UL << 3) 67239281Sgonzo#define TI_SDMA_STATUS_LAST (1UL << 4) 68239281Sgonzo#define TI_SDMA_STATUS_BLOCK (1UL << 5) 69239281Sgonzo#define TI_SDMA_STATUS_SYNC (1UL << 6) 70239281Sgonzo#define TI_SDMA_STATUS_PKT (1UL << 7) 71239281Sgonzo#define TI_SDMA_STATUS_TRANS_ERR (1UL << 8) 72239281Sgonzo#define TI_SDMA_STATUS_SECURE_ERR (1UL << 9) 73239281Sgonzo#define TI_SDMA_STATUS_SUPERVISOR_ERR (1UL << 10) 74239281Sgonzo#define TI_SDMA_STATUS_MISALIGNED_ADRS_ERR (1UL << 11) 75239281Sgonzo#define TI_SDMA_STATUS_DRAIN_END (1UL << 12) 76239281Sgonzo 77239281Sgonzo#define TI_SDMA_SYNC_FRAME (1UL << 0) 78239281Sgonzo#define TI_SDMA_SYNC_BLOCK (1UL << 1) 79239281Sgonzo#define TI_SDMA_SYNC_PACKET (TI_SDMA_SYNC_FRAME | TI_SDMA_SYNC_BLOCK) 80239281Sgonzo#define TI_SDMA_SYNC_TRIG_ON_SRC (1UL << 8) 81239281Sgonzo#define TI_SDMA_SYNC_TRIG_ON_DST (1UL << 9) 82239281Sgonzo 83239281Sgonzo#define TI_SDMA_IRQ_FLAG_DROP (1UL << 1) 84239281Sgonzo#define TI_SDMA_IRQ_FLAG_HALF_FRAME_COMPL (1UL << 2) 85239281Sgonzo#define TI_SDMA_IRQ_FLAG_FRAME_COMPL (1UL << 3) 86239281Sgonzo#define TI_SDMA_IRQ_FLAG_START_LAST_FRAME (1UL << 4) 87239281Sgonzo#define TI_SDMA_IRQ_FLAG_BLOCK_COMPL (1UL << 5) 88239281Sgonzo#define TI_SDMA_IRQ_FLAG_ENDOF_PKT (1UL << 7) 89239281Sgonzo#define TI_SDMA_IRQ_FLAG_DRAIN (1UL << 12) 90239281Sgonzo 91239281Sgonzoint ti_sdma_activate_channel(unsigned int *ch, 92239281Sgonzo void (*callback)(unsigned int ch, uint32_t status, void *data), void *data); 93239281Sgonzoint ti_sdma_deactivate_channel(unsigned int ch); 94239281Sgonzoint ti_sdma_start_xfer(unsigned int ch, unsigned int src_paddr, 95239281Sgonzo unsigned long dst_paddr, unsigned int frmcnt, unsigned int elmcnt); 96239281Sgonzoint ti_sdma_start_xfer_packet(unsigned int ch, unsigned int src_paddr, 97239281Sgonzo unsigned long dst_paddr, unsigned int frmcnt, unsigned int elmcnt, 98239281Sgonzo unsigned int pktsize); 99239281Sgonzoint ti_sdma_stop_xfer(unsigned int ch); 100239281Sgonzoint ti_sdma_enable_channel_irq(unsigned int ch, uint32_t flags); 101239281Sgonzoint ti_sdma_disable_channel_irq(unsigned int ch); 102239281Sgonzoint ti_sdma_get_channel_status(unsigned int ch, uint32_t *status); 103239281Sgonzoint ti_sdma_set_xfer_endianess(unsigned int ch, unsigned int src, unsigned int dst); 104239281Sgonzoint ti_sdma_set_xfer_burst(unsigned int ch, unsigned int src, unsigned int dst); 105239281Sgonzoint ti_sdma_set_xfer_data_type(unsigned int ch, unsigned int type); 106239281Sgonzoint ti_sdma_set_callback(unsigned int ch, 107239281Sgonzo void (*callback)(unsigned int ch, uint32_t status, void *data), void *data); 108239281Sgonzoint ti_sdma_sync_params(unsigned int ch, unsigned int trigger, unsigned int mode); 109239281Sgonzoint ti_sdma_set_addr_mode(unsigned int ch, unsigned int src_mode, unsigned int dst_mode); 110239281Sgonzo 111239281Sgonzo#endif /* _TI_SDMA_H_ */ 112