1239281Sgonzo/*- 2239281Sgonzo * Copyright (c) 2011 3239281Sgonzo * Ben Gray <ben.r.gray@gmail.com>. 4239281Sgonzo * All rights reserved. 5239281Sgonzo * 6239281Sgonzo * Redistribution and use in source and binary forms, with or without 7239281Sgonzo * modification, are permitted provided that the following conditions 8239281Sgonzo * are met: 9239281Sgonzo * 1. Redistributions of source code must retain the above copyright 10239281Sgonzo * notice, this list of conditions and the following disclaimer. 11239281Sgonzo * 2. Redistributions in binary form must reproduce the above copyright 12239281Sgonzo * notice, this list of conditions and the following disclaimer in the 13239281Sgonzo * documentation and/or other materials provided with the distribution. 14239281Sgonzo * 15239281Sgonzo * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16239281Sgonzo * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17239281Sgonzo * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18239281Sgonzo * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 19239281Sgonzo * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20239281Sgonzo * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21239281Sgonzo * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22239281Sgonzo * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23239281Sgonzo * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24239281Sgonzo * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25239281Sgonzo * SUCH DAMAGE. 26239281Sgonzo * 27239281Sgonzo * $FreeBSD$ 28239281Sgonzo */ 29239281Sgonzo 30239281Sgonzo#ifndef _TI_I2C_H_ 31239281Sgonzo#define _TI_I2C_H_ 32239281Sgonzo 33239281Sgonzo/** 34239281Sgonzo * Header file for the OMAP I2C driver. 35239281Sgonzo * 36239281Sgonzo * Simply contains register bit flags. 37239281Sgonzo */ 38239281Sgonzo 39239281Sgonzo/* 40239281Sgonzo * OMAP4 I2C Registers, Summary 1 41239281Sgonzo */ 42239281Sgonzo#define I2C_REG_IE 0x84 43239281Sgonzo#define I2C_IE_XDR (1UL << 14) /* Transmit draining interrupt */ 44239281Sgonzo#define I2C_IE_RDR (1UL << 13) /* Receive draining interrupt */ 45239281Sgonzo#define I2C_IE_AAS (1UL << 9) /* Addressed as Slave interrupt */ 46239281Sgonzo#define I2C_IE_BF (1UL << 8) /* Bus Free interrupt */ 47239281Sgonzo#define I2C_IE_AERR (1UL << 7) /* Access Error interrupt */ 48239281Sgonzo#define I2C_IE_STC (1UL << 6) /* Start Condition interrupt */ 49239281Sgonzo#define I2C_IE_GC (1UL << 5) /* General Call interrupt */ 50239281Sgonzo#define I2C_IE_XRDY (1UL << 4) /* Transmit Data Ready interrupt */ 51239281Sgonzo#define I2C_IE_RRDY (1UL << 3) /* Receive Data Ready interrupt */ 52239281Sgonzo#define I2C_IE_ARDY (1UL << 2) /* Register Access Ready interrupt */ 53239281Sgonzo#define I2C_IE_NACK (1UL << 1) /* No Acknowledgment interrupt */ 54239281Sgonzo#define I2C_IE_AL (1UL << 0) /* Arbitration Lost interrupt */ 55239281Sgonzo#define I2C_REG_STAT 0x88 56239281Sgonzo#define I2C_STAT_XDR (1UL << 14) 57239281Sgonzo#define I2C_STAT_RDR (1UL << 13) 58239281Sgonzo#define I2C_STAT_BB (1UL << 12) 59239281Sgonzo#define I2C_STAT_ROVR (1UL << 11) 60239281Sgonzo#define I2C_STAT_XUDF (1UL << 10) 61239281Sgonzo#define I2C_STAT_AAS (1UL << 9) 62239281Sgonzo#define I2C_STAT_BF (1UL << 8) 63239281Sgonzo#define I2C_STAT_AERR (1UL << 7) 64239281Sgonzo#define I2C_STAT_STC (1UL << 6) 65239281Sgonzo#define I2C_STAT_GC (1UL << 5) 66239281Sgonzo#define I2C_STAT_XRDY (1UL << 4) 67239281Sgonzo#define I2C_STAT_RRDY (1UL << 3) 68239281Sgonzo#define I2C_STAT_ARDY (1UL << 2) 69239281Sgonzo#define I2C_STAT_NACK (1UL << 1) 70239281Sgonzo#define I2C_STAT_AL (1UL << 0) 71239281Sgonzo#define I2C_REG_SYSS 0x90 72239281Sgonzo#define I2C_REG_BUF 0x94 73239281Sgonzo#define I2C_REG_CNT 0x98 74239281Sgonzo#define I2C_REG_DATA 0x9c 75239281Sgonzo#define I2C_REG_CON 0xa4 76239281Sgonzo#define I2C_CON_I2C_EN (1UL << 15) 77239281Sgonzo#define I2C_CON_OPMODE_STD (0UL << 12) 78239281Sgonzo#define I2C_CON_OPMODE_HS (1UL << 12) 79239281Sgonzo#define I2C_CON_OPMODE_SCCB (2UL << 12) 80239281Sgonzo#define I2C_CON_OPMODE_MASK (3UL << 13) 81239281Sgonzo#define I2C_CON_I2C_STB (1UL << 11) 82239281Sgonzo#define I2C_CON_MST (1UL << 10) 83239281Sgonzo#define I2C_CON_TRX (1UL << 9) 84239281Sgonzo#define I2C_CON_XSA (1UL << 8) 85239281Sgonzo#define I2C_CON_XOA0 (1UL << 7) 86239281Sgonzo#define I2C_CON_XOA1 (1UL << 6) 87239281Sgonzo#define I2C_CON_XOA2 (1UL << 5) 88239281Sgonzo#define I2C_CON_XOA3 (1UL << 4) 89239281Sgonzo#define I2C_CON_STP (1UL << 1) 90239281Sgonzo#define I2C_CON_STT (1UL << 0) 91239281Sgonzo#define I2C_REG_OA0 0xa8 92239281Sgonzo#define I2C_REG_SA 0xac 93239281Sgonzo#define I2C_REG_PSC 0xb0 94239281Sgonzo#define I2C_REG_SCLL 0xb4 95239281Sgonzo#define I2C_REG_SCLH 0xb8 96239281Sgonzo#define I2C_REG_SYSTEST 0xbc 97239281Sgonzo#define I2C_REG_BUFSTAT 0xc0 98239281Sgonzo#define I2C_REG_OA1 0xc4 99239281Sgonzo#define I2C_REG_OA2 0xc8 100239281Sgonzo#define I2C_REG_OA3 0xcc 101239281Sgonzo#define I2C_REG_ACTOA 0xd0 102239281Sgonzo#define I2C_REG_SBLOCK 0xd4 103239281Sgonzo 104239281Sgonzo/* 105239281Sgonzo * OMAP4 I2C Registers, Summary 2 106239281Sgonzo */ 107239281Sgonzo#define I2C_REG_REVNB_LO 0x00 108239281Sgonzo#define I2C_REG_REVNB_HI 0x04 109239281Sgonzo#define I2C_REG_SYSC 0x10 110239281Sgonzo#define I2C_REG_IRQENABLE_SET 0x2C 111239281Sgonzo#define I2C_REG_IRQENABLE_CLR 0x30 112239281Sgonzo 113239281Sgonzo 114239281Sgonzo 115239281Sgonzo#endif /* _TI_I2C_H_ */ 116