if_cpswreg.h revision 246276
1234353Sdim/*- 2203954Srdivacky * Copyright (c) 2012 Damjan Marion <dmarion@Freebsd.org> 3203954Srdivacky * All rights reserved. 4203954Srdivacky * 5203954Srdivacky * Redistribution and use in source and binary forms, with or without 6203954Srdivacky * modification, are permitted provided that the following conditions 7234353Sdim * are met: 8203954Srdivacky * 1. Redistributions of source code must retain the above copyright 9203954Srdivacky * notice, this list of conditions and the following disclaimer. 10203954Srdivacky * 2. Redistributions in binary form must reproduce the above copyright 11203954Srdivacky * notice, this list of conditions and the following disclaimer in the 12203954Srdivacky * documentation and/or other materials provided with the distribution. 13203954Srdivacky * 14203954Srdivacky * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15203954Srdivacky * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16203954Srdivacky * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17203954Srdivacky * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18218893Sdim * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19218893Sdim * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20203954Srdivacky * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21203954Srdivacky * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22210299Sed * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23210299Sed * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24210299Sed * SUCH DAMAGE. 25210299Sed * 26210299Sed * $FreeBSD: head/sys/arm/ti/cpsw/if_cpswreg.h 246276 2013-02-03 01:08:01Z kientzle $ 27210299Sed */ 28210299Sed 29210299Sed#ifndef _IF_CPSWREG_H 30210299Sed#define _IF_CPSWREG_H 31210299Sed 32210299Sed#define CPSW_SS_OFFSET 0x0000 33210299Sed#define CPSW_SS_IDVER (CPSW_SS_OFFSET + 0x00) 34210299Sed#define CPSW_SS_SOFT_RESET (CPSW_SS_OFFSET + 0x08) 35210299Sed#define CPSW_SS_STAT_PORT_EN (CPSW_SS_OFFSET + 0x0C) 36210299Sed#define CPSW_SS_PTYPE (CPSW_SS_OFFSET + 0x10) 37210299Sed#define CPSW_SS_FLOW_CONTROL (CPSW_SS_OFFSET + 0x24) 38210299Sed 39210299Sed#define CPSW_PORT_OFFSET 0x0100 40210299Sed#define CPSW_PORT_P_MAX_BLKS(p) (CPSW_PORT_OFFSET + 0x08 + ((p) * 0x100)) 41223017Sdim#define CPSW_PORT_P_BLK_CNT(p) (CPSW_PORT_OFFSET + 0x0C + ((p) * 0x100)) 42226633Sdim#define CPSW_PORT_P_TX_PRI_MAP(p) (CPSW_PORT_OFFSET + 0x118 + ((p-1) * 0x100)) 43226633Sdim#define CPSW_PORT_P0_CPDMA_TX_PRI_MAP (CPSW_PORT_OFFSET + 0x01C) 44234353Sdim#define CPSW_PORT_P0_CPDMA_RX_CH_MAP (CPSW_PORT_OFFSET + 0x020) 45234353Sdim#define CPSW_PORT_P_SA_LO(p) (CPSW_PORT_OFFSET + 0x120 + ((p-1) * 0x100)) 46210299Sed#define CPSW_PORT_P_SA_HI(p) (CPSW_PORT_OFFSET + 0x124 + ((p-1) * 0x100)) 47210299Sed 48223017Sdim#define CPSW_CPDMA_OFFSET 0x0800 49223017Sdim#define CPSW_CPDMA_TX_CONTROL (CPSW_CPDMA_OFFSET + 0x04) 50210299Sed#define CPSW_CPDMA_TX_TEARDOWN (CPSW_CPDMA_OFFSET + 0x08) 51234353Sdim#define CPSW_CPDMA_RX_CONTROL (CPSW_CPDMA_OFFSET + 0x14) 52210299Sed#define CPSW_CPDMA_RX_TEARDOWN (CPSW_CPDMA_OFFSET + 0x18) 53224145Sdim#define CPSW_CPDMA_SOFT_RESET (CPSW_CPDMA_OFFSET + 0x1c) 54224145Sdim#define CPSW_CPDMA_DMACONTROL (CPSW_CPDMA_OFFSET + 0x20) 55218893Sdim#define CPSW_CPDMA_DMASTATUS (CPSW_CPDMA_OFFSET + 0x24) 56234353Sdim#define CPSW_CPDMA_RX_BUFFER_OFFSET (CPSW_CPDMA_OFFSET + 0x28) 57234353Sdim#define CPSW_CPDMA_TX_INTSTAT_RAW (CPSW_CPDMA_OFFSET + 0x80) 58218893Sdim#define CPSW_CPDMA_TX_INTSTAT_MASKED (CPSW_CPDMA_OFFSET + 0x84) 59210299Sed#define CPSW_CPDMA_TX_INTMASK_SET (CPSW_CPDMA_OFFSET + 0x88) 60210299Sed#define CPSW_CPDMA_TX_INTMASK_CLEAR (CPSW_CPDMA_OFFSET + 0x8C) 61210299Sed#define CPSW_CPDMA_CPDMA_EOI_VECTOR (CPSW_CPDMA_OFFSET + 0x94) 62210299Sed#define CPSW_CPDMA_RX_INTSTAT_RAW (CPSW_CPDMA_OFFSET + 0xA0) 63210299Sed#define CPSW_CPDMA_RX_INTSTAT_MASKED (CPSW_CPDMA_OFFSET + 0xA4) 64210299Sed#define CPSW_CPDMA_RX_INTMASK_SET (CPSW_CPDMA_OFFSET + 0xA8) 65210299Sed#define CPSW_CPDMA_RX_INTMASK_CLEAR (CPSW_CPDMA_OFFSET + 0xAc) 66210299Sed#define CPSW_CPDMA_DMA_INTSTAT_RAW (CPSW_CPDMA_OFFSET + 0xB0) 67210299Sed#define CPSW_CPDMA_DMA_INTSTAT_MASKED (CPSW_CPDMA_OFFSET + 0xB4) 68210299Sed#define CPSW_CPDMA_DMA_INTMASK_SET (CPSW_CPDMA_OFFSET + 0xB8) 69210299Sed#define CPSW_CPDMA_DMA_INTMASK_CLEAR (CPSW_CPDMA_OFFSET + 0xBC) 70210299Sed#define CPSW_CPDMA_RX_FREEBUFFER(p) (CPSW_CPDMA_OFFSET + 0x0e0 + ((p) * 0x04)) 71210299Sed 72210299Sed#define CPSW_STATS_OFFSET 0x0900 73210299Sed 74239462Sdim#define CPSW_STATERAM_OFFSET 0x0A00 75239462Sdim#define CPSW_CPDMA_TX_HDP(p) (CPSW_STATERAM_OFFSET + 0x00 + ((p) * 0x04)) 76239462Sdim#define CPSW_CPDMA_RX_HDP(p) (CPSW_STATERAM_OFFSET + 0x20 + ((p) * 0x04)) 77239462Sdim#define CPSW_CPDMA_TX_CP(p) (CPSW_STATERAM_OFFSET + 0x40 + ((p) * 0x04)) 78239462Sdim#define CPSW_CPDMA_RX_CP(p) (CPSW_STATERAM_OFFSET + 0x60 + ((p) * 0x04)) 79234353Sdim 80234353Sdim#define CPSW_CPTS_OFFSET 0x0C00 81239462Sdim 82210299Sed#define CPSW_ALE_OFFSET 0x0D00 83218893Sdim#define CPSW_ALE_CONTROL (CPSW_ALE_OFFSET + 0x08) 84239462Sdim#define CPSW_ALE_TBLCTL (CPSW_ALE_OFFSET + 0x20) 85239462Sdim#define CPSW_ALE_TBLW2 (CPSW_ALE_OFFSET + 0x34) 86239462Sdim#define CPSW_ALE_TBLW1 (CPSW_ALE_OFFSET + 0x38) 87239462Sdim#define CPSW_ALE_TBLW0 (CPSW_ALE_OFFSET + 0x3C) 88239462Sdim#define CPSW_ALE_PORTCTL(p) (CPSW_ALE_OFFSET + 0x40 + ((p) * 0x04)) 89234353Sdim 90234353Sdim/* SL1 is at 0x0D80, SL2 is at 0x0DC0 */ 91234353Sdim#define CPSW_SL_OFFSET 0x0D80 92234353Sdim#define CPSW_SL_MACCONTROL(p) (CPSW_SL_OFFSET + (0x40 * (p)) + 0x04) 93234353Sdim#define CPSW_SL_MACSTATUS(p) (CPSW_SL_OFFSET + (0x40 * (p)) + 0x08) 94210299Sed#define CPSW_SL_SOFT_RESET(p) (CPSW_SL_OFFSET + (0x40 * (p)) + 0x0C) 95234353Sdim#define CPSW_SL_RX_MAXLEN(p) (CPSW_SL_OFFSET + (0x40 * (p)) + 0x10) 96234353Sdim#define CPSW_SL_RX_PAUSE(p) (CPSW_SL_OFFSET + (0x40 * (p)) + 0x18) 97234353Sdim#define CPSW_SL_TX_PAUSE(p) (CPSW_SL_OFFSET + (0x40 * (p)) + 0x1C) 98234353Sdim#define CPSW_SL_RX_PRI_MAP(p) (CPSW_SL_OFFSET + (0x40 * (p)) + 0x24) 99234353Sdim 100234353Sdim#define MDIO_OFFSET 0x1000 101234353Sdim#define MDIOCONTROL (MDIO_OFFSET + 0x04) 102234353Sdim#define MDIOUSERACCESS0 (MDIO_OFFSET + 0x80) 103234353Sdim#define MDIOUSERPHYSEL0 (MDIO_OFFSET + 0x84) 104234353Sdim 105234353Sdim#define CPSW_WR_OFFSET 0x1200 106234353Sdim#define CPSW_WR_SOFT_RESET (CPSW_WR_OFFSET + 0x04) 107234353Sdim#define CPSW_WR_CONTROL (CPSW_WR_OFFSET + 0x08) 108234353Sdim#define CPSW_WR_INT_CONTROL (CPSW_WR_OFFSET + 0x0c) 109210299Sed#define CPSW_WR_C_RX_THRESH_EN(p) (CPSW_WR_OFFSET + (0x10 * (p)) + 0x10) 110212904Sdim#define CPSW_WR_C_RX_EN(p) (CPSW_WR_OFFSET + (0x10 * (p)) + 0x14) 111212904Sdim#define CPSW_WR_C_TX_EN(p) (CPSW_WR_OFFSET + (0x10 * (p)) + 0x18) 112210299Sed#define CPSW_WR_C_MISC_EN(p) (CPSW_WR_OFFSET + (0x10 * (p)) + 0x1C) 113212904Sdim#define CPSW_WR_C_RX_THRESH_STAT(p) (CPSW_WR_OFFSET + (0x10 * (p)) + 0x40) 114210299Sed#define CPSW_WR_C_RX_STAT(p) (CPSW_WR_OFFSET + (0x10 * (p)) + 0x44) 115234353Sdim#define CPSW_WR_C_TX_STAT(p) (CPSW_WR_OFFSET + (0x10 * (p)) + 0x48) 116234353Sdim#define CPSW_WR_C_MISC_STAT(p) (CPSW_WR_OFFSET + (0x10 * (p)) + 0x4C) 117234353Sdim 118234353Sdim#define CPSW_CPPI_RAM_OFFSET 0x2000 119212904Sdim#define CPSW_CPPI_RAM_SIZE 0x2000 120212904Sdim 121212904Sdim#define CPDMA_BD_SOP (1<<15) 122212904Sdim#define CPDMA_BD_EOP (1<<14) 123212904Sdim#define CPDMA_BD_OWNER (1<<13) 124212904Sdim#define CPDMA_BD_EOQ (1<<12) 125212904Sdim#define CPDMA_BD_TDOWNCMPLT (1<<11) 126212904Sdim#define CPDMA_BD_PKT_ERR_MASK (3<< 4) 127212904Sdim 128212904Sdimstruct cpsw_cpdma_bd { 129212904Sdim volatile uint32_t next; 130212904Sdim volatile uint32_t bufptr; 131226633Sdim volatile uint16_t buflen; 132234353Sdim volatile uint16_t bufoff; 133239462Sdim volatile uint16_t pktlen; 134226633Sdim volatile uint16_t flags; 135239462Sdim}; 136239462Sdim 137239462Sdim#endif /*_IF_CPSWREG_H */ 138212904Sdim