if_cpswreg.h revision 244939
1239281Sgonzo/*- 2239281Sgonzo * Copyright (c) 2012 Damjan Marion <dmarion@Freebsd.org> 3239281Sgonzo * All rights reserved. 4239281Sgonzo * 5239281Sgonzo * Redistribution and use in source and binary forms, with or without 6239281Sgonzo * modification, are permitted provided that the following conditions 7239281Sgonzo * are met: 8239281Sgonzo * 1. Redistributions of source code must retain the above copyright 9239281Sgonzo * notice, this list of conditions and the following disclaimer. 10239281Sgonzo * 2. Redistributions in binary form must reproduce the above copyright 11239281Sgonzo * notice, this list of conditions and the following disclaimer in the 12239281Sgonzo * documentation and/or other materials provided with the distribution. 13239281Sgonzo * 14239281Sgonzo * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15239281Sgonzo * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16239281Sgonzo * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17239281Sgonzo * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18239281Sgonzo * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19239281Sgonzo * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20239281Sgonzo * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21239281Sgonzo * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22239281Sgonzo * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23239281Sgonzo * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24239281Sgonzo * SUCH DAMAGE. 25239281Sgonzo * 26239281Sgonzo * $FreeBSD: head/sys/arm/ti/cpsw/if_cpswreg.h 244939 2013-01-01 18:55:04Z kientzle $ 27239281Sgonzo */ 28239281Sgonzo 29239281Sgonzo#ifndef _IF_CPSWREG_H 30239281Sgonzo#define _IF_CPSWREG_H 31239281Sgonzo 32239281Sgonzo#define CPSW_SS_OFFSET 0x0000 33239281Sgonzo#define CPSW_SS_IDVER (CPSW_SS_OFFSET + 0x00) 34239281Sgonzo#define CPSW_SS_SOFT_RESET (CPSW_SS_OFFSET + 0x08) 35239281Sgonzo#define CPSW_SS_STAT_PORT_EN (CPSW_SS_OFFSET + 0x0C) 36239281Sgonzo#define CPSW_SS_PTYPE (CPSW_SS_OFFSET + 0x10) 37239281Sgonzo 38239281Sgonzo#define CPSW_PORT_OFFSET 0x0100 39239281Sgonzo#define CPSW_PORT_P_TX_PRI_MAP(p) (CPSW_PORT_OFFSET + 0x118 + ((p-1) * 0x100)) 40239281Sgonzo#define CPSW_PORT_P0_CPDMA_TX_PRI_MAP (CPSW_PORT_OFFSET + 0x01C) 41239281Sgonzo#define CPSW_PORT_P0_CPDMA_RX_CH_MAP (CPSW_PORT_OFFSET + 0x020) 42239281Sgonzo#define CPSW_PORT_P_SA_LO(p) (CPSW_PORT_OFFSET + 0x120 + ((p-1) * 0x100)) 43239281Sgonzo#define CPSW_PORT_P_SA_HI(p) (CPSW_PORT_OFFSET + 0x124 + ((p-1) * 0x100)) 44239281Sgonzo 45239281Sgonzo#define CPSW_CPDMA_OFFSET 0x0800 46239281Sgonzo#define CPSW_CPDMA_TX_CONTROL (CPSW_CPDMA_OFFSET + 0x04) 47244939Skientzle#define CPSW_CPDMA_TX_TEARDOWN (CPSW_CPDMA_OFFSET + 0x08) 48239281Sgonzo#define CPSW_CPDMA_RX_CONTROL (CPSW_CPDMA_OFFSET + 0x14) 49244939Skientzle#define CPSW_CPDMA_RX_TEARDOWN (CPSW_CPDMA_OFFSET + 0x18) 50239281Sgonzo#define CPSW_CPDMA_SOFT_RESET (CPSW_CPDMA_OFFSET + 0x1c) 51239281Sgonzo#define CPSW_CPDMA_DMACONTROL (CPSW_CPDMA_OFFSET + 0x20) 52239281Sgonzo#define CPSW_CPDMA_DMASTATUS (CPSW_CPDMA_OFFSET + 0x24) 53239281Sgonzo#define CPSW_CPDMA_RX_BUFFER_OFFSET (CPSW_CPDMA_OFFSET + 0x28) 54239281Sgonzo#define CPSW_CPDMA_TX_INTSTAT_RAW (CPSW_CPDMA_OFFSET + 0x80) 55239281Sgonzo#define CPSW_CPDMA_TX_INTSTAT_MASKED (CPSW_CPDMA_OFFSET + 0x84) 56239281Sgonzo#define CPSW_CPDMA_TX_INTMASK_SET (CPSW_CPDMA_OFFSET + 0x88) 57239281Sgonzo#define CPSW_CPDMA_TX_INTMASK_CLEAR (CPSW_CPDMA_OFFSET + 0x8C) 58239281Sgonzo#define CPSW_CPDMA_CPDMA_EOI_VECTOR (CPSW_CPDMA_OFFSET + 0x94) 59239281Sgonzo#define CPSW_CPDMA_RX_INTSTAT_RAW (CPSW_CPDMA_OFFSET + 0xA0) 60239281Sgonzo#define CPSW_CPDMA_RX_INTSTAT_MASKED (CPSW_CPDMA_OFFSET + 0xA4) 61239281Sgonzo#define CPSW_CPDMA_RX_INTMASK_SET (CPSW_CPDMA_OFFSET + 0xA8) 62239281Sgonzo#define CPSW_CPDMA_RX_INTMASK_CLEAR (CPSW_CPDMA_OFFSET + 0xAc) 63239281Sgonzo#define CPSW_CPDMA_DMA_INTSTAT_RAW (CPSW_CPDMA_OFFSET + 0xB0) 64239281Sgonzo#define CPSW_CPDMA_DMA_INTSTAT_MASKED (CPSW_CPDMA_OFFSET + 0xB4) 65239281Sgonzo#define CPSW_CPDMA_DMA_INTMASK_SET (CPSW_CPDMA_OFFSET + 0xB8) 66239281Sgonzo#define CPSW_CPDMA_DMA_INTMASK_CLEAR (CPSW_CPDMA_OFFSET + 0xBC) 67239281Sgonzo#define CPSW_CPDMA_RX_FREEBUFFER(p) (CPSW_CPDMA_OFFSET + 0x0e0 + ((p) * 0x04)) 68239281Sgonzo 69244939Skientzle#define CPSW_STATS_OFFSET 0x0900 70244939Skientzle 71244939Skientzle#define CPSW_STATERAM_OFFSET 0x0A00 72244939Skientzle#define CPSW_CPDMA_TX_HDP(p) (CPSW_STATERAM_OFFSET + 0x00 + ((p) * 0x04)) 73244939Skientzle#define CPSW_CPDMA_RX_HDP(p) (CPSW_STATERAM_OFFSET + 0x20 + ((p) * 0x04)) 74244939Skientzle#define CPSW_CPDMA_TX_CP(p) (CPSW_STATERAM_OFFSET + 0x40 + ((p) * 0x04)) 75244939Skientzle#define CPSW_CPDMA_RX_CP(p) (CPSW_STATERAM_OFFSET + 0x60 + ((p) * 0x04)) 76244939Skientzle 77239281Sgonzo#define CPSW_CPTS_OFFSET 0x0C00 78239281Sgonzo 79239281Sgonzo#define CPSW_ALE_OFFSET 0x0D00 80239281Sgonzo#define CPSW_ALE_CONTROL (CPSW_ALE_OFFSET + 0x08) 81239281Sgonzo#define CPSW_ALE_TBLCTL (CPSW_ALE_OFFSET + 0x20) 82239281Sgonzo#define CPSW_ALE_TBLW2 (CPSW_ALE_OFFSET + 0x34) 83239281Sgonzo#define CPSW_ALE_TBLW1 (CPSW_ALE_OFFSET + 0x38) 84239281Sgonzo#define CPSW_ALE_TBLW0 (CPSW_ALE_OFFSET + 0x3C) 85239281Sgonzo#define CPSW_ALE_PORTCTL(p) (CPSW_ALE_OFFSET + 0x40 + ((p) * 0x04)) 86239281Sgonzo 87239281Sgonzo#define CPSW_SL_OFFSET 0x0D80 88239281Sgonzo#define CPSW_SL_MACCONTROL(p) (CPSW_SL_OFFSET + (0x40 * (p)) + 0x04) 89239281Sgonzo#define CPSW_SL_SOFT_RESET(p) (CPSW_SL_OFFSET + (0x40 * (p)) + 0x0C) 90239281Sgonzo#define CPSW_SL_RX_MAXLEN(p) (CPSW_SL_OFFSET + (0x40 * (p)) + 0x10) 91239281Sgonzo#define CPSW_SL_RX_PRI_MAP(p) (CPSW_SL_OFFSET + (0x40 * (p)) + 0x24) 92239281Sgonzo 93239281Sgonzo#define MDIO_OFFSET 0x1000 94239281Sgonzo#define MDIOCONTROL (MDIO_OFFSET + 0x04) 95239281Sgonzo#define MDIOUSERACCESS0 (MDIO_OFFSET + 0x80) 96239281Sgonzo#define MDIOUSERPHYSEL0 (MDIO_OFFSET + 0x84) 97239281Sgonzo 98239281Sgonzo#define CPSW_WR_OFFSET 0x1200 99239281Sgonzo#define CPSW_WR_SOFT_RESET (CPSW_WR_OFFSET + 0x04) 100239281Sgonzo#define CPSW_WR_CONTROL (CPSW_WR_OFFSET + 0x08) 101239281Sgonzo#define CPSW_WR_INT_CONTROL (CPSW_WR_OFFSET + 0x0c) 102239281Sgonzo#define CPSW_WR_C_RX_THRESH_EN(p) (CPSW_WR_OFFSET + (0x10 * (p)) + 0x10) 103239281Sgonzo#define CPSW_WR_C_RX_EN(p) (CPSW_WR_OFFSET + (0x10 * (p)) + 0x14) 104239281Sgonzo#define CPSW_WR_C_TX_EN(p) (CPSW_WR_OFFSET + (0x10 * (p)) + 0x18) 105239281Sgonzo#define CPSW_WR_C_MISC_EN(p) (CPSW_WR_OFFSET + (0x10 * (p)) + 0x1C) 106239281Sgonzo#define CPSW_WR_C_RX_THRESH_STAT(p) (CPSW_WR_OFFSET + (0x10 * (p)) + 0x40) 107239281Sgonzo#define CPSW_WR_C_RX_STAT(p) (CPSW_WR_OFFSET + (0x10 * (p)) + 0x44) 108239281Sgonzo#define CPSW_WR_C_TX_STAT(p) (CPSW_WR_OFFSET + (0x10 * (p)) + 0x48) 109239281Sgonzo#define CPSW_WR_C_MISC_STAT(p) (CPSW_WR_OFFSET + (0x10 * (p)) + 0x4C) 110239281Sgonzo 111239281Sgonzo#define CPSW_CPPI_RAM_OFFSET 0x2000 112239281Sgonzo 113239281Sgonzo#endif /*_IF_CPSWREG_H */ 114