am335x_prcm.c revision 254592
1/*- 2 * Copyright (c) 2012 Damjan Marion <dmarion@Freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> 28__FBSDID("$FreeBSD: head/sys/arm/ti/am335x/am335x_prcm.c 254592 2013-08-21 04:20:17Z ian $"); 29 30#include <sys/param.h> 31#include <sys/systm.h> 32#include <sys/bus.h> 33#include <sys/kernel.h> 34#include <sys/module.h> 35#include <sys/malloc.h> 36#include <sys/rman.h> 37#include <sys/timeet.h> 38#include <sys/timetc.h> 39#include <sys/watchdog.h> 40#include <machine/bus.h> 41#include <machine/cpu.h> 42#include <machine/frame.h> 43#include <machine/intr.h> 44 45#include <arm/ti/tivar.h> 46#include <arm/ti/ti_scm.h> 47#include <arm/ti/ti_prcm.h> 48 49#include <dev/fdt/fdt_common.h> 50#include <dev/ofw/openfirm.h> 51#include <dev/ofw/ofw_bus.h> 52#include <dev/ofw/ofw_bus_subr.h> 53 54#include <machine/bus.h> 55#include <machine/fdt.h> 56 57#define CM_PER 0 58#define CM_PER_L4LS_CLKSTCTRL (CM_PER + 0x000) 59#define CM_PER_L3S_CLKSTCTRL (CM_PER + 0x004) 60#define CM_PER_L3_CLKSTCTRL (CM_PER + 0x00C) 61#define CM_PER_CPGMAC0_CLKCTRL (CM_PER + 0x014) 62#define CM_PER_LCDC_CLKCTRL (CM_PER + 0x018) 63#define CM_PER_USB0_CLKCTRL (CM_PER + 0x01C) 64#define CM_PER_TPTC0_CLKCTRL (CM_PER + 0x024) 65#define CM_PER_UART5_CLKCTRL (CM_PER + 0x038) 66#define CM_PER_MMC0_CLKCTRL (CM_PER + 0x03C) 67#define CM_PER_I2C2_CLKCTRL (CM_PER + 0x044) 68#define CM_PER_I2C1_CLKCTRL (CM_PER + 0x048) 69#define CM_PER_UART1_CLKCTRL (CM_PER + 0x06C) 70#define CM_PER_UART2_CLKCTRL (CM_PER + 0x070) 71#define CM_PER_UART3_CLKCTRL (CM_PER + 0x074) 72#define CM_PER_UART4_CLKCTRL (CM_PER + 0x078) 73#define CM_PER_TIMER7_CLKCTRL (CM_PER + 0x07C) 74#define CM_PER_TIMER2_CLKCTRL (CM_PER + 0x080) 75#define CM_PER_TIMER3_CLKCTRL (CM_PER + 0x084) 76#define CM_PER_TIMER4_CLKCTRL (CM_PER + 0x088) 77#define CM_PER_GPIO1_CLKCTRL (CM_PER + 0x0AC) 78#define CM_PER_GPIO2_CLKCTRL (CM_PER + 0x0B0) 79#define CM_PER_GPIO3_CLKCTRL (CM_PER + 0x0B4) 80#define CM_PER_TPCC_CLKCTRL (CM_PER + 0x0BC) 81#define CM_PER_EPWMSS1_CLKCTRL (CM_PER + 0x0CC) 82#define CM_PER_EPWMSS0_CLKCTRL (CM_PER + 0x0D4) 83#define CM_PER_EPWMSS2_CLKCTRL (CM_PER + 0x0D8) 84#define CM_PER_L3_INSTR_CLKCTRL (CM_PER + 0x0DC) 85#define CM_PER_L3_CLKCTRL (CM_PER + 0x0E0) 86#define CM_PER_PRUSS_CLKCTRL (CM_PER + 0x0E8) 87#define CM_PER_TIMER5_CLKCTRL (CM_PER + 0x0EC) 88#define CM_PER_TIMER6_CLKCTRL (CM_PER + 0x0F0) 89#define CM_PER_MMC1_CLKCTRL (CM_PER + 0x0F4) 90#define CM_PER_MMC2_CLKCTRL (CM_PER + 0x0F8) 91#define CM_PER_TPTC1_CLKCTRL (CM_PER + 0x0FC) 92#define CM_PER_TPTC2_CLKCTRL (CM_PER + 0x100) 93#define CM_PER_SPINLOCK0_CLKCTRL (CM_PER + 0x10C) 94#define CM_PER_MAILBOX0_CLKCTRL (CM_PER + 0x110) 95#define CM_PER_OCPWP_L3_CLKSTCTRL (CM_PER + 0x12C) 96#define CM_PER_OCPWP_CLKCTRL (CM_PER + 0x130) 97#define CM_PER_CPSW_CLKSTCTRL (CM_PER + 0x144) 98#define CM_PER_PRUSS_CLKSTCTRL (CM_PER + 0x140) 99 100#define CM_WKUP 0x400 101#define CM_WKUP_CLKSTCTRL (CM_WKUP + 0x000) 102#define CM_WKUP_CONTROL_CLKCTRL (CM_WKUP + 0x004) 103#define CM_WKUP_GPIO0_CLKCTRL (CM_WKUP + 0x008) 104#define CM_WKUP_CM_L3_AON_CLKSTCTRL (CM_WKUP + 0x01C) 105#define CM_WKUP_CM_CLKSEL_DPLL_MPU (CM_WKUP + 0x02C) 106#define CM_WKUP_CM_IDLEST_DPLL_DISP (CM_WKUP + 0x048) 107#define CM_WKUP_CM_CLKSEL_DPLL_DISP (CM_WKUP + 0x054) 108#define CM_WKUP_CM_CLKDCOLDO_DPLL_PER (CM_WKUP + 0x07C) 109#define CM_WKUP_CM_CLKMODE_DPLL_DISP (CM_WKUP + 0x098) 110#define CM_WKUP_I2C0_CLKCTRL (CM_WKUP + 0x0B8) 111 112#define CM_DPLL 0x500 113#define CLKSEL_TIMER7_CLK (CM_DPLL + 0x004) 114#define CLKSEL_TIMER2_CLK (CM_DPLL + 0x008) 115#define CLKSEL_TIMER3_CLK (CM_DPLL + 0x00C) 116#define CLKSEL_TIMER4_CLK (CM_DPLL + 0x010) 117#define CLKSEL_TIMER5_CLK (CM_DPLL + 0x018) 118#define CLKSEL_TIMER6_CLK (CM_DPLL + 0x01C) 119#define CLKSEL_PRUSS_OCP_CLK (CM_DPLL + 0x030) 120 121#define PRM_PER 0xC00 122#define PRM_PER_RSTCTRL (PRM_PER + 0x00) 123 124#define PRM_DEVICE_OFFSET 0xF00 125#define PRM_RSTCTRL (PRM_DEVICE_OFFSET + 0x00) 126 127struct am335x_prcm_softc { 128 struct resource * res[2]; 129 bus_space_tag_t bst; 130 bus_space_handle_t bsh; 131}; 132 133static struct resource_spec am335x_prcm_spec[] = { 134 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 135 { -1, 0 } 136}; 137 138static struct am335x_prcm_softc *am335x_prcm_sc = NULL; 139 140static int am335x_clk_generic_activate(struct ti_clock_dev *clkdev); 141static int am335x_clk_gpio_activate(struct ti_clock_dev *clkdev); 142static int am335x_clk_generic_deactivate(struct ti_clock_dev *clkdev); 143static int am335x_clk_generic_set_source(struct ti_clock_dev *clkdev, clk_src_t clksrc); 144static int am335x_clk_hsmmc_get_source_freq(struct ti_clock_dev *clkdev, unsigned int *freq); 145static int am335x_clk_get_sysclk_freq(struct ti_clock_dev *clkdev, unsigned int *freq); 146static int am335x_clk_get_arm_fclk_freq(struct ti_clock_dev *clkdev, unsigned int *freq); 147static int am335x_clk_get_arm_disp_freq(struct ti_clock_dev *clkdev, unsigned int *freq); 148static void am335x_prcm_reset(void); 149static int am335x_clk_cpsw_activate(struct ti_clock_dev *clkdev); 150static int am335x_clk_musb0_activate(struct ti_clock_dev *clkdev); 151static int am335x_clk_lcdc_activate(struct ti_clock_dev *clkdev); 152static int am335x_clk_pruss_activate(struct ti_clock_dev *clkdev); 153 154#define AM335X_NOOP_CLOCK_DEV(i) \ 155 { .id = (i) } 156 157#define AM335X_GENERIC_CLOCK_DEV(i) \ 158 { .id = (i), \ 159 .clk_activate = am335x_clk_generic_activate, \ 160 .clk_deactivate = am335x_clk_generic_deactivate, \ 161 .clk_set_source = am335x_clk_generic_set_source, \ 162 .clk_accessible = NULL, \ 163 .clk_get_source_freq = NULL \ 164 } 165 166#define AM335X_GPIO_CLOCK_DEV(i) \ 167 { .id = (i), \ 168 .clk_activate = am335x_clk_gpio_activate, \ 169 .clk_deactivate = am335x_clk_generic_deactivate, \ 170 .clk_set_source = am335x_clk_generic_set_source, \ 171 .clk_accessible = NULL, \ 172 .clk_get_source_freq = NULL \ 173 } 174 175#define AM335X_MMCHS_CLOCK_DEV(i) \ 176 { .id = (i), \ 177 .clk_activate = am335x_clk_generic_activate, \ 178 .clk_deactivate = am335x_clk_generic_deactivate, \ 179 .clk_set_source = am335x_clk_generic_set_source, \ 180 .clk_accessible = NULL, \ 181 .clk_get_source_freq = am335x_clk_hsmmc_get_source_freq \ 182 } 183 184struct ti_clock_dev ti_clk_devmap[] = { 185 /* System clocks */ 186 { .id = SYS_CLK, 187 .clk_activate = NULL, 188 .clk_deactivate = NULL, 189 .clk_set_source = NULL, 190 .clk_accessible = NULL, 191 .clk_get_source_freq = am335x_clk_get_sysclk_freq, 192 }, 193 /* MPU (ARM) core clocks */ 194 { .id = MPU_CLK, 195 .clk_activate = NULL, 196 .clk_deactivate = NULL, 197 .clk_set_source = NULL, 198 .clk_accessible = NULL, 199 .clk_get_source_freq = am335x_clk_get_arm_fclk_freq, 200 }, 201 /* CPSW Ethernet Switch core clocks */ 202 { .id = CPSW_CLK, 203 .clk_activate = am335x_clk_cpsw_activate, 204 .clk_deactivate = NULL, 205 .clk_set_source = NULL, 206 .clk_accessible = NULL, 207 .clk_get_source_freq = NULL, 208 }, 209 210 /* Mentor USB HS controller core clocks */ 211 { .id = MUSB0_CLK, 212 .clk_activate = am335x_clk_musb0_activate, 213 .clk_deactivate = NULL, 214 .clk_set_source = NULL, 215 .clk_accessible = NULL, 216 .clk_get_source_freq = NULL, 217 }, 218 219 /* LCD controller clocks */ 220 { .id = LCDC_CLK, 221 .clk_activate = am335x_clk_lcdc_activate, 222 .clk_deactivate = NULL, 223 .clk_set_source = NULL, 224 .clk_accessible = NULL, 225 .clk_get_source_freq = am335x_clk_get_arm_disp_freq, 226 }, 227 228 /* UART. Uart0 clock cannot be controlled. */ 229 AM335X_NOOP_CLOCK_DEV(UART0_CLK), 230 AM335X_GENERIC_CLOCK_DEV(UART1_CLK), 231 AM335X_GENERIC_CLOCK_DEV(UART2_CLK), 232 AM335X_GENERIC_CLOCK_DEV(UART3_CLK), 233 AM335X_GENERIC_CLOCK_DEV(UART4_CLK), 234 AM335X_GENERIC_CLOCK_DEV(UART5_CLK), 235 236 /* DMTimer */ 237 AM335X_GENERIC_CLOCK_DEV(DMTIMER2_CLK), 238 AM335X_GENERIC_CLOCK_DEV(DMTIMER3_CLK), 239 AM335X_GENERIC_CLOCK_DEV(DMTIMER4_CLK), 240 AM335X_GENERIC_CLOCK_DEV(DMTIMER5_CLK), 241 AM335X_GENERIC_CLOCK_DEV(DMTIMER6_CLK), 242 AM335X_GENERIC_CLOCK_DEV(DMTIMER7_CLK), 243 244 /* GPIO */ 245 AM335X_GPIO_CLOCK_DEV(GPIO0_CLK), 246 AM335X_GPIO_CLOCK_DEV(GPIO1_CLK), 247 AM335X_GPIO_CLOCK_DEV(GPIO2_CLK), 248 AM335X_GPIO_CLOCK_DEV(GPIO3_CLK), 249 250 /* I2C */ 251 AM335X_GENERIC_CLOCK_DEV(I2C0_CLK), 252 AM335X_GENERIC_CLOCK_DEV(I2C1_CLK), 253 AM335X_GENERIC_CLOCK_DEV(I2C2_CLK), 254 255 /* EDMA */ 256 AM335X_GENERIC_CLOCK_DEV(EDMA_TPCC_CLK), 257 AM335X_GENERIC_CLOCK_DEV(EDMA_TPTC0_CLK), 258 AM335X_GENERIC_CLOCK_DEV(EDMA_TPTC1_CLK), 259 AM335X_GENERIC_CLOCK_DEV(EDMA_TPTC2_CLK), 260 261 /* MMCHS */ 262 AM335X_MMCHS_CLOCK_DEV(MMC0_CLK), 263 AM335X_MMCHS_CLOCK_DEV(MMC1_CLK), 264 AM335X_MMCHS_CLOCK_DEV(MMC2_CLK), 265 266 /* PWMSS */ 267 AM335X_GENERIC_CLOCK_DEV(PWMSS0_CLK), 268 AM335X_GENERIC_CLOCK_DEV(PWMSS1_CLK), 269 AM335X_GENERIC_CLOCK_DEV(PWMSS2_CLK), 270 271 /* System Mailbox clock */ 272 AM335X_GENERIC_CLOCK_DEV(MAILBOX0_CLK), 273 274 /* SPINLOCK */ 275 AM335X_GENERIC_CLOCK_DEV(SPINLOCK0_CLK), 276 277 /* PRU-ICSS */ 278 { .id = PRUSS_CLK, 279 .clk_activate = am335x_clk_pruss_activate, 280 .clk_deactivate = NULL, 281 .clk_set_source = NULL, 282 .clk_accessible = NULL, 283 .clk_get_source_freq = NULL, 284 }, 285 286 287 288 { INVALID_CLK_IDENT, NULL, NULL, NULL, NULL } 289}; 290 291struct am335x_clk_details { 292 clk_ident_t id; 293 uint32_t clkctrl_reg; 294 uint32_t clksel_reg; 295}; 296 297#define _CLK_DETAIL(i, c, s) \ 298 { .id = (i), \ 299 .clkctrl_reg = (c), \ 300 .clksel_reg = (s), \ 301 } 302 303static struct am335x_clk_details g_am335x_clk_details[] = { 304 305 /* UART. UART0 clock not controllable. */ 306 _CLK_DETAIL(UART0_CLK, 0, 0), 307 _CLK_DETAIL(UART1_CLK, CM_PER_UART1_CLKCTRL, 0), 308 _CLK_DETAIL(UART2_CLK, CM_PER_UART2_CLKCTRL, 0), 309 _CLK_DETAIL(UART3_CLK, CM_PER_UART3_CLKCTRL, 0), 310 _CLK_DETAIL(UART4_CLK, CM_PER_UART4_CLKCTRL, 0), 311 _CLK_DETAIL(UART5_CLK, CM_PER_UART5_CLKCTRL, 0), 312 313 /* DMTimer modules */ 314 _CLK_DETAIL(DMTIMER2_CLK, CM_PER_TIMER2_CLKCTRL, CLKSEL_TIMER2_CLK), 315 _CLK_DETAIL(DMTIMER3_CLK, CM_PER_TIMER3_CLKCTRL, CLKSEL_TIMER3_CLK), 316 _CLK_DETAIL(DMTIMER4_CLK, CM_PER_TIMER4_CLKCTRL, CLKSEL_TIMER4_CLK), 317 _CLK_DETAIL(DMTIMER5_CLK, CM_PER_TIMER5_CLKCTRL, CLKSEL_TIMER5_CLK), 318 _CLK_DETAIL(DMTIMER6_CLK, CM_PER_TIMER6_CLKCTRL, CLKSEL_TIMER6_CLK), 319 _CLK_DETAIL(DMTIMER7_CLK, CM_PER_TIMER7_CLKCTRL, CLKSEL_TIMER7_CLK), 320 321 /* GPIO modules */ 322 _CLK_DETAIL(GPIO0_CLK, CM_WKUP_GPIO0_CLKCTRL, 0), 323 _CLK_DETAIL(GPIO1_CLK, CM_PER_GPIO1_CLKCTRL, 0), 324 _CLK_DETAIL(GPIO2_CLK, CM_PER_GPIO2_CLKCTRL, 0), 325 _CLK_DETAIL(GPIO3_CLK, CM_PER_GPIO3_CLKCTRL, 0), 326 327 /* I2C modules */ 328 _CLK_DETAIL(I2C0_CLK, CM_WKUP_I2C0_CLKCTRL, 0), 329 _CLK_DETAIL(I2C1_CLK, CM_PER_I2C1_CLKCTRL, 0), 330 _CLK_DETAIL(I2C2_CLK, CM_PER_I2C2_CLKCTRL, 0), 331 332 /* EDMA modules */ 333 _CLK_DETAIL(EDMA_TPCC_CLK, CM_PER_TPCC_CLKCTRL, 0), 334 _CLK_DETAIL(EDMA_TPTC0_CLK, CM_PER_TPTC0_CLKCTRL, 0), 335 _CLK_DETAIL(EDMA_TPTC1_CLK, CM_PER_TPTC1_CLKCTRL, 0), 336 _CLK_DETAIL(EDMA_TPTC2_CLK, CM_PER_TPTC2_CLKCTRL, 0), 337 338 /* MMCHS modules*/ 339 _CLK_DETAIL(MMC0_CLK, CM_PER_MMC0_CLKCTRL, 0), 340 _CLK_DETAIL(MMC1_CLK, CM_PER_MMC1_CLKCTRL, 0), 341 _CLK_DETAIL(MMC2_CLK, CM_PER_MMC1_CLKCTRL, 0), 342 343 /* PWMSS modules */ 344 _CLK_DETAIL(PWMSS0_CLK, CM_PER_EPWMSS0_CLKCTRL, 0), 345 _CLK_DETAIL(PWMSS1_CLK, CM_PER_EPWMSS1_CLKCTRL, 0), 346 _CLK_DETAIL(PWMSS2_CLK, CM_PER_EPWMSS2_CLKCTRL, 0), 347 348 _CLK_DETAIL(MAILBOX0_CLK, CM_PER_MAILBOX0_CLKCTRL, 0), 349 _CLK_DETAIL(SPINLOCK0_CLK, CM_PER_SPINLOCK0_CLKCTRL, 0), 350 351 { INVALID_CLK_IDENT, 0}, 352}; 353 354/* Read/Write macros */ 355#define prcm_read_4(reg) \ 356 bus_space_read_4(am335x_prcm_sc->bst, am335x_prcm_sc->bsh, reg) 357#define prcm_write_4(reg, val) \ 358 bus_space_write_4(am335x_prcm_sc->bst, am335x_prcm_sc->bsh, reg, val) 359 360void am335x_prcm_setup_dmtimer(int); 361 362static int 363am335x_prcm_probe(device_t dev) 364{ 365 if (ofw_bus_is_compatible(dev, "am335x,prcm")) { 366 device_set_desc(dev, "AM335x Power and Clock Management"); 367 return(BUS_PROBE_DEFAULT); 368 } 369 370 return (ENXIO); 371} 372 373static int 374am335x_prcm_attach(device_t dev) 375{ 376 struct am335x_prcm_softc *sc = device_get_softc(dev); 377 unsigned int sysclk, fclk; 378 379 if (am335x_prcm_sc) 380 return (ENXIO); 381 382 if (bus_alloc_resources(dev, am335x_prcm_spec, sc->res)) { 383 device_printf(dev, "could not allocate resources\n"); 384 return (ENXIO); 385 } 386 387 sc->bst = rman_get_bustag(sc->res[0]); 388 sc->bsh = rman_get_bushandle(sc->res[0]); 389 390 am335x_prcm_sc = sc; 391 ti_cpu_reset = am335x_prcm_reset; 392 393 am335x_clk_get_sysclk_freq(NULL, &sysclk); 394 am335x_clk_get_arm_fclk_freq(NULL, &fclk); 395 device_printf(dev, "Clocks: System %u.%01u MHz, CPU %u MHz\n", 396 sysclk/1000000, (sysclk % 1000000)/100000, fclk/1000000); 397 398 return (0); 399} 400 401static device_method_t am335x_prcm_methods[] = { 402 DEVMETHOD(device_probe, am335x_prcm_probe), 403 DEVMETHOD(device_attach, am335x_prcm_attach), 404 { 0, 0 } 405}; 406 407static driver_t am335x_prcm_driver = { 408 "am335x_prcm", 409 am335x_prcm_methods, 410 sizeof(struct am335x_prcm_softc), 411}; 412 413static devclass_t am335x_prcm_devclass; 414 415DRIVER_MODULE(am335x_prcm, simplebus, am335x_prcm_driver, 416 am335x_prcm_devclass, 0, 0); 417MODULE_DEPEND(am335x_prcm, ti_scm, 1, 1, 1); 418 419static struct am335x_clk_details* 420am335x_clk_details(clk_ident_t id) 421{ 422 struct am335x_clk_details *walker; 423 424 for (walker = g_am335x_clk_details; walker->id != INVALID_CLK_IDENT; walker++) { 425 if (id == walker->id) 426 return (walker); 427 } 428 429 return NULL; 430} 431 432static int 433am335x_clk_generic_activate(struct ti_clock_dev *clkdev) 434{ 435 struct am335x_prcm_softc *sc = am335x_prcm_sc; 436 struct am335x_clk_details* clk_details; 437 438 if (sc == NULL) 439 return ENXIO; 440 441 clk_details = am335x_clk_details(clkdev->id); 442 443 if (clk_details == NULL) 444 return (ENXIO); 445 446 /* set *_CLKCTRL register MODULEMODE[1:0] to enable(2) */ 447 prcm_write_4(clk_details->clkctrl_reg, 2); 448 while ((prcm_read_4(clk_details->clkctrl_reg) & 0x3) != 2) 449 DELAY(10); 450 451 return (0); 452} 453 454static int 455am335x_clk_gpio_activate(struct ti_clock_dev *clkdev) 456{ 457 struct am335x_prcm_softc *sc = am335x_prcm_sc; 458 struct am335x_clk_details* clk_details; 459 460 if (sc == NULL) 461 return ENXIO; 462 463 clk_details = am335x_clk_details(clkdev->id); 464 465 if (clk_details == NULL) 466 return (ENXIO); 467 468 /* set *_CLKCTRL register MODULEMODE[1:0] to enable(2) */ 469 /* set *_CLKCTRL register OPTFCLKEN_GPIO_1_G DBCLK[18] to FCLK_EN(1) */ 470 prcm_write_4(clk_details->clkctrl_reg, 2 | (1 << 18)); 471 while ((prcm_read_4(clk_details->clkctrl_reg) & 472 (3 | (1 << 18) )) != (2 | (1 << 18))) 473 DELAY(10); 474 475 return (0); 476} 477 478static int 479am335x_clk_generic_deactivate(struct ti_clock_dev *clkdev) 480{ 481 struct am335x_prcm_softc *sc = am335x_prcm_sc; 482 struct am335x_clk_details* clk_details; 483 484 if (sc == NULL) 485 return ENXIO; 486 487 clk_details = am335x_clk_details(clkdev->id); 488 489 if (clk_details == NULL) 490 return (ENXIO); 491 492 /* set *_CLKCTRL register MODULEMODE[1:0] to disable(0) */ 493 prcm_write_4(clk_details->clkctrl_reg, 0); 494 while ((prcm_read_4(clk_details->clkctrl_reg) & 0x3) != 0) 495 DELAY(10); 496 497 return (0); 498} 499 500static int 501am335x_clk_generic_set_source(struct ti_clock_dev *clkdev, clk_src_t clksrc) 502{ 503 struct am335x_prcm_softc *sc = am335x_prcm_sc; 504 struct am335x_clk_details* clk_details; 505 uint32_t reg; 506 507 if (sc == NULL) 508 return ENXIO; 509 510 clk_details = am335x_clk_details(clkdev->id); 511 512 if (clk_details == NULL) 513 return (ENXIO); 514 515 switch (clksrc) { 516 case EXT_CLK: 517 reg = 0; /* SEL2: TCLKIN clock */ 518 break; 519 case SYSCLK_CLK: 520 reg = 1; /* SEL1: CLK_M_OSC clock */ 521 break; 522 case F32KHZ_CLK: 523 reg = 2; /* SEL3: CLK_32KHZ clock */ 524 break; 525 default: 526 return (ENXIO); 527 } 528 529 prcm_write_4(clk_details->clksel_reg, reg); 530 while ((prcm_read_4(clk_details->clksel_reg) & 0x3) != reg) 531 DELAY(10); 532 533 return (0); 534} 535 536static int 537am335x_clk_hsmmc_get_source_freq(struct ti_clock_dev *clkdev, unsigned int *freq) 538{ 539 *freq = 96000000; 540 return (0); 541} 542 543static int 544am335x_clk_get_sysclk_freq(struct ti_clock_dev *clkdev, unsigned int *freq) 545{ 546 uint32_t ctrl_status; 547 548 /* Read the input clock freq from the control module */ 549 /* control_status reg (0x40) */ 550 if (ti_scm_reg_read_4(0x40, &ctrl_status)) 551 return ENXIO; 552 553 switch ((ctrl_status>>22) & 0x3) { 554 case 0x0: 555 /* 19.2Mhz */ 556 *freq = 19200000; 557 break; 558 case 0x1: 559 /* 24Mhz */ 560 *freq = 24000000; 561 break; 562 case 0x2: 563 /* 25Mhz */ 564 *freq = 25000000; 565 break; 566 case 0x3: 567 /* 26Mhz */ 568 *freq = 26000000; 569 break; 570 } 571 572 return (0); 573} 574 575#define DPLL_BYP_CLKSEL(reg) ((reg>>23) & 1) 576#define DPLL_DIV(reg) ((reg & 0x7f)+1) 577#define DPLL_MULT(reg) ((reg>>8) & 0x7FF) 578 579static int 580am335x_clk_get_arm_fclk_freq(struct ti_clock_dev *clkdev, unsigned int *freq) 581{ 582 uint32_t reg; 583 uint32_t sysclk; 584 585 reg = prcm_read_4(CM_WKUP_CM_CLKSEL_DPLL_MPU); 586 587 /*Check if we are running in bypass */ 588 if (DPLL_BYP_CLKSEL(reg)) 589 return ENXIO; 590 591 am335x_clk_get_sysclk_freq(NULL, &sysclk); 592 *freq = DPLL_MULT(reg) * (sysclk / DPLL_DIV(reg)); 593 return(0); 594} 595 596static int 597am335x_clk_get_arm_disp_freq(struct ti_clock_dev *clkdev, unsigned int *freq) 598{ 599 uint32_t reg; 600 uint32_t sysclk; 601 602 reg = prcm_read_4(CM_WKUP_CM_CLKSEL_DPLL_DISP); 603 604 /*Check if we are running in bypass */ 605 if (DPLL_BYP_CLKSEL(reg)) 606 return ENXIO; 607 608 am335x_clk_get_sysclk_freq(NULL, &sysclk); 609 *freq = DPLL_MULT(reg) * (sysclk / DPLL_DIV(reg)); 610 return(0); 611} 612 613static void 614am335x_prcm_reset(void) 615{ 616 prcm_write_4(PRM_RSTCTRL, (1<<1)); 617} 618 619static int 620am335x_clk_cpsw_activate(struct ti_clock_dev *clkdev) 621{ 622 struct am335x_prcm_softc *sc = am335x_prcm_sc; 623 624 if (sc == NULL) 625 return ENXIO; 626 627 /* set MODULENAME to ENABLE */ 628 prcm_write_4(CM_PER_CPGMAC0_CLKCTRL, 2); 629 630 /* wait for IDLEST to become Func(0) */ 631 while(prcm_read_4(CM_PER_CPGMAC0_CLKCTRL) & (3<<16)); 632 633 /*set CLKTRCTRL to SW_WKUP(2) */ 634 prcm_write_4(CM_PER_CPSW_CLKSTCTRL, 2); 635 636 /* wait for 125 MHz OCP clock to become active */ 637 while((prcm_read_4(CM_PER_CPSW_CLKSTCTRL) & (1<<4)) == 0); 638 return(0); 639} 640 641static int 642am335x_clk_musb0_activate(struct ti_clock_dev *clkdev) 643{ 644 struct am335x_prcm_softc *sc = am335x_prcm_sc; 645 646 if (sc == NULL) 647 return ENXIO; 648 649 /* set ST_DPLL_CLKDCOLDO(9) to CLK_GATED(1) */ 650 /* set DPLL_CLKDCOLDO_GATE_CTRL(8) to CLK_ENABLE(1)*/ 651 prcm_write_4(CM_WKUP_CM_CLKDCOLDO_DPLL_PER, 0x300); 652 653 /*set MODULEMODE to ENABLE(2) */ 654 prcm_write_4(CM_PER_USB0_CLKCTRL, 2); 655 656 /* wait for MODULEMODE to become ENABLE(2) */ 657 while ((prcm_read_4(CM_PER_USB0_CLKCTRL) & 0x3) != 2) 658 DELAY(10); 659 660 /* wait for IDLEST to become Func(0) */ 661 while(prcm_read_4(CM_PER_USB0_CLKCTRL) & (3<<16)) 662 DELAY(10); 663 664 return(0); 665} 666 667static int 668am335x_clk_lcdc_activate(struct ti_clock_dev *clkdev) 669{ 670 struct am335x_prcm_softc *sc = am335x_prcm_sc; 671 672 if (sc == NULL) 673 return (ENXIO); 674 675 /* Bypass mode */ 676 prcm_write_4(CM_WKUP_CM_CLKMODE_DPLL_DISP, 0x4); 677 678 /* Make sure it's in bypass mode */ 679 while (!(prcm_read_4(CM_WKUP_CM_IDLEST_DPLL_DISP) 680 & (1 << 8))) 681 DELAY(10); 682 683 /* 684 * For now set frequency to 5xSYSFREQ 685 * More flexible control might be required 686 */ 687 prcm_write_4(CM_WKUP_CM_CLKSEL_DPLL_DISP, (5 << 8) | 0); 688 689 /* Locked mode */ 690 prcm_write_4(CM_WKUP_CM_CLKMODE_DPLL_DISP, 0x7); 691 692 int timeout = 10000; 693 while ((!(prcm_read_4(CM_WKUP_CM_IDLEST_DPLL_DISP) 694 & (1 << 0))) && timeout--) 695 DELAY(10); 696 697 /*set MODULEMODE to ENABLE(2) */ 698 prcm_write_4(CM_PER_LCDC_CLKCTRL, 2); 699 700 /* wait for MODULEMODE to become ENABLE(2) */ 701 while ((prcm_read_4(CM_PER_LCDC_CLKCTRL) & 0x3) != 2) 702 DELAY(10); 703 704 /* wait for IDLEST to become Func(0) */ 705 while(prcm_read_4(CM_PER_LCDC_CLKCTRL) & (3<<16)) 706 DELAY(10); 707 708 return (0); 709} 710 711static int 712am335x_clk_pruss_activate(struct ti_clock_dev *clkdev) 713{ 714 struct am335x_prcm_softc *sc = am335x_prcm_sc; 715 716 if (sc == NULL) 717 return (ENXIO); 718 719 /* Set MODULEMODE to ENABLE(2) */ 720 prcm_write_4(CM_PER_PRUSS_CLKCTRL, 2); 721 722 /* Wait for MODULEMODE to become ENABLE(2) */ 723 while ((prcm_read_4(CM_PER_PRUSS_CLKCTRL) & 0x3) != 2) 724 DELAY(10); 725 726 /* Set CLKTRCTRL to SW_WKUP(2) */ 727 prcm_write_4(CM_PER_PRUSS_CLKSTCTRL, 2); 728 729 /* Wait for the 200 MHz OCP clock to become active */ 730 while ((prcm_read_4(CM_PER_PRUSS_CLKSTCTRL) & (1<<4)) == 0) 731 DELAY(10); 732 733 /* Wait for the 200 MHz IEP clock to become active */ 734 while ((prcm_read_4(CM_PER_PRUSS_CLKSTCTRL) & (1<<5)) == 0) 735 DELAY(10); 736 737 /* Wait for the 192 MHz UART clock to become active */ 738 while ((prcm_read_4(CM_PER_PRUSS_CLKSTCTRL) & (1<<6)) == 0) 739 DELAY(10); 740 741 /* Select DISP DPLL as OCP clock */ 742 prcm_write_4(CLKSEL_PRUSS_OCP_CLK, 1); 743 while ((prcm_read_4(CLKSEL_PRUSS_OCP_CLK) & 0x3) != 1) 744 DELAY(10); 745 746 /* Clear the RESET bit */ 747 prcm_write_4(PRM_PER_RSTCTRL, prcm_read_4(PRM_PER_RSTCTRL) & ~2); 748 749 return (0); 750} 751