mvwin.h revision 250291
1/*- 2 * Copyright (C) 2007-2011 MARVELL INTERNATIONAL LTD. 3 * All rights reserved. 4 * 5 * Developed by Semihalf. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. Neither the name of MARVELL nor the names of contributors 16 * may be used to endorse or promote products derived from this software 17 * without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 * $FreeBSD: head/sys/arm/mv/mvwin.h 250291 2013-05-06 13:34:36Z gber $ 32 */ 33 34#ifndef _MVWIN_H_ 35#define _MVWIN_H_ 36 37/* 38 * Decode windows addresses. 39 * 40 * All decoding windows must be aligned to their size, which has to be 41 * a power of 2. 42 */ 43 44/* 45 * SoC Integrated devices: 0xF1000000, 16 MB (VA == PA) 46 */ 47 48/* SoC Regs */ 49#define MV_PHYS_BASE 0xF1000000 50#define MV_SIZE (1024 * 1024) /* 1 MB */ 51 52/* SRAM */ 53#define MV_CESA_SRAM_BASE 0xF1100000 54 55/* AXI Regs */ 56#ifdef SOC_MV_DOVE 57#define MV_AXI_PHYS_BASE 0xF1800000 58#define MV_AXI_BASE MV_AXI_PHYS_BASE 59#define MV_AXI_SIZE (16 * 1024 * 1024) /* 16 MB */ 60#endif 61 62/* 63 * External devices: 0x80000000, 1 GB (VA == PA) 64 * Includes Device Bus, PCI and PCIE. 65 */ 66#if defined(SOC_MV_ORION) 67#define MV_PCI_PORTS 2 /* 1x PCI + 1x PCIE */ 68#elif defined(SOC_MV_KIRKWOOD) || defined(SOC_MV_FREY) 69#define MV_PCI_PORTS 1 /* 1x PCIE */ 70#elif defined(SOC_MV_DISCOVERY) 71#define MV_PCI_PORTS 8 /* 8x PCIE */ 72#elif defined(SOC_MV_DOVE) || defined(SOC_MV_LOKIPLUS) 73#define MV_PCI_PORTS 2 /* 2x PCIE */ 74#elif defined(SOC_MV_ARMADAXP) 75#define MV_PCI_PORTS 3 /* 3x PCIE */ 76#else 77#error "MV_PCI_PORTS not configured !" 78#endif 79 80/* PCI/PCIE Memory */ 81#define MV_PCI_MEM_PHYS_BASE 0x80000000 82#define MV_PCI_MEM_SIZE (512 * 1024 * 1024) /* 512 MB */ 83#define MV_PCI_MEM_BASE MV_PCI_MEM_PHYS_BASE 84#define MV_PCI_MEM_SLICE_SIZE (MV_PCI_MEM_SIZE / MV_PCI_PORTS) 85#define MV_PCI_MEM_SLICE(n) (MV_PCI_MEM_BASE + ((n) * \ 86 MV_PCI_MEM_SLICE_SIZE)) 87/* PCI/PCIE I/O */ 88#define MV_PCI_IO_PHYS_BASE 0xBF000000 89#define MV_PCI_IO_SIZE (16 * 1024 * 1024) /* 16 MB */ 90#define MV_PCI_IO_BASE MV_PCI_IO_PHYS_BASE 91#define MV_PCI_IO_SLICE_SIZE (MV_PCI_IO_SIZE / MV_PCI_PORTS) 92#define MV_PCI_IO_SLICE(n) (MV_PCI_IO_BASE + ((n) * MV_PCI_IO_SLICE_SIZE)) 93 94#if defined(SOC_MV_FREY) 95#define MV_PCI_VA_MEM_BASE MV_PCI_MEM_BASE 96#else 97#define MV_PCI_VA_MEM_BASE 0 98#endif 99#define MV_PCI_VA_IO_BASE 0 100 101/* 102 * Device Bus (VA == PA) 103 */ 104#define MV_DEV_BOOT_BASE 0xF9300000 105#define MV_DEV_BOOT_SIZE (1024 * 1024) /* 1 MB */ 106 107#define MV_DEV_CS0_BASE 0xF9400000 108#define MV_DEV_CS0_SIZE (1024 * 1024) /* 1 MB */ 109 110#define MV_DEV_CS1_BASE 0xF9500000 111#define MV_DEV_CS1_SIZE (32 * 1024 * 1024) /* 32 MB */ 112 113#define MV_DEV_CS2_BASE 0xFB500000 114#define MV_DEV_CS2_SIZE (1024 * 1024) /* 1 MB */ 115 116 117/* 118 * Integrated SoC peripherals addresses 119 */ 120#define MV_BASE MV_PHYS_BASE /* VA == PA mapping */ 121#if defined(SOC_MV_DOVE) 122#define MV_DDR_CADR_BASE (MV_AXI_BASE + 0x100) 123#elif defined(SOC_MV_LOKIPLUS) 124#define MV_DDR_CADR_BASE (MV_BASE + 0xF1500) 125#else 126#define MV_DDR_CADR_BASE (MV_BASE + 0x1500) 127#endif 128#define MV_MPP_BASE (MV_BASE + 0x10000) 129 130#if defined(SOC_MV_ARMADAXP) 131#define MV_MISC_BASE (MV_BASE + 0x18200) 132#define MV_MBUS_BRIDGE_BASE (MV_BASE + 0x20000) 133#define MV_INTREGS_BASE (MV_MBUS_BRIDGE_BASE + 0x80) 134#define MV_MP_CLOCKS_BASE (MV_MBUS_BRIDGE_BASE + 0x700) 135#define MV_CPU_CONTROL_BASE (MV_MBUS_BRIDGE_BASE + 0x1800) 136#elif !defined(SOC_MV_FREY) 137#define MV_MBUS_BRIDGE_BASE (MV_BASE + 0x20000) 138#define MV_INTREGS_BASE (MV_MBUS_BRIDGE_BASE + 0x80) 139#define MV_CPU_CONTROL_BASE (MV_MBUS_BRIDGE_BASE + 0x100) 140#else 141#define MV_CPU_CONTROL_BASE (MV_BASE + 0x10000) 142#endif 143 144#define MV_PCI_BASE (MV_BASE + 0x30000) 145#define MV_PCI_SIZE 0x2000 146 147#if defined(SOC_MV_FREY) 148#define MV_PCIE_BASE (MV_BASE + 0x8000) 149#else 150#define MV_PCIE_BASE (MV_BASE + 0x40000) 151#endif 152#define MV_PCIE_SIZE 0x2000 153 154#define MV_PCIE00_BASE (MV_PCIE_BASE + 0x00000) 155#define MV_PCIE01_BASE (MV_PCIE_BASE + 0x04000) 156#define MV_PCIE02_BASE (MV_PCIE_BASE + 0x08000) 157#define MV_PCIE03_BASE (MV_PCIE_BASE + 0x0C000) 158#define MV_PCIE10_BASE (MV_PCIE_BASE + 0x40000) 159#define MV_PCIE11_BASE (MV_PCIE_BASE + 0x44000) 160#define MV_PCIE12_BASE (MV_PCIE_BASE + 0x48000) 161#define MV_PCIE13_BASE (MV_PCIE_BASE + 0x4C000) 162 163#define MV_SDIO_BASE (MV_BASE + 0x90000) 164#define MV_SDIO_SIZE 0x10000 165 166/* 167 * Decode windows definitions and macros 168 */ 169#if defined(SOC_MV_ARMADAXP) 170#define MV_WIN_CPU_CTRL(n) (((n) < 8) ? 0x10 * (n) : 0x90 + (0x8 * ((n) - 8))) 171#define MV_WIN_CPU_BASE(n) ((((n) < 8) ? 0x10 * (n) : 0x90 + (0x8 * ((n) - 8))) + 0x4) 172#define MV_WIN_CPU_REMAP_LO(n) (0x10 * (n) + 0x008) 173#define MV_WIN_CPU_REMAP_HI(n) (0x10 * (n) + 0x00C) 174#else 175#define MV_WIN_CPU_CTRL(n) (0x10 * (n) + (((n) < 8) ? 0x000 : 0x880)) 176#define MV_WIN_CPU_BASE(n) (0x10 * (n) + (((n) < 8) ? 0x004 : 0x884)) 177#define MV_WIN_CPU_REMAP_LO(n) (0x10 * (n) + (((n) < 8) ? 0x008 : 0x888)) 178#define MV_WIN_CPU_REMAP_HI(n) (0x10 * (n) + (((n) < 8) ? 0x00C : 0x88C)) 179#endif 180 181#if defined(SOC_MV_DISCOVERY) 182#define MV_WIN_CPU_MAX 14 183#elif defined(SOC_MV_ARMADAXP) 184#define MV_WIN_CPU_MAX 20 185#else 186#define MV_WIN_CPU_MAX 8 187#endif 188 189#define MV_WIN_CPU_ATTR_SHIFT 8 190#if defined(SOC_MV_LOKIPLUS) 191#define MV_WIN_CPU_TARGET_SHIFT 0 192#define MV_WIN_CPU_ENABLE_BIT (1 << 5) 193#else 194#define MV_WIN_CPU_TARGET_SHIFT 4 195#define MV_WIN_CPU_ENABLE_BIT 1 196#endif 197 198#if defined(SOC_MV_DOVE) 199#define MV_WIN_DDR_MAX 2 200#else /* SOC_MV_DOVE */ 201#if defined(SOC_MV_LOKIPLUS) 202#define MV_WIN_DDR_BASE(n) (0xc * (n) + 0x4) 203#define MV_WIN_DDR_SIZE(n) (0xc * (n) + 0x0) 204#else /* SOC_MV_LOKIPLUS */ 205#define MV_WIN_DDR_BASE(n) (0x8 * (n) + 0x0) 206#define MV_WIN_DDR_SIZE(n) (0x8 * (n) + 0x4) 207#endif /* SOC_MV_LOKIPLUS */ 208#define MV_WIN_DDR_MAX 4 209#endif /* SOC_MV_DOVE */ 210 211/* 212 * These values are valid only for peripherals decoding windows 213 * Bit in ATTR is zeroed according to CS bank number 214 */ 215#define MV_WIN_DDR_ATTR(cs) (0x0F & ~(0x01 << (cs))) 216#define MV_WIN_DDR_TARGET 0x0 217 218#if defined(SOC_MV_DISCOVERY) 219#define MV_WIN_CESA_TARGET 9 220#define MV_WIN_CESA_ATTR(eng_sel) 1 221#elif defined(SOC_MV_ARMADAXP) 222#define MV_WIN_CESA_TARGET 9 223/* 224 * Bits [2:3] of cesa attribute select engine: 225 * eng_sel: 226 * 1: engine1 227 * 2: engine0 228 */ 229#define MV_WIN_CESA_ATTR(eng_sel) (1 | ((eng_sel) << 2)) 230#else 231#define MV_WIN_CESA_TARGET 3 232#define MV_WIN_CESA_ATTR(eng_sel) 0 233#endif 234 235#define MV_WIN_USB_CTRL(n) (0x10 * (n) + 0x320) 236#define MV_WIN_USB_BASE(n) (0x10 * (n) + 0x324) 237#define MV_WIN_USB_MAX 4 238 239#define MV_WIN_ETH_BASE(n) (0x8 * (n) + 0x200) 240#define MV_WIN_ETH_SIZE(n) (0x8 * (n) + 0x204) 241#define MV_WIN_ETH_REMAP(n) (0x4 * (n) + 0x280) 242#define MV_WIN_ETH_MAX 6 243 244#define MV_WIN_IDMA_BASE(n) (0x8 * (n) + 0xa00) 245#define MV_WIN_IDMA_SIZE(n) (0x8 * (n) + 0xa04) 246#define MV_WIN_IDMA_REMAP(n) (0x4 * (n) + 0xa60) 247#define MV_WIN_IDMA_CAP(n) (0x4 * (n) + 0xa70) 248#define MV_WIN_IDMA_MAX 8 249#define MV_IDMA_CHAN_MAX 4 250 251#define MV_WIN_XOR_BASE(n, m) (0x4 * (n) + 0xa50 + (m) * 0x100) 252#define MV_WIN_XOR_SIZE(n, m) (0x4 * (n) + 0xa70 + (m) * 0x100) 253#define MV_WIN_XOR_REMAP(n, m) (0x4 * (n) + 0xa90 + (m) * 0x100) 254#define MV_WIN_XOR_CTRL(n, m) (0x4 * (n) + 0xa40 + (m) * 0x100) 255#define MV_WIN_XOR_OVERR(n, m) (0x4 * (n) + 0xaa0 + (m) * 0x100) 256#define MV_WIN_XOR_MAX 8 257#define MV_XOR_CHAN_MAX 2 258#define MV_XOR_NON_REMAP 4 259 260#if defined(SOC_MV_DISCOVERY) || defined(SOC_MV_KIRKWOOD) || defined(SOC_MV_DOVE) 261#define MV_WIN_PCIE_TARGET(n) 4 262#define MV_WIN_PCIE_MEM_ATTR(n) 0xE8 263#define MV_WIN_PCIE_IO_ATTR(n) 0xE0 264#elif defined(SOC_MV_ARMADAXP) 265#define MV_WIN_PCIE_TARGET(n) (4 + (4 * ((n) % 2))) 266#define MV_WIN_PCIE_MEM_ATTR(n) (0xE8 + (0x10 * ((n) / 2))) 267#define MV_WIN_PCIE_IO_ATTR(n) (0xE0 + (0x10 * ((n) / 2))) 268#elif defined(SOC_MV_ORION) 269#define MV_WIN_PCIE_TARGET(n) 4 270#define MV_WIN_PCIE_MEM_ATTR(n) 0x59 271#define MV_WIN_PCIE_IO_ATTR(n) 0x51 272#elif defined(SOC_MV_LOKIPLUS) 273#define MV_WIN_PCIE_TARGET(n) (3 + (n)) 274#define MV_WIN_PCIE_MEM_ATTR(n) 0x59 275#define MV_WIN_PCIE_IO_ATTR(n) 0x51 276#endif 277 278#define MV_WIN_PCI_TARGET 3 279#define MV_WIN_PCI_MEM_ATTR 0x59 280#define MV_WIN_PCI_IO_ATTR 0x51 281 282#define MV_WIN_PCIE_CTRL(n) (0x10 * (((n) < 5) ? (n) : \ 283 (n) + 1) + 0x1820) 284#define MV_WIN_PCIE_BASE(n) (0x10 * (((n) < 5) ? (n) : \ 285 (n) + 1) + 0x1824) 286#define MV_WIN_PCIE_REMAP(n) (0x10 * (((n) < 5) ? (n) : \ 287 (n) + 1) + 0x182C) 288#define MV_WIN_PCIE_MAX 6 289 290#define MV_PCIE_BAR_CTRL(n) (0x04 * (n) + 0x1800) 291#define MV_PCIE_BAR_BASE(n) (0x08 * ((n) < 3 ? (n) : 4) + 0x0010) 292#define MV_PCIE_BAR_BASE_H(n) (0x08 * (n) + 0x0014) 293#define MV_PCIE_BAR_MAX 4 294#define MV_PCIE_BAR_64BIT (0x4) 295#define MV_PCIE_BAR_PREFETCH_EN (0x8) 296 297#define MV_PCIE_CONTROL (0x1a00) 298#define MV_PCIE_ROOT_CMPLX (1 << 1) 299 300#define MV_WIN_SATA_CTRL(n) (0x10 * (n) + 0x30) 301#define MV_WIN_SATA_BASE(n) (0x10 * (n) + 0x34) 302#define MV_WIN_SATA_MAX 4 303 304#define WIN_REG_IDX_RD(pre,reg,off,base) \ 305 static __inline uint32_t \ 306 pre ## _ ## reg ## _read(int i) \ 307 { \ 308 return (bus_space_read_4(fdtbus_bs_tag, base, off(i))); \ 309 } 310 311#define WIN_REG_IDX_RD2(pre,reg,off,base) \ 312 static __inline uint32_t \ 313 pre ## _ ## reg ## _read(int i, int j) \ 314 { \ 315 return (bus_space_read_4(fdtbus_bs_tag, base, off(i, j))); \ 316 } \ 317 318#define WIN_REG_BASE_IDX_RD(pre,reg,off) \ 319 static __inline uint32_t \ 320 pre ## _ ## reg ## _read(uint32_t base, int i) \ 321 { \ 322 return (bus_space_read_4(fdtbus_bs_tag, base, off(i))); \ 323 } 324 325#define WIN_REG_BASE_IDX_RD2(pre,reg,off) \ 326 static __inline uint32_t \ 327 pre ## _ ## reg ## _read(uint32_t base, int i, int j) \ 328 { \ 329 return (bus_space_read_4(fdtbus_bs_tag, base, off(i, j))); \ 330 } 331 332#define WIN_REG_IDX_WR(pre,reg,off,base) \ 333 static __inline void \ 334 pre ## _ ## reg ## _write(int i, uint32_t val) \ 335 { \ 336 bus_space_write_4(fdtbus_bs_tag, base, off(i), val); \ 337 } 338 339#define WIN_REG_IDX_WR2(pre,reg,off,base) \ 340 static __inline void \ 341 pre ## _ ## reg ## _write(int i, int j, uint32_t val) \ 342 { \ 343 bus_space_write_4(fdtbus_bs_tag, base, off(i, j), val); \ 344 } 345 346#define WIN_REG_BASE_IDX_WR(pre,reg,off) \ 347 static __inline void \ 348 pre ## _ ## reg ## _write(uint32_t base, int i, uint32_t val) \ 349 { \ 350 bus_space_write_4(fdtbus_bs_tag, base, off(i), val); \ 351 } 352 353#define WIN_REG_BASE_IDX_WR2(pre,reg,off) \ 354 static __inline void \ 355 pre ## _ ## reg ## _write(uint32_t base, int i, int j, uint32_t val) \ 356 { \ 357 bus_space_write_4(fdtbus_bs_tag, base, off(i, j), val); \ 358 } 359 360#define WIN_REG_RD(pre,reg,off,base) \ 361 static __inline uint32_t \ 362 pre ## _ ## reg ## _read(void) \ 363 { \ 364 return (bus_space_read_4(fdtbus_bs_tag, base, off)); \ 365 } 366 367#define WIN_REG_BASE_RD(pre,reg,off) \ 368 static __inline uint32_t \ 369 pre ## _ ## reg ## _read(uint32_t base) \ 370 { \ 371 return (bus_space_read_4(fdtbus_bs_tag, base, off)); \ 372 } 373 374#define WIN_REG_WR(pre,reg,off,base) \ 375 static __inline void \ 376 pre ## _ ## reg ## _write(uint32_t val) \ 377 { \ 378 bus_space_write_4(fdtbus_bs_tag, base, off, val); \ 379 } 380 381#define WIN_REG_BASE_WR(pre,reg,off) \ 382 static __inline void \ 383 pre ## _ ## reg ## _write(uint32_t base, uint32_t val) \ 384 { \ 385 bus_space_write_4(fdtbus_bs_tag, base, off, val); \ 386 } 387 388#endif /* _MVWIN_H_ */ 389