mvwin.h revision 239277
1/*- 2 * Copyright (C) 2007-2011 MARVELL INTERNATIONAL LTD. 3 * All rights reserved. 4 * 5 * Developed by Semihalf. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. Neither the name of MARVELL nor the names of contributors 16 * may be used to endorse or promote products derived from this software 17 * without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 * $FreeBSD: head/sys/arm/mv/mvwin.h 239277 2012-08-15 05:15:49Z gonzo $ 32 */ 33 34#ifndef _MVWIN_H_ 35#define _MVWIN_H_ 36 37/* 38 * Decode windows addresses. 39 * 40 * All decoding windows must be aligned to their size, which has to be 41 * a power of 2. 42 */ 43 44/* 45 * SoC Integrated devices: 0xF1000000, 16 MB (VA == PA) 46 */ 47 48/* SoC Regs */ 49#define MV_PHYS_BASE 0xF1000000 50#define MV_SIZE (1024 * 1024) /* 1 MB */ 51 52/* SRAM */ 53#define MV_CESA_SRAM_BASE 0xF1100000 54 55/* AXI Regs */ 56#ifdef SOC_MV_DOVE 57#define MV_AXI_PHYS_BASE 0xF1800000 58#define MV_AXI_BASE MV_AXI_PHYS_BASE 59#define MV_AXI_SIZE (16 * 1024 * 1024) /* 16 MB */ 60#endif 61 62/* 63 * External devices: 0x80000000, 1 GB (VA == PA) 64 * Includes Device Bus, PCI and PCIE. 65 */ 66#if defined(SOC_MV_ORION) 67#define MV_PCI_PORTS 2 /* 1x PCI + 1x PCIE */ 68#elif defined(SOC_MV_KIRKWOOD) || defined(SOC_MV_FREY) 69#define MV_PCI_PORTS 1 /* 1x PCIE */ 70#elif defined(SOC_MV_DISCOVERY) 71#define MV_PCI_PORTS 8 /* 8x PCIE */ 72#elif defined(SOC_MV_DOVE) || defined(SOC_MV_LOKIPLUS) 73#define MV_PCI_PORTS 2 /* 2x PCIE */ 74#elif defined(SOC_MV_ARMADAXP) 75#define MV_PCI_PORTS 3 /* 3x PCIE */ 76#else 77#error "MV_PCI_PORTS not configured !" 78#endif 79 80/* PCI/PCIE Memory */ 81#define MV_PCI_MEM_PHYS_BASE 0x80000000 82#define MV_PCI_MEM_SIZE (512 * 1024 * 1024) /* 512 MB */ 83#define MV_PCI_MEM_BASE MV_PCI_MEM_PHYS_BASE 84#define MV_PCI_MEM_SLICE_SIZE (MV_PCI_MEM_SIZE / MV_PCI_PORTS) 85#define MV_PCI_MEM_SLICE(n) (MV_PCI_MEM_BASE + ((n) * \ 86 MV_PCI_MEM_SLICE_SIZE)) 87/* PCI/PCIE I/O */ 88#define MV_PCI_IO_PHYS_BASE 0xBF000000 89#define MV_PCI_IO_SIZE (16 * 1024 * 1024) /* 16 MB */ 90#define MV_PCI_IO_BASE MV_PCI_IO_PHYS_BASE 91#define MV_PCI_IO_SLICE_SIZE (MV_PCI_IO_SIZE / MV_PCI_PORTS) 92#define MV_PCI_IO_SLICE(n) (MV_PCI_IO_BASE + ((n) * MV_PCI_IO_SLICE_SIZE)) 93 94#if defined(SOC_MV_FREY) 95#define MV_PCI_VA_MEM_BASE MV_PCI_MEM_BASE 96#else 97#define MV_PCI_VA_MEM_BASE 0 98#endif 99#define MV_PCI_VA_IO_BASE 0 100 101/* 102 * Device Bus (VA == PA) 103 */ 104#define MV_DEV_BOOT_BASE 0xF9300000 105#define MV_DEV_BOOT_SIZE (1024 * 1024) /* 1 MB */ 106 107#define MV_DEV_CS0_BASE 0xF9400000 108#define MV_DEV_CS0_SIZE (1024 * 1024) /* 1 MB */ 109 110#define MV_DEV_CS1_BASE 0xF9500000 111#define MV_DEV_CS1_SIZE (32 * 1024 * 1024) /* 32 MB */ 112 113#define MV_DEV_CS2_BASE 0xFB500000 114#define MV_DEV_CS2_SIZE (1024 * 1024) /* 1 MB */ 115 116 117/* 118 * Integrated SoC peripherals addresses 119 */ 120#define MV_BASE MV_PHYS_BASE /* VA == PA mapping */ 121#if defined(SOC_MV_DOVE) 122#define MV_DDR_CADR_BASE (MV_AXI_BASE + 0x100) 123#elif defined(SOC_MV_LOKIPLUS) 124#define MV_DDR_CADR_BASE (MV_BASE + 0xF1500) 125#else 126#define MV_DDR_CADR_BASE (MV_BASE + 0x1500) 127#endif 128#define MV_MPP_BASE (MV_BASE + 0x10000) 129 130#if defined(SOC_MV_ARMADAXP) 131#define MV_MBUS_BRIDGE_BASE (MV_BASE + 0x20000) 132#define MV_INTREGS_BASE (MV_MBUS_BRIDGE_BASE + 0x80) 133#define MV_CPU_CONTROL_BASE (MV_MBUS_BRIDGE_BASE + 0x1800) 134#elif !defined(SOC_MV_FREY) 135#define MV_MBUS_BRIDGE_BASE (MV_BASE + 0x20000) 136#define MV_INTREGS_BASE (MV_MBUS_BRIDGE_BASE + 0x80) 137#define MV_CPU_CONTROL_BASE (MV_MBUS_BRIDGE_BASE + 0x100) 138#else 139#define MV_CPU_CONTROL_BASE (MV_BASE + 0x10000) 140#endif 141 142#define MV_PCI_BASE (MV_BASE + 0x30000) 143#define MV_PCI_SIZE 0x2000 144 145#if defined(SOC_MV_FREY) 146#define MV_PCIE_BASE (MV_BASE + 0x8000) 147#else 148#define MV_PCIE_BASE (MV_BASE + 0x40000) 149#endif 150#define MV_PCIE_SIZE 0x2000 151 152#define MV_PCIE00_BASE (MV_PCIE_BASE + 0x00000) 153#define MV_PCIE01_BASE (MV_PCIE_BASE + 0x04000) 154#define MV_PCIE02_BASE (MV_PCIE_BASE + 0x08000) 155#define MV_PCIE03_BASE (MV_PCIE_BASE + 0x0C000) 156#define MV_PCIE10_BASE (MV_PCIE_BASE + 0x40000) 157#define MV_PCIE11_BASE (MV_PCIE_BASE + 0x44000) 158#define MV_PCIE12_BASE (MV_PCIE_BASE + 0x48000) 159#define MV_PCIE13_BASE (MV_PCIE_BASE + 0x4C000) 160 161#define MV_SDIO_BASE (MV_BASE + 0x90000) 162#define MV_SDIO_SIZE 0x10000 163 164/* 165 * Decode windows definitions and macros 166 */ 167#if defined(SOC_MV_ARMADAXP) 168#define MV_WIN_CPU_CTRL(n) (((n) < 8) ? 0x10 * (n) : 0x90 + (0x8 * ((n) - 8))) 169#define MV_WIN_CPU_BASE(n) ((((n) < 8) ? 0x10 * (n) : 0x90 + (0x8 * ((n) - 8))) + 0x4) 170#define MV_WIN_CPU_REMAP_LO(n) (0x10 * (n) + 0x008) 171#define MV_WIN_CPU_REMAP_HI(n) (0x10 * (n) + 0x00C) 172#else 173#define MV_WIN_CPU_CTRL(n) (0x10 * (n) + (((n) < 8) ? 0x000 : 0x880)) 174#define MV_WIN_CPU_BASE(n) (0x10 * (n) + (((n) < 8) ? 0x004 : 0x884)) 175#define MV_WIN_CPU_REMAP_LO(n) (0x10 * (n) + (((n) < 8) ? 0x008 : 0x888)) 176#define MV_WIN_CPU_REMAP_HI(n) (0x10 * (n) + (((n) < 8) ? 0x00C : 0x88C)) 177#endif 178 179#if defined(SOC_MV_DISCOVERY) 180#define MV_WIN_CPU_MAX 14 181#elif defined(SOC_MV_ARMADAXP) 182#define MV_WIN_CPU_MAX 20 183#else 184#define MV_WIN_CPU_MAX 8 185#endif 186 187#define MV_WIN_CPU_ATTR_SHIFT 8 188#if defined(SOC_MV_LOKIPLUS) 189#define MV_WIN_CPU_TARGET_SHIFT 0 190#define MV_WIN_CPU_ENABLE_BIT (1 << 5) 191#else 192#define MV_WIN_CPU_TARGET_SHIFT 4 193#define MV_WIN_CPU_ENABLE_BIT 1 194#endif 195 196#if defined(SOC_MV_DOVE) 197#define MV_WIN_DDR_MAX 2 198#else /* SOC_MV_DOVE */ 199#if defined(SOC_MV_LOKIPLUS) 200#define MV_WIN_DDR_BASE(n) (0xc * (n) + 0x4) 201#define MV_WIN_DDR_SIZE(n) (0xc * (n) + 0x0) 202#else /* SOC_MV_LOKIPLUS */ 203#define MV_WIN_DDR_BASE(n) (0x8 * (n) + 0x0) 204#define MV_WIN_DDR_SIZE(n) (0x8 * (n) + 0x4) 205#endif /* SOC_MV_LOKIPLUS */ 206#define MV_WIN_DDR_MAX 4 207#endif /* SOC_MV_DOVE */ 208 209#define MV_WIN_CESA_CTRL(n) (0x8 * (n) + 0xa04) 210#define MV_WIN_CESA_BASE(n) (0x8 * (n) + 0xa00) 211#define MV_WIN_CESA_MAX 4 212 213#if defined(SOC_MV_DISCOVERY) 214#define MV_WIN_CESA_TARGET 9 215#define MV_WIN_CESA_ATTR 1 216#else 217#define MV_WIN_CESA_TARGET 3 218#define MV_WIN_CESA_ATTR 0 219#endif 220 221#define MV_WIN_USB_CTRL(n) (0x10 * (n) + 0x320) 222#define MV_WIN_USB_BASE(n) (0x10 * (n) + 0x324) 223#define MV_WIN_USB_MAX 4 224 225#define MV_WIN_ETH_BASE(n) (0x8 * (n) + 0x200) 226#define MV_WIN_ETH_SIZE(n) (0x8 * (n) + 0x204) 227#define MV_WIN_ETH_REMAP(n) (0x4 * (n) + 0x280) 228#define MV_WIN_ETH_MAX 6 229 230#define MV_WIN_IDMA_BASE(n) (0x8 * (n) + 0xa00) 231#define MV_WIN_IDMA_SIZE(n) (0x8 * (n) + 0xa04) 232#define MV_WIN_IDMA_REMAP(n) (0x4 * (n) + 0xa60) 233#define MV_WIN_IDMA_CAP(n) (0x4 * (n) + 0xa70) 234#define MV_WIN_IDMA_MAX 8 235#define MV_IDMA_CHAN_MAX 4 236 237#define MV_WIN_XOR_BASE(n, m) (0x4 * (n) + 0xa50 + (m) * 0x100) 238#define MV_WIN_XOR_SIZE(n, m) (0x4 * (n) + 0xa70 + (m) * 0x100) 239#define MV_WIN_XOR_REMAP(n, m) (0x4 * (n) + 0xa90 + (m) * 0x100) 240#define MV_WIN_XOR_CTRL(n, m) (0x4 * (n) + 0xa40 + (m) * 0x100) 241#define MV_WIN_XOR_OVERR(n, m) (0x4 * (n) + 0xaa0 + (m) * 0x100) 242#define MV_WIN_XOR_MAX 8 243#define MV_XOR_CHAN_MAX 2 244#define MV_XOR_NON_REMAP 4 245 246#if defined(SOC_MV_DISCOVERY) || defined(SOC_MV_KIRKWOOD) || defined(SOC_MV_DOVE) 247#define MV_WIN_PCIE_TARGET(n) 4 248#define MV_WIN_PCIE_MEM_ATTR(n) 0xE8 249#define MV_WIN_PCIE_IO_ATTR(n) 0xE0 250#elif defined(SOC_MV_ARMADAXP) 251#define MV_WIN_PCIE_TARGET(n) (4 + (4 * ((n) % 2))) 252#define MV_WIN_PCIE_MEM_ATTR(n) (0xE8 + (0x10 * ((n) / 2))) 253#define MV_WIN_PCIE_IO_ATTR(n) (0xE0 + (0x10 * ((n) / 2))) 254#elif defined(SOC_MV_ORION) 255#define MV_WIN_PCIE_TARGET(n) 4 256#define MV_WIN_PCIE_MEM_ATTR(n) 0x59 257#define MV_WIN_PCIE_IO_ATTR(n) 0x51 258#define MV_WIN_PCI_TARGET 3 259#define MV_WIN_PCI_MEM_ATTR 0x59 260#define MV_WIN_PCI_IO_ATTR 0x51 261#elif defined(SOC_MV_LOKIPLUS) 262#define MV_WIN_PCIE_TARGET(n) (3 + (n)) 263#define MV_WIN_PCIE_MEM_ATTR(n) 0x59 264#define MV_WIN_PCIE_IO_ATTR(n) 0x51 265#endif 266 267#define MV_WIN_PCIE_CTRL(n) (0x10 * (((n) < 5) ? (n) : \ 268 (n) + 1) + 0x1820) 269#define MV_WIN_PCIE_BASE(n) (0x10 * (((n) < 5) ? (n) : \ 270 (n) + 1) + 0x1824) 271#define MV_WIN_PCIE_REMAP(n) (0x10 * (((n) < 5) ? (n) : \ 272 (n) + 1) + 0x182C) 273#define MV_WIN_PCIE_MAX 6 274 275#define MV_PCIE_BAR_CTRL(n) (0x04 * (n) + 0x1800) 276#define MV_PCIE_BAR_BASE(n) (0x08 * ((n) < 3 ? (n) : 4) + 0x0010) 277#define MV_PCIE_BAR_BASE_H(n) (0x08 * (n) + 0x0014) 278#define MV_PCIE_BAR_MAX 4 279#define MV_PCIE_BAR_64BIT (0x4) 280#define MV_PCIE_BAR_PREFETCH_EN (0x8) 281 282#define MV_PCIE_CONTROL (0x1a00) 283#define MV_PCIE_ROOT_CMPLX (1 << 1) 284 285#define MV_WIN_SATA_CTRL(n) (0x10 * (n) + 0x30) 286#define MV_WIN_SATA_BASE(n) (0x10 * (n) + 0x34) 287#define MV_WIN_SATA_MAX 4 288 289#define WIN_REG_IDX_RD(pre,reg,off,base) \ 290 static __inline uint32_t \ 291 pre ## _ ## reg ## _read(int i) \ 292 { \ 293 return (bus_space_read_4(fdtbus_bs_tag, base, off(i))); \ 294 } 295 296#define WIN_REG_IDX_RD2(pre,reg,off,base) \ 297 static __inline uint32_t \ 298 pre ## _ ## reg ## _read(int i, int j) \ 299 { \ 300 return (bus_space_read_4(fdtbus_bs_tag, base, off(i, j))); \ 301 } \ 302 303#define WIN_REG_BASE_IDX_RD(pre,reg,off) \ 304 static __inline uint32_t \ 305 pre ## _ ## reg ## _read(uint32_t base, int i) \ 306 { \ 307 return (bus_space_read_4(fdtbus_bs_tag, base, off(i))); \ 308 } 309 310#define WIN_REG_BASE_IDX_RD2(pre,reg,off) \ 311 static __inline uint32_t \ 312 pre ## _ ## reg ## _read(uint32_t base, int i, int j) \ 313 { \ 314 return (bus_space_read_4(fdtbus_bs_tag, base, off(i, j))); \ 315 } 316 317#define WIN_REG_IDX_WR(pre,reg,off,base) \ 318 static __inline void \ 319 pre ## _ ## reg ## _write(int i, uint32_t val) \ 320 { \ 321 bus_space_write_4(fdtbus_bs_tag, base, off(i), val); \ 322 } 323 324#define WIN_REG_IDX_WR2(pre,reg,off,base) \ 325 static __inline void \ 326 pre ## _ ## reg ## _write(int i, int j, uint32_t val) \ 327 { \ 328 bus_space_write_4(fdtbus_bs_tag, base, off(i, j), val); \ 329 } 330 331#define WIN_REG_BASE_IDX_WR(pre,reg,off) \ 332 static __inline void \ 333 pre ## _ ## reg ## _write(uint32_t base, int i, uint32_t val) \ 334 { \ 335 bus_space_write_4(fdtbus_bs_tag, base, off(i), val); \ 336 } 337 338#define WIN_REG_BASE_IDX_WR2(pre,reg,off) \ 339 static __inline void \ 340 pre ## _ ## reg ## _write(uint32_t base, int i, int j, uint32_t val) \ 341 { \ 342 bus_space_write_4(fdtbus_bs_tag, base, off(i, j), val); \ 343 } 344 345#define WIN_REG_RD(pre,reg,off,base) \ 346 static __inline uint32_t \ 347 pre ## _ ## reg ## _read(void) \ 348 { \ 349 return (bus_space_read_4(fdtbus_bs_tag, base, off)); \ 350 } 351 352#define WIN_REG_BASE_RD(pre,reg,off) \ 353 static __inline uint32_t \ 354 pre ## _ ## reg ## _read(uint32_t base) \ 355 { \ 356 return (bus_space_read_4(fdtbus_bs_tag, base, off)); \ 357 } 358 359#define WIN_REG_WR(pre,reg,off,base) \ 360 static __inline void \ 361 pre ## _ ## reg ## _write(uint32_t val) \ 362 { \ 363 bus_space_write_4(fdtbus_bs_tag, base, off, val); \ 364 } 365 366#define WIN_REG_BASE_WR(pre,reg,off) \ 367 static __inline void \ 368 pre ## _ ## reg ## _write(uint32_t base, uint32_t val) \ 369 { \ 370 bus_space_write_4(fdtbus_bs_tag, base, off, val); \ 371 } 372 373#endif /* _MVWIN_H_ */ 374