mvwin.h revision 194949
1/*- 2 * Copyright (C) 2007-2008 MARVELL INTERNATIONAL LTD. 3 * All rights reserved. 4 * 5 * Developed by Semihalf. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. Neither the name of MARVELL nor the names of contributors 16 * may be used to endorse or promote products derived from this software 17 * without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 * $FreeBSD: head/sys/arm/mv/mvwin.h 194949 2009-06-25 10:03:51Z raj $ 32 */ 33 34#ifndef _MVWIN_H_ 35#define _MVWIN_H_ 36 37/* 38 * Physical addresses of integrated SoC peripherals 39 */ 40#define MV_PHYS_BASE 0xF1000000 41#define MV_SIZE 0x100000 42 43/* 44 * Decode windows addresses (physical) 45 */ 46#define MV_PCIE_IO_PHYS_BASE (MV_PHYS_BASE + MV_SIZE) 47#define MV_PCIE_IO_BASE MV_PCIE_IO_PHYS_BASE 48#define MV_PCIE_IO_SIZE (1024 * 1024) 49#define MV_PCI_IO_PHYS_BASE (MV_PCIE_IO_PHYS_BASE + MV_PCIE_IO_SIZE) 50#define MV_PCI_IO_BASE MV_PCI_IO_PHYS_BASE 51#define MV_PCI_IO_SIZE (1024 * 1024) 52 53#define MV_PCIE_MEM_PHYS_BASE (MV_PCI_IO_PHYS_BASE + MV_PCI_IO_SIZE) 54#define MV_PCIE_MEM_BASE MV_PCIE_MEM_PHYS_BASE 55#define MV_PCIE_MEM_SIZE (64 * 1024 * 1024) 56#define MV_PCI_MEM_PHYS_BASE (MV_PCIE_MEM_PHYS_BASE + MV_PCIE_MEM_SIZE) 57#define MV_PCI_MEM_BASE MV_PCI_MEM_PHYS_BASE 58#define MV_PCI_MEM_SIZE (64 * 1024 * 1024) 59 60/* XXX DEV_BOOT, CSx are board specific, should be defined per platform */ 61 62/* 512KB NOR FLASH */ 63#define MV_DEV_BOOT_PHYS_BASE (MV_PCI_MEM_PHYS_BASE + MV_PCI_MEM_SIZE) 64#define MV_DEV_BOOT_SIZE (512 * 1024) 65/* CS0: 7-seg LED */ 66#define MV_DEV_CS0_PHYS_BASE 0xFA000000 67#define MV_DEV_CS0_SIZE (1024 * 1024) /* XXX u-boot has 2MB */ 68/* CS1: 32MB NOR FLASH */ 69#define MV_DEV_CS1_PHYS_BASE (MV_DEV_CS0_PHYS_BASE + MV_DEV_CS0_SIZE) 70#define MV_DEV_CS1_SIZE (32 * 1024 * 1024) 71/* CS2: 32MB NAND FLASH */ 72#define MV_DEV_CS2_PHYS_BASE (MV_DEV_CS1_PHYS_BASE + MV_DEV_CS1_SIZE) 73#define MV_DEV_CS2_SIZE 1024 /* XXX u-boot has 1MB */ 74 75#define MV_CESA_SRAM_PHYS_BASE 0xFD000000 76#define MV_CESA_SRAM_BASE MV_CESA_SRAM_PHYS_BASE /* VA == PA mapping */ 77#define MV_CESA_SRAM_SIZE (1024 * 1024) 78 79/* XXX this is probably not robust against wraparounds... */ 80#if ((MV_CESA_SRAM_PHYS_BASE + MV_CESA_SRAM_SIZE) > 0xFFFEFFFF) 81#error Devices memory layout overlaps reset vectors range! 82#endif 83 84/* 85 * Integrated SoC peripherals addresses 86 */ 87#define MV_BASE MV_PHYS_BASE /* VA == PA mapping */ 88#define MV_DDR_CADR_BASE (MV_BASE + 0x1500) 89#define MV_MPP_BASE (MV_BASE + 0x10000) 90#define MV_GPIO_BASE (MV_BASE + 0x10100) 91#define MV_GPIO_SIZE 0x20 92#define MV_RTC_BASE (MV_BASE + 0x10300) 93#define MV_RTC_SIZE 0x08 94#define MV_TWSI0_BASE (MV_BASE + 0x11000) 95#define MV_TWSI1_BASE (MV_BASE + 0x11100) 96#define MV_TWSI_SIZE 0x20 97#define MV_UART0_BASE (MV_BASE + 0x12000) 98#define MV_UART1_BASE (MV_BASE + 0x12100) 99#define MV_UART_SIZE 0x20 100#define MV_MBUS_BRIDGE_BASE (MV_BASE + 0x20000) 101#define MV_INTREGS_BASE (MV_MBUS_BRIDGE_BASE + 0x80) 102#define MV_CPU_CONTROL_BASE (MV_MBUS_BRIDGE_BASE + 0x100) 103#define MV_IC_BASE (MV_MBUS_BRIDGE_BASE + 0x200) 104#define MV_IC_SIZE 0x3C 105#define MV_TIMERS_BASE (MV_MBUS_BRIDGE_BASE + 0x300) 106#define MV_TIMERS_SIZE 0x30 107#define MV_PCI_BASE (MV_BASE + 0x30000) 108#define MV_PCI_SIZE 0x2000 109#if defined (SOC_MV_KIRKWOOD) 110#define MV_CESA_BASE (MV_BASE + 0x30000) /* CESA,PCI don't coexist */ 111#elif defined (SOC_MV_ORION) || defined(SOC_MV_DISCOVERY) 112#define MV_CESA_BASE (MV_BASE + 0x90000) 113#endif 114#define MV_CESA_SIZE 0x10000 115#define MV_PCIE_BASE (MV_BASE + 0x40000) 116#define MV_PCIE_SIZE 0x2000 117 118#define MV_PCIE00_BASE (MV_PCIE_BASE + 0x00000) 119#define MV_PCIE01_BASE (MV_PCIE_BASE + 0x04000) 120#define MV_PCIE02_BASE (MV_PCIE_BASE + 0x08000) 121#define MV_PCIE03_BASE (MV_PCIE_BASE + 0x0C000) 122#define MV_PCIE10_BASE (MV_PCIE_BASE + 0x40000) 123#define MV_PCIE11_BASE (MV_PCIE_BASE + 0x44000) 124#define MV_PCIE12_BASE (MV_PCIE_BASE + 0x48000) 125#define MV_PCIE13_BASE (MV_PCIE_BASE + 0x4C000) 126 127#define MV_USB0_BASE (MV_BASE + 0x50000) 128#define MV_USB1_BASE (MV_USB0_BASE + 0x1000) 129#define MV_USB2_BASE (MV_USB0_BASE + 0x2000) 130#define MV_USB_SIZE 0x1000 131#define MV_USB_AWR_BASE (MV_USB0_BASE + 0x320) 132#define MV_IDMA_BASE (MV_BASE + 0x60000) 133#define MV_IDMA_SIZE 0x1000 134#define MV_XOR_BASE (MV_BASE + 0x60000) 135#define MV_XOR_SIZE 0x1000 136#define MV_ETH0_BASE (MV_BASE + 0x72000) 137#define MV_ETH1_BASE (MV_BASE + 0x76000) 138#define MV_ETH_SIZE 0x2000 139#if defined(SOC_MV_ORION) || defined(SOC_MV_KIRKWOOD) 140#define MV_SATAHC_BASE (MV_BASE + 0x80000) 141#define MV_SATAHC_SIZE 0x6000 142#elif defined(SOC_MV_DISCOVERY) 143#define MV_SATAHC_BASE (MV_BASE + 0xA0000) 144#define MV_SATAHC_SIZE 0x6000 145#endif 146 147#define MV_DEV_CS0_BASE MV_DEV_CS0_PHYS_BASE 148 149/* 150 * Decode windows definitions and macros 151 */ 152#define MV_WIN_CPU_CTRL(n) (0x10 * (n) + (((n) < 8) ? 0x000 : 0x880)) 153#define MV_WIN_CPU_BASE(n) (0x10 * (n) + (((n) < 8) ? 0x004 : 0x884)) 154#define MV_WIN_CPU_REMAP_LO(n) (0x10 * (n) + (((n) < 8) ? 0x008 : 0x888)) 155#define MV_WIN_CPU_REMAP_HI(n) (0x10 * (n) + (((n) < 8) ? 0x00C : 0x88C)) 156#if defined(SOC_MV_DISCOVERY) 157#define MV_WIN_CPU_MAX 14 158#else 159#define MV_WIN_CPU_MAX 8 160#endif 161 162#define MV_WIN_DDR_BASE(n) (0x8 * (n) + 0x0) 163#define MV_WIN_DDR_SIZE(n) (0x8 * (n) + 0x4) 164#define MV_WIN_DDR_MAX 4 165 166#define MV_WIN_CESA_CTRL(n) (0x8 * (n) + 0xa04) 167#define MV_WIN_CESA_BASE(n) (0x8 * (n) + 0xa00) 168#define MV_WIN_CESA_MAX 4 169 170#define MV_WIN_USB_CTRL(n, m) (0x10 * (n) + (m) * 0x1000 + 0x0) 171#define MV_WIN_USB_BASE(n, m) (0x10 * (n) + (m) * 0x1000 + 0x4) 172#define MV_WIN_USB_MAX 4 173 174#define MV_WIN_ETH_BASE(n) (0x8 * (n) + 0x200) 175#define MV_WIN_ETH_SIZE(n) (0x8 * (n) + 0x204) 176#define MV_WIN_ETH_REMAP(n) (0x4 * (n) + 0x280) 177#define MV_WIN_ETH_MAX 6 178 179#define MV_WIN_IDMA_BASE(n) (0x8 * (n) + 0xa00) 180#define MV_WIN_IDMA_SIZE(n) (0x8 * (n) + 0xa04) 181#define MV_WIN_IDMA_REMAP(n) (0x4 * (n) + 0xa60) 182#define MV_WIN_IDMA_CAP(n) (0x4 * (n) + 0xa70) 183#define MV_WIN_IDMA_MAX 8 184#define MV_IDMA_CHAN_MAX 4 185 186#define MV_WIN_XOR_BASE(n, m) (0x4 * (n) + 0xa50 + (m) * 0x100) 187#define MV_WIN_XOR_SIZE(n, m) (0x4 * (n) + 0xa70 + (m) * 0x100) 188#define MV_WIN_XOR_REMAP(n, m) (0x4 * (n) + 0xa90 + (m) * 0x100) 189#define MV_WIN_XOR_CTRL(n, m) (0x4 * (n) + 0xa40 + (m) * 0x100) 190#define MV_WIN_XOR_OVERR(n, m) (0x4 * (n) + 0xaa0 + (m) * 0x100) 191#define MV_WIN_XOR_MAX 8 192#define MV_XOR_CHAN_MAX 2 193#define MV_XOR_NON_REMAP 4 194 195#define MV_WIN_PCIE_CTRL(n) (0x10 * (((n) < 5) ? (n) : \ 196 (n) + 1) + 0x1820) 197#define MV_WIN_PCIE_BASE(n) (0x10 * (((n) < 5) ? (n) : \ 198 (n) + 1) + 0x1824) 199#define MV_WIN_PCIE_REMAP(n) (0x10 * (((n) < 5) ? (n) : \ 200 (n) + 1) + 0x182C) 201#define MV_WIN_PCIE_MAX 6 202 203#define MV_PCIE_BAR(n) (0x04 * (n) + 0x1804) 204#define MV_PCIE_BAR_MAX 3 205 206#define MV_WIN_SATA_CTRL(n) (0x10 * (n) + 0x30) 207#define MV_WIN_SATA_BASE(n) (0x10 * (n) + 0x34) 208#define MV_WIN_SATA_MAX 4 209 210#define WIN_REG_IDX_RD(pre,reg,off,base) \ 211 static __inline uint32_t \ 212 pre ## _ ## reg ## _read(int i) \ 213 { \ 214 return (bus_space_read_4(obio_tag, base, off(i))); \ 215 } 216 217#define WIN_REG_IDX_RD2(pre,reg,off,base) \ 218 static __inline uint32_t \ 219 pre ## _ ## reg ## _read(int i, int j) \ 220 { \ 221 return (bus_space_read_4(obio_tag, base, off(i, j))); \ 222 } \ 223 224#define WIN_REG_BASE_IDX_RD(pre,reg,off) \ 225 static __inline uint32_t \ 226 pre ## _ ## reg ## _read(uint32_t base, int i) \ 227 { \ 228 return (bus_space_read_4(obio_tag, base, off(i))); \ 229 } 230 231#define WIN_REG_IDX_WR(pre,reg,off,base) \ 232 static __inline void \ 233 pre ## _ ## reg ## _write(int i, uint32_t val) \ 234 { \ 235 bus_space_write_4(obio_tag, base, off(i), val); \ 236 } 237 238#define WIN_REG_IDX_WR2(pre,reg,off,base) \ 239 static __inline void \ 240 pre ## _ ## reg ## _write(int i, int j, uint32_t val) \ 241 { \ 242 bus_space_write_4(obio_tag, base, off(i, j), val); \ 243 } 244 245#define WIN_REG_BASE_IDX_WR(pre,reg,off) \ 246 static __inline void \ 247 pre ## _ ## reg ## _write(uint32_t base, int i, uint32_t val) \ 248 { \ 249 bus_space_write_4(obio_tag, base, off(i), val); \ 250 } 251 252#define WIN_REG_RD(pre,reg,off,base) \ 253 static __inline uint32_t \ 254 pre ## _ ## reg ## _read(void) \ 255 { \ 256 return (bus_space_read_4(obio_tag, base, off)); \ 257 } 258 259#define WIN_REG_BASE_RD(pre,reg,off) \ 260 static __inline uint32_t \ 261 pre ## _ ## reg ## _read(uint32_t base) \ 262 { \ 263 return (bus_space_read_4(obio_tag, base, off)); \ 264 } 265 266#define WIN_REG_WR(pre,reg,off,base) \ 267 static __inline void \ 268 pre ## _ ## reg ## _write(uint32_t val) \ 269 { \ 270 bus_space_write_4(obio_tag, base, off, val); \ 271 } 272 273#define WIN_REG_BASE_WR(pre,reg,off) \ 274 static __inline void \ 275 pre ## _ ## reg ## _write(uint32_t base, uint32_t val) \ 276 { \ 277 bus_space_write_4(obio_tag, base, off, val); \ 278 } 279 280#endif /* _MVWIN_H_ */ 281