1/*- 2 * Copyright (c) 2011 Jakub Wojciech Klama <jceel@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 */ 27#include <sys/cdefs.h> 28__FBSDID("$FreeBSD$"); 29 30#include <sys/param.h> 31#include <sys/systm.h> 32#include <sys/bus.h> 33#include <sys/kernel.h> 34#include <sys/module.h> 35#include <sys/malloc.h> 36#include <sys/rman.h> 37#include <sys/timetc.h> 38#include <sys/timeet.h> 39#include <machine/bus.h> 40#include <machine/cpu.h> 41#include <machine/frame.h> 42#include <machine/intr.h> 43 44#include <dev/fdt/fdt_common.h> 45#include <dev/ofw/ofw_bus.h> 46#include <dev/ofw/ofw_bus_subr.h> 47 48#include <arm/lpc/lpcreg.h> 49#include <arm/lpc/lpcvar.h> 50 51struct lpc_timer_softc { 52 device_t lt_dev; 53 struct eventtimer lt_et; 54 struct resource * lt_res[5]; 55 bus_space_tag_t lt_bst0; 56 bus_space_handle_t lt_bsh0; 57 bus_space_tag_t lt_bst1; 58 bus_space_handle_t lt_bsh1; 59 int lt_oneshot; 60 uint32_t lt_period; 61}; 62 63static struct resource_spec lpc_timer_spec[] = { 64 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 65 { SYS_RES_MEMORY, 1, RF_ACTIVE }, 66 { SYS_RES_IRQ, 0, RF_ACTIVE }, 67 { SYS_RES_IRQ, 1, RF_ACTIVE }, 68 { -1, 0 } 69}; 70 71static struct lpc_timer_softc *timer_softc = NULL; 72static int lpc_timer_initialized = 0; 73static int lpc_timer_probe(device_t); 74static int lpc_timer_attach(device_t); 75static int lpc_timer_start(struct eventtimer *, 76 sbintime_t first, sbintime_t period); 77static int lpc_timer_stop(struct eventtimer *et); 78static unsigned lpc_get_timecount(struct timecounter *); 79static int lpc_hardclock(void *); 80 81#define timer0_read_4(sc, reg) \ 82 bus_space_read_4(sc->lt_bst0, sc->lt_bsh0, reg) 83#define timer0_write_4(sc, reg, val) \ 84 bus_space_write_4(sc->lt_bst0, sc->lt_bsh0, reg, val) 85#define timer0_clear(sc) \ 86 do { \ 87 timer0_write_4(sc, LPC_TIMER_TC, 0); \ 88 timer0_write_4(sc, LPC_TIMER_PR, 0); \ 89 timer0_write_4(sc, LPC_TIMER_PC, 0); \ 90 } while(0) 91 92#define timer1_read_4(sc, reg) \ 93 bus_space_read_4(sc->lt_bst1, sc->lt_bsh1, reg) 94#define timer1_write_4(sc, reg, val) \ 95 bus_space_write_4(sc->lt_bst1, sc->lt_bsh1, reg, val) 96#define timer1_clear(sc) \ 97 do { \ 98 timer1_write_4(sc, LPC_TIMER_TC, 0); \ 99 timer1_write_4(sc, LPC_TIMER_PR, 0); \ 100 timer1_write_4(sc, LPC_TIMER_PC, 0); \ 101 } while(0) 102 103static struct timecounter lpc_timecounter = { 104 .tc_get_timecount = lpc_get_timecount, 105 .tc_name = "LPC32x0 Timer1", 106 .tc_frequency = 0, /* will be filled later */ 107 .tc_counter_mask = ~0u, 108 .tc_quality = 1000, 109}; 110 111static int 112lpc_timer_probe(device_t dev) 113{ 114 115 if (!ofw_bus_is_compatible(dev, "lpc,timer")) 116 return (ENXIO); 117 118 device_set_desc(dev, "LPC32x0 timer"); 119 return (BUS_PROBE_DEFAULT); 120} 121 122static int 123lpc_timer_attach(device_t dev) 124{ 125 void *intrcookie; 126 struct lpc_timer_softc *sc = device_get_softc(dev); 127 phandle_t node; 128 uint32_t freq; 129 130 if (timer_softc) 131 return (ENXIO); 132 133 timer_softc = sc; 134 135 if (bus_alloc_resources(dev, lpc_timer_spec, sc->lt_res)) { 136 device_printf(dev, "could not allocate resources\n"); 137 return (ENXIO); 138 } 139 140 sc->lt_bst0 = rman_get_bustag(sc->lt_res[0]); 141 sc->lt_bsh0 = rman_get_bushandle(sc->lt_res[0]); 142 sc->lt_bst1 = rman_get_bustag(sc->lt_res[1]); 143 sc->lt_bsh1 = rman_get_bushandle(sc->lt_res[1]); 144 145 if (bus_setup_intr(dev, sc->lt_res[2], INTR_TYPE_CLK, 146 lpc_hardclock, NULL, sc, &intrcookie)) { 147 device_printf(dev, "could not setup interrupt handler\n"); 148 bus_release_resources(dev, lpc_timer_spec, sc->lt_res); 149 return (ENXIO); 150 } 151 152 /* Enable timer clock */ 153 lpc_pwr_write(dev, LPC_CLKPWR_TIMCLK_CTRL1, 154 LPC_CLKPWR_TIMCLK_CTRL1_TIMER0 | 155 LPC_CLKPWR_TIMCLK_CTRL1_TIMER1); 156 157 /* Get PERIPH_CLK encoded in parent bus 'bus-frequency' property */ 158 node = ofw_bus_get_node(dev); 159 if (OF_getprop(OF_parent(node), "bus-frequency", &freq, 160 sizeof(pcell_t)) <= 0) { 161 bus_release_resources(dev, lpc_timer_spec, sc->lt_res); 162 bus_teardown_intr(dev, sc->lt_res[2], intrcookie); 163 device_printf(dev, "could not obtain base clock frequency\n"); 164 return (ENXIO); 165 } 166 167 freq = fdt32_to_cpu(freq); 168 169 /* Set desired frequency in event timer and timecounter */ 170 sc->lt_et.et_frequency = (uint64_t)freq; 171 lpc_timecounter.tc_frequency = (uint64_t)freq; 172 173 sc->lt_et.et_name = "LPC32x0 Timer0"; 174 sc->lt_et.et_flags = ET_FLAGS_PERIODIC | ET_FLAGS_ONESHOT; 175 sc->lt_et.et_quality = 1000; 176 sc->lt_et.et_min_period = (0x00000002LLU << 32) / sc->lt_et.et_frequency; 177 sc->lt_et.et_max_period = (0xfffffffeLLU << 32) / sc->lt_et.et_frequency; 178 sc->lt_et.et_start = lpc_timer_start; 179 sc->lt_et.et_stop = lpc_timer_stop; 180 sc->lt_et.et_priv = sc; 181 182 et_register(&sc->lt_et); 183 tc_init(&lpc_timecounter); 184 185 /* Reset and enable timecounter */ 186 timer1_write_4(sc, LPC_TIMER_TCR, LPC_TIMER_TCR_RESET); 187 timer1_write_4(sc, LPC_TIMER_TCR, 0); 188 timer1_clear(sc); 189 timer1_write_4(sc, LPC_TIMER_TCR, LPC_TIMER_TCR_ENABLE); 190 191 /* DELAY() now can work properly */ 192 lpc_timer_initialized = 1; 193 194 return (0); 195} 196 197static int 198lpc_timer_start(struct eventtimer *et, sbintime_t first, sbintime_t period) 199{ 200 struct lpc_timer_softc *sc = (struct lpc_timer_softc *)et->et_priv; 201 uint32_t ticks; 202 203 if (period == 0) { 204 sc->lt_oneshot = 1; 205 sc->lt_period = 0; 206 } else { 207 sc->lt_oneshot = 0; 208 sc->lt_period = ((uint32_t)et->et_frequency * period) >> 32; 209 } 210 211 if (first == 0) 212 ticks = sc->lt_period; 213 else 214 ticks = ((uint32_t)et->et_frequency * first) >> 32; 215 216 /* Reset timer */ 217 timer0_write_4(sc, LPC_TIMER_TCR, LPC_TIMER_TCR_RESET); 218 timer0_write_4(sc, LPC_TIMER_TCR, 0); 219 220 /* Start timer */ 221 timer0_clear(sc); 222 timer0_write_4(sc, LPC_TIMER_MR0, ticks); 223 timer0_write_4(sc, LPC_TIMER_MCR, LPC_TIMER_MCR_MR0I | LPC_TIMER_MCR_MR0S); 224 timer0_write_4(sc, LPC_TIMER_TCR, LPC_TIMER_TCR_ENABLE); 225 return (0); 226} 227 228static int 229lpc_timer_stop(struct eventtimer *et) 230{ 231 struct lpc_timer_softc *sc = (struct lpc_timer_softc *)et->et_priv; 232 233 timer0_write_4(sc, LPC_TIMER_TCR, 0); 234 return (0); 235} 236 237static device_method_t lpc_timer_methods[] = { 238 DEVMETHOD(device_probe, lpc_timer_probe), 239 DEVMETHOD(device_attach, lpc_timer_attach), 240 { 0, 0 } 241}; 242 243static driver_t lpc_timer_driver = { 244 "timer", 245 lpc_timer_methods, 246 sizeof(struct lpc_timer_softc), 247}; 248 249static devclass_t lpc_timer_devclass; 250 251DRIVER_MODULE(timer, simplebus, lpc_timer_driver, lpc_timer_devclass, 0, 0); 252 253static int 254lpc_hardclock(void *arg) 255{ 256 struct lpc_timer_softc *sc = (struct lpc_timer_softc *)arg; 257 258 /* Reset pending interrupt */ 259 timer0_write_4(sc, LPC_TIMER_IR, 0xffffffff); 260 261 /* Start timer again */ 262 if (!sc->lt_oneshot) { 263 timer0_clear(sc); 264 timer0_write_4(sc, LPC_TIMER_MR0, sc->lt_period); 265 timer0_write_4(sc, LPC_TIMER_TCR, LPC_TIMER_TCR_ENABLE); 266 } 267 268 if (sc->lt_et.et_active) 269 sc->lt_et.et_event_cb(&sc->lt_et, sc->lt_et.et_arg); 270 271 return (FILTER_HANDLED); 272} 273 274static unsigned 275lpc_get_timecount(struct timecounter *tc) 276{ 277 return timer1_read_4(timer_softc, LPC_TIMER_TC); 278} 279 280void 281cpu_initclocks(void) 282{ 283 cpu_initclocks_bsp(); 284} 285 286void 287DELAY(int usec) 288{ 289 uint32_t counter; 290 uint32_t first, last; 291 int val = (lpc_timecounter.tc_frequency / 1000000 + 1) * usec; 292 293 /* Timer is not initialized yet */ 294 if (!lpc_timer_initialized) { 295 for (; usec > 0; usec--) 296 for (counter = 100; counter > 0; counter--) 297 ; 298 return; 299 } 300 301 first = lpc_get_timecount(&lpc_timecounter); 302 while (val > 0) { 303 last = lpc_get_timecount(&lpc_timecounter); 304 if (last < first) { 305 /* Timer rolled over */ 306 last = first; 307 } 308 309 val -= (last - first); 310 first = last; 311 } 312} 313