imx51_ccmreg.h revision 250357
1210284Sjmallett/* $NetBSD: imx51_ccmreg.h,v 1.1 2012/04/17 09:33:31 bsh Exp $ */ 2232812Sjmallett/* 3215990Sjmallett * Copyright (c) 2011, 2012 Genetec Corporation. All rights reserved. 4210284Sjmallett * Written by Hashimoto Kenichi for Genetec Corporation. 5210284Sjmallett * 6215990Sjmallett * Redistribution and use in source and binary forms, with or without 7215990Sjmallett * modification, are permitted provided that the following conditions 8215990Sjmallett * are met: 9210284Sjmallett * 1. Redistributions of source code must retain the above copyright 10215990Sjmallett * notice, this list of conditions and the following disclaimer. 11215990Sjmallett * 2. Redistributions in binary form must reproduce the above copyright 12210284Sjmallett * notice, this list of conditions and the following disclaimer in the 13215990Sjmallett * documentation and/or other materials provided with the distribution. 14215990Sjmallett * 15215990Sjmallett * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND 16215990Sjmallett * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 17215990Sjmallett * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 18232812Sjmallett * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION 19215990Sjmallett * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20215990Sjmallett * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21215990Sjmallett * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22215990Sjmallett * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23215990Sjmallett * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24215990Sjmallett * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25215990Sjmallett * POSSIBILITY OF SUCH DAMAGE. 26215990Sjmallett */ 27215990Sjmallett 28215990Sjmallett/*- 29232812Sjmallett * Copyright (c) 2012, 2013 The FreeBSD Foundation 30215990Sjmallett * All rights reserved. 31215990Sjmallett * 32215990Sjmallett * Portions of this software were developed by Oleksandr Rybalko 33215990Sjmallett * under sponsorship from the FreeBSD Foundation. 34215990Sjmallett * 35215990Sjmallett * Redistribution and use in source and binary forms, with or without 36215990Sjmallett * modification, are permitted provided that the following conditions 37215990Sjmallett * are met: 38210284Sjmallett * 1. Redistributions of source code must retain the above copyright 39210284Sjmallett * notice, this list of conditions and the following disclaimer. 40210284Sjmallett * 2. Redistributions in binary form must reproduce the above copyright 41210284Sjmallett * notice, this list of conditions and the following disclaimer in the 42210284Sjmallett * documentation and/or other materials provided with the distribution. 43210284Sjmallett * 44215990Sjmallett * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 45210284Sjmallett * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 46210284Sjmallett * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 47210284Sjmallett * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 48210284Sjmallett * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 49210284Sjmallett * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 50232812Sjmallett * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 51210284Sjmallett * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 52210284Sjmallett * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 53210284Sjmallett * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 54210284Sjmallett * SUCH DAMAGE. 55210284Sjmallett * 56210284Sjmallett * $FreeBSD: head/sys/arm/freescale/imx/imx51_ccmreg.h 250357 2013-05-08 09:42:50Z ray $ 57210284Sjmallett */ 58210284Sjmallett 59210284Sjmallett#ifndef _IMX51_CCMREG_H 60210284Sjmallett#define _IMX51_CCMREG_H 61210284Sjmallett 62210284Sjmallett#include <sys/cdefs.h> 63210284Sjmallett 64210284Sjmallett/* register offset address */ 65210284Sjmallett 66210284Sjmallett#define CCMC_BASE 0x73fd4000 67210284Sjmallett#define CCMC_CCR 0x0000 68210284Sjmallett#define CCR_FPM_MULT 0x00001000 69232812Sjmallett#define CCMC_CCDR 0x0004 70232812Sjmallett#define CCMC_CSR 0x0008 71232812Sjmallett#define CCMC_CCSR 0x000c 72232812Sjmallett#define CCSR_LP_APM 0x00000200 73232812Sjmallett#define CCSR_STEP_SEL_SHIFT 7 74232812Sjmallett#define CCSR_STEP_SEL_MASK 0x00000180 75232812Sjmallett#define CCSR_PLL2_DIV_PODF_SHIFT 5 76232812Sjmallett#define CCSR_PLL2_DIV_PODF_MASK 0x00000060 77210284Sjmallett#define CCSR_PLL3_DIV_PODF_SHIFT 3 78210284Sjmallett#define CCSR_PLL3_DIV_PODF_MASK 0x00000030 79210284Sjmallett#define CCSR_PLL1_SW_CLK_SEL 0x00000004 80210284Sjmallett#define CCSR_PLL2_SW_CLK_SEL 0x00000002 81210284Sjmallett#define CCSR_PLL3_SW_CLK_SEL 0x00000001 82210284Sjmallett#define CCMC_CACRR 0x0010 83210284Sjmallett#define CCMC_CBCDR 0x0014 84210284Sjmallett#define CBCDR_DDR_HIGH_FREQ_CLK_SEL 0x40000000 85210284Sjmallett#define CBCDR_DDR_CLK_PODF_SHIFT 27 86210284Sjmallett#define CBCDR_DDR_CLK_PODF_MASK 0x38000000 87210284Sjmallett#define CBCDR_EMI_CLK_SEL 0x04000000 88210284Sjmallett#define CBCDR_PERIPH_CLK_SEL 0x02000000 89210284Sjmallett#define CBCDR_EMI_SLOW_PODF_SHIFT 22 90210284Sjmallett#define CBCDR_EMI_SLOW_PODF_MASK 0x01c00000 91210284Sjmallett#define CBCDR_AXI_B_PODF_SHIFT 19 92210284Sjmallett#define CBCDR_AXI_B_PODF_MASK 0x00380000 93210284Sjmallett#define CBCDR_AXI_A_PODF_SHIFT 16 94210284Sjmallett#define CBCDR_AXI_A_PODF_MASK 0x1fff0000 95210284Sjmallett#define CBCDR_NFC_PODF_SHIFT 13 96210284Sjmallett#define CBCDR_NFC_PODF_MASK 0x00018000 97210284Sjmallett#define CBCDR_AHB_PODF_SHIFT 10 98210284Sjmallett#define CBCDR_AHB_PODF_MASK 0x00001c00 99210284Sjmallett#define CBCDR_IPG_PODF_SHIFT 8 100210284Sjmallett#define CBCDR_IPG_PODF_MASK 0x00000300 101210284Sjmallett#define CBCDR_PERCLK_PRED1_SHIFT 6 102215990Sjmallett#define CBCDR_PERCLK_PRED1_MASK 0x000000c0 103210284Sjmallett#define CBCDR_PERCLK_PRED2_SHIFT 3 104210284Sjmallett#define CBCDR_PERCLK_PRED2_MASK 0x00000038 105210284Sjmallett#define CBCDR_PERCLK_PODF_SHIFT 0 106210284Sjmallett#define CBCDR_PERCLK_PODF_MASK 0x00000007 107215990Sjmallett#define CCMC_CBCMR 0x0018 108210284Sjmallett#define CBCMR_PERIPH_APM_SEL_SHIFT 12 109215990Sjmallett#define CBCMR_PERIPH_APM_SEL_MASK 0x00003000 110210284Sjmallett#define CBCMR_IPU_HSP_CLK_SEL_SHIFT 6 111210284Sjmallett#define CBCMR_IPU_HSP_CLK_SEL_MASK 0x000000c0 112210284Sjmallett#define CBCMR_PERCLK_LP_APM_SEL 0x00000002 113210284Sjmallett#define CBCMR_PERCLK_IPG_SEL 0x00000001 114210284Sjmallett#define CCMC_CSCMR1 0x001c 115210284Sjmallett#define CSCMR1_UART_CLK_SEL_SHIFT 24 116210284Sjmallett#define CSCMR1_UART_CLK_SEL_MASK 0x03000000 117210284Sjmallett#define CCMC_CSCMR2 0x0020 118210284Sjmallett#define CCMC_CSCDR1 0x0024 119210284Sjmallett#define CSCDR1_UART_CLK_PRED_SHIFT 3 120210284Sjmallett#define CSCDR1_UART_CLK_PRED_MASK 0x00000038 121210284Sjmallett#define CSCDR1_UART_CLK_PODF_SHIFT 0 122210284Sjmallett#define CSCDR1_UART_CLK_PODF_MASK 0x00000007 123210284Sjmallett#define CCMC_CS1CDR 0x0028 124210284Sjmallett#define CCMC_CS2CDR 0x002c 125210284Sjmallett#define CCMC_CDCDR 0x0030 126210284Sjmallett#define CCMC_CSCDR2 0x0038 127210284Sjmallett#define CCMC_CSCDR3 0x003c 128210284Sjmallett#define CCMC_CSCDR4 0x0040 129210284Sjmallett#define CCMC_CWDR 0x0044 130210284Sjmallett#define CCMC_CDHIPR 0x0048 131210284Sjmallett#define CCMC_CDCR 0x004c 132210284Sjmallett#define CDCR_PERIPH_CLK_DVFS_PODF_SHIFT 0 133210284Sjmallett#define CDCR_PERIPH_CLK_DVFS_PODF_MASK 0x00000003 134210284Sjmallett#define CCMC_CTOR 0x0050 135210284Sjmallett#define CCMC_CLPCR 0x0054 136210284Sjmallett#define CCMC_CISR 0x0058 137210284Sjmallett#define CCMC_CIMR 0x005c 138210284Sjmallett#define CCMC_CCOSR 0x0060 139210284Sjmallett#define CCMC_CGPR 0x0064 140215990Sjmallett#define CCMC_CCGR(n) (0x0068 + (n) * 4) 141210284Sjmallett#define CCMC_CMEOR 0x0084 142210284Sjmallett 143215990Sjmallett#define CCMC_SIZE 0x88 144210284Sjmallett 145210284Sjmallett/* CCGR Clock Gate Register */ 146210284Sjmallett 147210284Sjmallett#define CCMR_CCGR_NSOURCE 16 148210284Sjmallett#define CCMR_CCGR_NGROUPS 7 149210284Sjmallett#define CCMR_CCGR_MODULE(clk) ((clk) / CCMR_CCGR_NSOURCE) 150210284Sjmallett#define __CCGR_NUM(a, b) ((a) * 16 + (b)) 151210284Sjmallett 152210284Sjmallett#define CCGR_ARM_BUS_CLK __CCGR_NUM(0, 0) 153210284Sjmallett#define CCGR_ARM_AXI_CLK __CCGR_NUM(0, 1) 154210284Sjmallett#define CCGR_ARM_DEBUG_CLK __CCGR_NUM(0, 2) 155210284Sjmallett#define CCGR_TZIC_CLK __CCGR_NUM(0, 3) 156210284Sjmallett#define CCGR_DAP_CLK __CCGR_NUM(0, 4) 157210284Sjmallett#define CCGR_TPIU_CLK __CCGR_NUM(0, 5) 158210284Sjmallett#define CCGR_CTI2_CLK __CCGR_NUM(0, 6) 159210284Sjmallett#define CCGR_CTI3_CLK __CCGR_NUM(0, 7) 160210284Sjmallett#define CCGR_AHBMUX1_CLK __CCGR_NUM(0, 8) 161210284Sjmallett#define CCGR_AHBMUX2_CLK __CCGR_NUM(0, 9) 162210284Sjmallett#define CCGR_ROMCP_CLK __CCGR_NUM(0, 10) 163210284Sjmallett#define CCGR_ROM_CLK __CCGR_NUM(0, 11) 164210284Sjmallett#define CCGR_AIPS_TZ1_CLK __CCGR_NUM(0, 12) 165210284Sjmallett#define CCGR_AIPS_TZ2_CLK __CCGR_NUM(0, 13) 166210284Sjmallett#define CCGR_AHB_MAX_CLK __CCGR_NUM(0, 14) 167210284Sjmallett#define CCGR_IIM_CLK __CCGR_NUM(0, 15) 168210284Sjmallett#define CCGR_TMAX1_CLK __CCGR_NUM(1, 0) 169210284Sjmallett#define CCGR_TMAX2_CLK __CCGR_NUM(1, 1) 170210284Sjmallett#define CCGR_TMAX3_CLK __CCGR_NUM(1, 2) 171210284Sjmallett#define CCGR_UART1_CLK __CCGR_NUM(1, 3) 172210284Sjmallett#define CCGR_UART1_SERIAL_CLK __CCGR_NUM(1, 4) 173232812Sjmallett#define CCGR_UART2_CLK __CCGR_NUM(1, 5) 174232812Sjmallett#define CCGR_UART2_SERIAL_CLK __CCGR_NUM(1, 6) 175232812Sjmallett#define CCGR_UART3_CLK __CCGR_NUM(1, 7) 176232812Sjmallett#define CCGR_UART3_SERIAL_CLK __CCGR_NUM(1, 8) 177232812Sjmallett#define CCGR_I2C1_SERIAL_CLK __CCGR_NUM(1, 9) 178232812Sjmallett#define CCGR_I2C2_SERIAL_CLK __CCGR_NUM(1, 10) 179232812Sjmallett#define CCGR_HSI2C_CLK __CCGR_NUM(1, 11) 180232812Sjmallett#define CCGR_HSI2C_SERIAL_CLK __CCGR_NUM(1, 12) 181232812Sjmallett#define CCGR_FIRI_CLK __CCGR_NUM(1, 13) 182232812Sjmallett#define CCGR_FIRI_SERIAL_CLK __CCGR_NUM(1, 14) 183232812Sjmallett#define CCGR_SCC_CLK __CCGR_NUM(1, 15) 184232812Sjmallett 185232812Sjmallett#define CCGR_USB_PHY_CLK __CCGR_NUM(2, 0) 186232812Sjmallett#define CCGR_EPIT1_CLK __CCGR_NUM(2, 1) 187232812Sjmallett#define CCGR_EPIT1_SERIAL_CLK __CCGR_NUM(2, 2) 188210284Sjmallett#define CCGR_EPIT2_CLK __CCGR_NUM(2, 3) 189210284Sjmallett#define CCGR_EPIT2_SERIAL_CLK __CCGR_NUM(2, 4) 190210284Sjmallett#define CCGR_PWM1_CLK __CCGR_NUM(2, 5) 191210284Sjmallett#define CCGR_PWM1_SERIAL_CLK __CCGR_NUM(2, 6) 192210284Sjmallett#define CCGR_PWM2_CLK __CCGR_NUM(2, 7) 193210284Sjmallett#define CCGR_PWM2_SERIAL_CLK __CCGR_NUM(2, 8) 194210284Sjmallett#define CCGR_GPT_CLK __CCGR_NUM(2, 9) 195210284Sjmallett#define CCGR_GPT_SERIAL_CLK __CCGR_NUM(2, 10) 196210284Sjmallett#define CCGR_OWIRE_CLK __CCGR_NUM(2, 11) 197210284Sjmallett#define CCGR_FEC_CLK __CCGR_NUM(2, 12) 198210284Sjmallett#define CCGR_USBOH3_IPG_AHB_CLK __CCGR_NUM(2, 13) 199210284Sjmallett#define CCGR_USBOH3_60M_CLK __CCGR_NUM(2, 14) 200210284Sjmallett#define CCGR_TVE_CLK __CCGR_NUM(2, 15) 201210284Sjmallett 202210284Sjmallett#define CCGR_ESDHC1_CLK __CCGR_NUM(3, 0) 203210284Sjmallett#define CCGR_ESDHC1_SERIAL_CLK __CCGR_NUM(3, 1) 204210284Sjmallett#define CCGR_ESDHC2_CLK __CCGR_NUM(3, 2) 205210284Sjmallett#define CCGR_ESDHC2_SERIAL_CLK __CCGR_NUM(3, 3) 206210284Sjmallett#define CCGR_ESDHC3_CLK __CCGR_NUM(3, 4) 207210284Sjmallett#define CCGR_ESDHC3_SERIAL_CLK __CCGR_NUM(3, 5) 208210284Sjmallett#define CCGR_ESDHC4_CLK __CCGR_NUM(3, 6) 209210284Sjmallett#define CCGR_ESDHC4_SERIAL_CLK __CCGR_NUM(3, 7) 210210284Sjmallett#define CCGR_SSI1_CLK __CCGR_NUM(3, 8) 211210284Sjmallett#define CCGR_SSI1_SERIAL_CLK __CCGR_NUM(3, 9) 212210284Sjmallett#define CCGR_SSI2_CLK __CCGR_NUM(3, 10) 213210284Sjmallett#define CCGR_SSI2_SERIAL_CLK __CCGR_NUM(3, 11) 214210284Sjmallett#define CCGR_SSI3_CLK __CCGR_NUM(3, 12) 215210284Sjmallett#define CCGR_SSI3_SERIAL_CLK __CCGR_NUM(3, 13) 216210284Sjmallett#define CCGR_SSI_EXT1_CLK __CCGR_NUM(3, 14) 217210284Sjmallett#define CCGR_SSI_EXT2_CLK __CCGR_NUM(3, 15) 218215990Sjmallett 219210284Sjmallett#define CCGR_PATA_CLK __CCGR_NUM(4, 0) 220232812Sjmallett#define CCGR_SIM_CLK __CCGR_NUM(4, 1) 221232812Sjmallett#define CCGR_SIM_SERIAL_CLK __CCGR_NUM(4, 2) 222232812Sjmallett#define CCGR_SAHARA_CLK __CCGR_NUM(4, 3) 223232812Sjmallett#define CCGR_RTIC_CLK __CCGR_NUM(4, 4) 224232812Sjmallett#define CCGR_ECSPI1_CLK __CCGR_NUM(4, 5) 225232812Sjmallett#define CCGR_ECSPI1_SERIAL_CLK __CCGR_NUM(4, 6) 226232812Sjmallett#define CCGR_ECSPI2_CLK __CCGR_NUM(4, 7) 227232812Sjmallett#define CCGR_ECSPI2_SERIAL_CLK __CCGR_NUM(4, 8) 228232812Sjmallett#define CCGR_CSPI_CLK __CCGR_NUM(4, 9) 229232812Sjmallett#define CCGR_SRTC_CLK __CCGR_NUM(4, 10) 230232812Sjmallett#define CCGR_SDMA_CLK __CCGR_NUM(4, 11) 231232812Sjmallett 232232812Sjmallett#define CCGR_SPBA_CLK __CCGR_NUM(5, 0) 233232812Sjmallett#define CCGR_GPU_CLK __CCGR_NUM(5, 1) 234210284Sjmallett#define CCGR_GARB_CLK __CCGR_NUM(5, 2) 235210284Sjmallett#define CCGR_VPU_CLK __CCGR_NUM(5, 3) 236232812Sjmallett#define CCGR_VPU_SERIAL_CLK __CCGR_NUM(5, 4) 237210284Sjmallett#define CCGR_IPU_CLK __CCGR_NUM(5, 5) 238210284Sjmallett#define CCGR_EMI_GARB_CLK __CCGR_NUM(6, 0) 239210284Sjmallett#define CCGR_IPU_DI0_CLK __CCGR_NUM(6, 1) 240210284Sjmallett#define CCGR_IPU_DI1_CLK __CCGR_NUM(6, 2) 241210284Sjmallett#define CCGR_GPU2D_CLK __CCGR_NUM(6, 3) 242210284Sjmallett#define CCGR_SLIMBUS_CLK __CCGR_NUM(6, 4) 243210284Sjmallett#define CCGR_SLIMBUS_SERIAL_CLK __CCGR_NUM(6, 5) 244210284Sjmallett 245210284Sjmallett#define CCGR_CLK_MODE_OFF 0 246210284Sjmallett#define CCGR_CLK_MODE_RUNMODE 1 247210284Sjmallett#define CCGR_CLK_MODE_ALWAYS 3 248210284Sjmallett 249210284Sjmallett#endif /* _IMX51_CCMREG_H */ 250215990Sjmallett 251210284Sjmallett