1155324Simp/*- 2155324Simp * Copyright (c) 2006 M. Warner Losh. All rights reserved. 3155324Simp * 4155324Simp * Redistribution and use in source and binary forms, with or without 5155324Simp * modification, are permitted provided that the following conditions 6155324Simp * are met: 7155324Simp * 1. Redistributions of source code must retain the above copyright 8155324Simp * notice, this list of conditions and the following disclaimer. 9155324Simp * 2. Redistributions in binary form must reproduce the above copyright 10155324Simp * notice, this list of conditions and the following disclaimer in the 11155324Simp * documentation and/or other materials provided with the distribution. 12155324Simp * 13185265Simp * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 14185265Simp * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15185265Simp * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16185265Simp * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17185265Simp * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18185265Simp * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19185265Simp * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20185265Simp * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21185265Simp * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22185265Simp * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23185265Simp * SUCH DAMAGE. 24155324Simp */ 25155324Simp 26155324Simp/* $FreeBSD$ */ 27155324Simp 28155324Simp#ifndef ARM_AT91_AT91_TWIREG_H 29234281Smarius#define ARM_AT91_AT91_TWIREG_H 30155324Simp 31234281Smarius#define TWI_CR 0x00 /* TWI Control Register */ 32234281Smarius#define TWI_MMR 0x04 /* TWI Master Mode Register */ 33234281Smarius#define TWI_SMR 0x08 /* TWI Master Mode Register */ 34234281Smarius#define TWI_IADR 0x0c /* TWI Internal Address Register */ 35234281Smarius#define TWI_CWGR 0x10 /* TWI Clock Waveform Generator Reg */ 36155324Simp /* 0x14 reserved */ 37155324Simp /* 0x18 reserved */ 38155324Simp /* 0x1c reserved */ 39234281Smarius#define TWI_SR 0x20 /* TWI Status Register */ 40234281Smarius#define TWI_IER 0x24 /* TWI Interrupt Enable Register */ 41234281Smarius#define TWI_IDR 0x28 /* TWI Interrupt Disable Register */ 42234281Smarius#define TWI_IMR 0x2c /* TWI Interrupt Mask Register */ 43234281Smarius#define TWI_RHR 0x30 /* TWI Receiver Holding Register */ 44234281Smarius#define TWI_THR 0x34 /* TWI Transmit Holding Register */ 45155324Simp 46155324Simp/* TWI_CR */ 47234281Smarius#define TWI_CR_START (1U << 0) /* Send a start */ 48234281Smarius#define TWI_CR_STOP (1U << 1) /* Send a stop */ 49234281Smarius#define TWI_CR_MSEN (1U << 2) /* Master Transfer Enable */ 50234281Smarius#define TWI_CR_MSDIS (1U << 3) /* Master Transfer Disable */ 51234281Smarius#define TWI_CR_SVEN (1U << 4) /* Slave Transfer Enable */ 52234281Smarius#define TWI_CR_SVDIS (1U << 5) /* Slave Transfer Disable */ 53234281Smarius#define TWI_CR_SWRST (1U << 7) /* Software Reset */ 54155324Simp 55155324Simp/* TWI_MMR */ 56155324Simp/* TWI_SMR */ 57234281Smarius#define TWI_MMR_IADRSZ(n) ((n) << 8) /* Set size of transfer */ 58234281Smarius#define TWI_MMR_MWRITE 0U /* Master Read Direction */ 59234281Smarius#define TWI_MMR_MREAD (1U << 12) /* Master Read Direction */ 60234281Smarius#define TWI_MMR_DADR(n) ((n) << 15) /* Device Address */ 61155324Simp 62155324Simp/* TWI_CWGR */ 63234281Smarius#define TWI_CWGR_CKDIV(x) ((x) << 16) /* Clock Divider */ 64234281Smarius#define TWI_CWGR_CHDIV(x) ((x) << 8) /* Clock High Divider */ 65234281Smarius#define TWI_CWGR_CLDIV(x) ((x) << 0) /* Clock Low Divider */ 66234281Smarius#define TWI_CWGR_DIV(rate) \ 67234291Smarius (at91_is_sam9() || at91_is_sam9xe() ? \ 68234281Smarius ((at91_master_clock / (4 * (rate))) - 3) : \ 69234281Smarius ((at91_master_clock / (4 * (rate))) - 2)) 70155324Simp 71155324Simp/* TWI_SR */ 72155324Simp/* TWI_IER */ 73155324Simp/* TWI_IDR */ 74155324Simp/* TWI_IMR */ 75234281Smarius#define TWI_SR_TXCOMP (1U << 0) /* Transmission Completed */ 76234281Smarius#define TWI_SR_RXRDY (1U << 1) /* Receive Holding Register Ready */ 77234281Smarius#define TWI_SR_TXRDY (1U << 2) /* Transmit Holding Register Ready */ 78234281Smarius#define TWI_SR_SVREAD (1U << 3) /* Slave Read */ 79234281Smarius#define TWI_SR_SVACC (1U << 4) /* Slave Access */ 80234281Smarius#define TWI_SR_GCACC (1U << 5) /* General Call Access */ 81234281Smarius#define TWI_SR_OVRE (1U << 6) /* Overrun error */ 82234281Smarius#define TWI_SR_UNRE (1U << 7) /* Underrun Error */ 83234281Smarius#define TWI_SR_NACK (1U << 8) /* Not Acknowledged */ 84234281Smarius#define TWI_SR_ARBLST (1U << 9) /* Arbitration Lost */ 85155324Simp 86155324Simp#endif /* ARM_AT91_AT91_TWIREG_H */ 87