1219820Sjeff/* 2219820Sjeff * Copyright (c) 2005 Topspin Communications. All rights reserved. 3219820Sjeff * 4219820Sjeff * This software is available to you under a choice of one of two 5219820Sjeff * licenses. You may choose to be licensed under the terms of the GNU 6219820Sjeff * General Public License (GPL) Version 2, available from the file 7219820Sjeff * COPYING in the main directory of this source tree, or the 8219820Sjeff * OpenIB.org BSD license below: 9219820Sjeff * 10219820Sjeff * Redistribution and use in source and binary forms, with or 11219820Sjeff * without modification, are permitted provided that the following 12219820Sjeff * conditions are met: 13219820Sjeff * 14219820Sjeff * - Redistributions of source code must retain the above 15219820Sjeff * copyright notice, this list of conditions and the following 16219820Sjeff * disclaimer. 17219820Sjeff * 18219820Sjeff * - Redistributions in binary form must reproduce the above 19219820Sjeff * copyright notice, this list of conditions and the following 20219820Sjeff * disclaimer in the documentation and/or other materials 21219820Sjeff * provided with the distribution. 22219820Sjeff * 23219820Sjeff * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24219820Sjeff * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25219820Sjeff * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26219820Sjeff * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27219820Sjeff * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28219820Sjeff * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29219820Sjeff * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30219820Sjeff * SOFTWARE. 31219820Sjeff */ 32219820Sjeff 33219820Sjeff#ifndef INFINIBAND_ARCH_H 34219820Sjeff#define INFINIBAND_ARCH_H 35219820Sjeff 36219820Sjeff#include <stdint.h> 37219820Sjeff#include <infiniband/endian.h> 38219820Sjeff#include <infiniband/byteswap.h> 39219820Sjeff 40219820Sjeff#if __BYTE_ORDER == __LITTLE_ENDIAN 41219820Sjeffstatic inline uint64_t htonll(uint64_t x) { return bswap_64(x); } 42219820Sjeffstatic inline uint64_t ntohll(uint64_t x) { return bswap_64(x); } 43219820Sjeff#elif __BYTE_ORDER == __BIG_ENDIAN 44219820Sjeffstatic inline uint64_t htonll(uint64_t x) { return x; } 45219820Sjeffstatic inline uint64_t ntohll(uint64_t x) { return x; } 46219820Sjeff#else 47219820Sjeff#error __BYTE_ORDER is neither __LITTLE_ENDIAN nor __BIG_ENDIAN 48219820Sjeff#endif 49219820Sjeff 50219820Sjeff/* 51219820Sjeff * Architecture-specific defines. Currently, an architecture is 52219820Sjeff * required to implement the following operations: 53219820Sjeff * 54219820Sjeff * mb() - memory barrier. No loads or stores may be reordered across 55219820Sjeff * this macro by either the compiler or the CPU. 56219820Sjeff * rmb() - read memory barrier. No loads may be reordered across this 57219820Sjeff * macro by either the compiler or the CPU. 58219820Sjeff * wmb() - write memory barrier. No stores may be reordered across 59219820Sjeff * this macro by either the compiler or the CPU. 60219820Sjeff * wc_wmb() - flush write combine buffers. No write-combined writes 61219820Sjeff * will be reordered across this macro by either the compiler or 62219820Sjeff * the CPU. 63219820Sjeff */ 64219820Sjeff 65219820Sjeff#if defined(__i386__) 66219820Sjeff 67219820Sjeff#define mb() asm volatile("lock; addl $0,0(%%esp) " ::: "memory") 68219820Sjeff#define rmb() mb() 69219820Sjeff#define wmb() asm volatile("" ::: "memory") 70219820Sjeff#define wc_wmb() mb() 71219820Sjeff 72219820Sjeff#elif defined(__x86_64__) 73219820Sjeff 74219820Sjeff/* 75219820Sjeff * Only use lfence for mb() and rmb() because we don't care about 76219820Sjeff * ordering against non-temporal stores (for now at least). 77219820Sjeff */ 78219820Sjeff#define mb() asm volatile("lfence" ::: "memory") 79219820Sjeff#define rmb() mb() 80219820Sjeff#define wmb() asm volatile("" ::: "memory") 81219820Sjeff#define wc_wmb() asm volatile("sfence" ::: "memory") 82219820Sjeff 83219820Sjeff#elif defined(__PPC64__) 84219820Sjeff 85219820Sjeff#define mb() asm volatile("sync" ::: "memory") 86219820Sjeff#define rmb() asm volatile("lwsync" ::: "memory") 87219820Sjeff#define wmb() mb() 88219820Sjeff#define wc_wmb() wmb() 89219820Sjeff 90219820Sjeff#elif defined(__ia64__) 91219820Sjeff 92219820Sjeff#define mb() asm volatile("mf" ::: "memory") 93219820Sjeff#define rmb() mb() 94219820Sjeff#define wmb() mb() 95219820Sjeff#define wc_wmb() asm volatile("fwb" ::: "memory") 96219820Sjeff 97219820Sjeff#elif defined(__PPC__) 98219820Sjeff 99219820Sjeff#define mb() asm volatile("sync" ::: "memory") 100219820Sjeff#define rmb() mb() 101219820Sjeff#define wmb() mb() 102219820Sjeff#define wc_wmb() wmb() 103219820Sjeff 104219820Sjeff#elif defined(__sparc_v9__) 105219820Sjeff 106219820Sjeff#define mb() asm volatile("membar #LoadLoad | #LoadStore | #StoreStore | #StoreLoad" ::: "memory") 107219820Sjeff#define rmb() asm volatile("membar #LoadLoad" ::: "memory") 108219820Sjeff#define wmb() asm volatile("membar #StoreStore" ::: "memory") 109219820Sjeff#define wc_wmb() wmb() 110219820Sjeff 111219820Sjeff#elif defined(__sparc__) 112219820Sjeff 113219820Sjeff#define mb() asm volatile("" ::: "memory") 114219820Sjeff#define rmb() mb() 115219820Sjeff#define wmb() mb() 116219820Sjeff#define wc_wmb() wmb() 117219820Sjeff 118219820Sjeff#else 119219820Sjeff 120219820Sjeff#warning No architecture specific defines found. Using generic implementation. 121219820Sjeff 122219820Sjeff#define mb() asm volatile("" ::: "memory") 123219820Sjeff#define rmb() mb() 124219820Sjeff#define wmb() mb() 125219820Sjeff#define wc_wmb() wmb() 126219820Sjeff 127219820Sjeff#endif 128219820Sjeff 129219820Sjeff#endif /* INFINIBAND_ARCH_H */ 130