SubtargetEmitter.cpp revision 249423
1//===- SubtargetEmitter.cpp - Generate subtarget enumerations -------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This tablegen backend emits subtarget enumerations. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "subtarget-emitter" 15 16#include "CodeGenTarget.h" 17#include "CodeGenSchedule.h" 18#include "llvm/ADT/STLExtras.h" 19#include "llvm/ADT/StringExtras.h" 20#include "llvm/MC/MCInstrItineraries.h" 21#include "llvm/Support/Debug.h" 22#include "llvm/Support/Format.h" 23#include "llvm/TableGen/Error.h" 24#include "llvm/TableGen/Record.h" 25#include "llvm/TableGen/TableGenBackend.h" 26#include <algorithm> 27#include <map> 28#include <string> 29#include <vector> 30using namespace llvm; 31 32namespace { 33class SubtargetEmitter { 34 // Each processor has a SchedClassDesc table with an entry for each SchedClass. 35 // The SchedClassDesc table indexes into a global write resource table, write 36 // latency table, and read advance table. 37 struct SchedClassTables { 38 std::vector<std::vector<MCSchedClassDesc> > ProcSchedClasses; 39 std::vector<MCWriteProcResEntry> WriteProcResources; 40 std::vector<MCWriteLatencyEntry> WriteLatencies; 41 std::vector<std::string> WriterNames; 42 std::vector<MCReadAdvanceEntry> ReadAdvanceEntries; 43 44 // Reserve an invalid entry at index 0 45 SchedClassTables() { 46 ProcSchedClasses.resize(1); 47 WriteProcResources.resize(1); 48 WriteLatencies.resize(1); 49 WriterNames.push_back("InvalidWrite"); 50 ReadAdvanceEntries.resize(1); 51 } 52 }; 53 54 struct LessWriteProcResources { 55 bool operator()(const MCWriteProcResEntry &LHS, 56 const MCWriteProcResEntry &RHS) { 57 return LHS.ProcResourceIdx < RHS.ProcResourceIdx; 58 } 59 }; 60 61 RecordKeeper &Records; 62 CodeGenSchedModels &SchedModels; 63 std::string Target; 64 65 void Enumeration(raw_ostream &OS, const char *ClassName, bool isBits); 66 unsigned FeatureKeyValues(raw_ostream &OS); 67 unsigned CPUKeyValues(raw_ostream &OS); 68 void FormItineraryStageString(const std::string &Names, 69 Record *ItinData, std::string &ItinString, 70 unsigned &NStages); 71 void FormItineraryOperandCycleString(Record *ItinData, std::string &ItinString, 72 unsigned &NOperandCycles); 73 void FormItineraryBypassString(const std::string &Names, 74 Record *ItinData, 75 std::string &ItinString, unsigned NOperandCycles); 76 void EmitStageAndOperandCycleData(raw_ostream &OS, 77 std::vector<std::vector<InstrItinerary> > 78 &ProcItinLists); 79 void EmitItineraries(raw_ostream &OS, 80 std::vector<std::vector<InstrItinerary> > 81 &ProcItinLists); 82 void EmitProcessorProp(raw_ostream &OS, const Record *R, const char *Name, 83 char Separator); 84 void EmitProcessorResources(const CodeGenProcModel &ProcModel, 85 raw_ostream &OS); 86 Record *FindWriteResources(const CodeGenSchedRW &SchedWrite, 87 const CodeGenProcModel &ProcModel); 88 Record *FindReadAdvance(const CodeGenSchedRW &SchedRead, 89 const CodeGenProcModel &ProcModel); 90 void ExpandProcResources(RecVec &PRVec, std::vector<int64_t> &Cycles, 91 const CodeGenProcModel &ProcModel); 92 void GenSchedClassTables(const CodeGenProcModel &ProcModel, 93 SchedClassTables &SchedTables); 94 void EmitSchedClassTables(SchedClassTables &SchedTables, raw_ostream &OS); 95 void EmitProcessorModels(raw_ostream &OS); 96 void EmitProcessorLookup(raw_ostream &OS); 97 void EmitSchedModelHelpers(std::string ClassName, raw_ostream &OS); 98 void EmitSchedModel(raw_ostream &OS); 99 void ParseFeaturesFunction(raw_ostream &OS, unsigned NumFeatures, 100 unsigned NumProcs); 101 102public: 103 SubtargetEmitter(RecordKeeper &R, CodeGenTarget &TGT): 104 Records(R), SchedModels(TGT.getSchedModels()), Target(TGT.getName()) {} 105 106 void run(raw_ostream &o); 107 108}; 109} // End anonymous namespace 110 111// 112// Enumeration - Emit the specified class as an enumeration. 113// 114void SubtargetEmitter::Enumeration(raw_ostream &OS, 115 const char *ClassName, 116 bool isBits) { 117 // Get all records of class and sort 118 std::vector<Record*> DefList = Records.getAllDerivedDefinitions(ClassName); 119 std::sort(DefList.begin(), DefList.end(), LessRecord()); 120 121 unsigned N = DefList.size(); 122 if (N == 0) 123 return; 124 if (N > 64) { 125 errs() << "Too many (> 64) subtarget features!\n"; 126 exit(1); 127 } 128 129 OS << "namespace " << Target << " {\n"; 130 131 // For bit flag enumerations with more than 32 items, emit constants. 132 // Emit an enum for everything else. 133 if (isBits && N > 32) { 134 // For each record 135 for (unsigned i = 0; i < N; i++) { 136 // Next record 137 Record *Def = DefList[i]; 138 139 // Get and emit name and expression (1 << i) 140 OS << " const uint64_t " << Def->getName() << " = 1ULL << " << i << ";\n"; 141 } 142 } else { 143 // Open enumeration 144 OS << "enum {\n"; 145 146 // For each record 147 for (unsigned i = 0; i < N;) { 148 // Next record 149 Record *Def = DefList[i]; 150 151 // Get and emit name 152 OS << " " << Def->getName(); 153 154 // If bit flags then emit expression (1 << i) 155 if (isBits) OS << " = " << " 1ULL << " << i; 156 157 // Depending on 'if more in the list' emit comma 158 if (++i < N) OS << ","; 159 160 OS << "\n"; 161 } 162 163 // Close enumeration 164 OS << "};\n"; 165 } 166 167 OS << "}\n"; 168} 169 170// 171// FeatureKeyValues - Emit data of all the subtarget features. Used by the 172// command line. 173// 174unsigned SubtargetEmitter::FeatureKeyValues(raw_ostream &OS) { 175 // Gather and sort all the features 176 std::vector<Record*> FeatureList = 177 Records.getAllDerivedDefinitions("SubtargetFeature"); 178 179 if (FeatureList.empty()) 180 return 0; 181 182 std::sort(FeatureList.begin(), FeatureList.end(), LessRecordFieldName()); 183 184 // Begin feature table 185 OS << "// Sorted (by key) array of values for CPU features.\n" 186 << "extern const llvm::SubtargetFeatureKV " << Target 187 << "FeatureKV[] = {\n"; 188 189 // For each feature 190 unsigned NumFeatures = 0; 191 for (unsigned i = 0, N = FeatureList.size(); i < N; ++i) { 192 // Next feature 193 Record *Feature = FeatureList[i]; 194 195 const std::string &Name = Feature->getName(); 196 const std::string &CommandLineName = Feature->getValueAsString("Name"); 197 const std::string &Desc = Feature->getValueAsString("Desc"); 198 199 if (CommandLineName.empty()) continue; 200 201 // Emit as { "feature", "description", featureEnum, i1 | i2 | ... | in } 202 OS << " { " 203 << "\"" << CommandLineName << "\", " 204 << "\"" << Desc << "\", " 205 << Target << "::" << Name << ", "; 206 207 const std::vector<Record*> &ImpliesList = 208 Feature->getValueAsListOfDefs("Implies"); 209 210 if (ImpliesList.empty()) { 211 OS << "0ULL"; 212 } else { 213 for (unsigned j = 0, M = ImpliesList.size(); j < M;) { 214 OS << Target << "::" << ImpliesList[j]->getName(); 215 if (++j < M) OS << " | "; 216 } 217 } 218 219 OS << " }"; 220 ++NumFeatures; 221 222 // Depending on 'if more in the list' emit comma 223 if ((i + 1) < N) OS << ","; 224 225 OS << "\n"; 226 } 227 228 // End feature table 229 OS << "};\n"; 230 231 return NumFeatures; 232} 233 234// 235// CPUKeyValues - Emit data of all the subtarget processors. Used by command 236// line. 237// 238unsigned SubtargetEmitter::CPUKeyValues(raw_ostream &OS) { 239 // Gather and sort processor information 240 std::vector<Record*> ProcessorList = 241 Records.getAllDerivedDefinitions("Processor"); 242 std::sort(ProcessorList.begin(), ProcessorList.end(), LessRecordFieldName()); 243 244 // Begin processor table 245 OS << "// Sorted (by key) array of values for CPU subtype.\n" 246 << "extern const llvm::SubtargetFeatureKV " << Target 247 << "SubTypeKV[] = {\n"; 248 249 // For each processor 250 for (unsigned i = 0, N = ProcessorList.size(); i < N;) { 251 // Next processor 252 Record *Processor = ProcessorList[i]; 253 254 const std::string &Name = Processor->getValueAsString("Name"); 255 const std::vector<Record*> &FeatureList = 256 Processor->getValueAsListOfDefs("Features"); 257 258 // Emit as { "cpu", "description", f1 | f2 | ... fn }, 259 OS << " { " 260 << "\"" << Name << "\", " 261 << "\"Select the " << Name << " processor\", "; 262 263 if (FeatureList.empty()) { 264 OS << "0ULL"; 265 } else { 266 for (unsigned j = 0, M = FeatureList.size(); j < M;) { 267 OS << Target << "::" << FeatureList[j]->getName(); 268 if (++j < M) OS << " | "; 269 } 270 } 271 272 // The "0" is for the "implies" section of this data structure. 273 OS << ", 0ULL }"; 274 275 // Depending on 'if more in the list' emit comma 276 if (++i < N) OS << ","; 277 278 OS << "\n"; 279 } 280 281 // End processor table 282 OS << "};\n"; 283 284 return ProcessorList.size(); 285} 286 287// 288// FormItineraryStageString - Compose a string containing the stage 289// data initialization for the specified itinerary. N is the number 290// of stages. 291// 292void SubtargetEmitter::FormItineraryStageString(const std::string &Name, 293 Record *ItinData, 294 std::string &ItinString, 295 unsigned &NStages) { 296 // Get states list 297 const std::vector<Record*> &StageList = 298 ItinData->getValueAsListOfDefs("Stages"); 299 300 // For each stage 301 unsigned N = NStages = StageList.size(); 302 for (unsigned i = 0; i < N;) { 303 // Next stage 304 const Record *Stage = StageList[i]; 305 306 // Form string as ,{ cycles, u1 | u2 | ... | un, timeinc, kind } 307 int Cycles = Stage->getValueAsInt("Cycles"); 308 ItinString += " { " + itostr(Cycles) + ", "; 309 310 // Get unit list 311 const std::vector<Record*> &UnitList = Stage->getValueAsListOfDefs("Units"); 312 313 // For each unit 314 for (unsigned j = 0, M = UnitList.size(); j < M;) { 315 // Add name and bitwise or 316 ItinString += Name + "FU::" + UnitList[j]->getName(); 317 if (++j < M) ItinString += " | "; 318 } 319 320 int TimeInc = Stage->getValueAsInt("TimeInc"); 321 ItinString += ", " + itostr(TimeInc); 322 323 int Kind = Stage->getValueAsInt("Kind"); 324 ItinString += ", (llvm::InstrStage::ReservationKinds)" + itostr(Kind); 325 326 // Close off stage 327 ItinString += " }"; 328 if (++i < N) ItinString += ", "; 329 } 330} 331 332// 333// FormItineraryOperandCycleString - Compose a string containing the 334// operand cycle initialization for the specified itinerary. N is the 335// number of operands that has cycles specified. 336// 337void SubtargetEmitter::FormItineraryOperandCycleString(Record *ItinData, 338 std::string &ItinString, unsigned &NOperandCycles) { 339 // Get operand cycle list 340 const std::vector<int64_t> &OperandCycleList = 341 ItinData->getValueAsListOfInts("OperandCycles"); 342 343 // For each operand cycle 344 unsigned N = NOperandCycles = OperandCycleList.size(); 345 for (unsigned i = 0; i < N;) { 346 // Next operand cycle 347 const int OCycle = OperandCycleList[i]; 348 349 ItinString += " " + itostr(OCycle); 350 if (++i < N) ItinString += ", "; 351 } 352} 353 354void SubtargetEmitter::FormItineraryBypassString(const std::string &Name, 355 Record *ItinData, 356 std::string &ItinString, 357 unsigned NOperandCycles) { 358 const std::vector<Record*> &BypassList = 359 ItinData->getValueAsListOfDefs("Bypasses"); 360 unsigned N = BypassList.size(); 361 unsigned i = 0; 362 for (; i < N;) { 363 ItinString += Name + "Bypass::" + BypassList[i]->getName(); 364 if (++i < NOperandCycles) ItinString += ", "; 365 } 366 for (; i < NOperandCycles;) { 367 ItinString += " 0"; 368 if (++i < NOperandCycles) ItinString += ", "; 369 } 370} 371 372// 373// EmitStageAndOperandCycleData - Generate unique itinerary stages and operand 374// cycle tables. Create a list of InstrItinerary objects (ProcItinLists) indexed 375// by CodeGenSchedClass::Index. 376// 377void SubtargetEmitter:: 378EmitStageAndOperandCycleData(raw_ostream &OS, 379 std::vector<std::vector<InstrItinerary> > 380 &ProcItinLists) { 381 382 // Multiple processor models may share an itinerary record. Emit it once. 383 SmallPtrSet<Record*, 8> ItinsDefSet; 384 385 // Emit functional units for all the itineraries. 386 for (CodeGenSchedModels::ProcIter PI = SchedModels.procModelBegin(), 387 PE = SchedModels.procModelEnd(); PI != PE; ++PI) { 388 389 if (!ItinsDefSet.insert(PI->ItinsDef)) 390 continue; 391 392 std::vector<Record*> FUs = PI->ItinsDef->getValueAsListOfDefs("FU"); 393 if (FUs.empty()) 394 continue; 395 396 const std::string &Name = PI->ItinsDef->getName(); 397 OS << "\n// Functional units for \"" << Name << "\"\n" 398 << "namespace " << Name << "FU {\n"; 399 400 for (unsigned j = 0, FUN = FUs.size(); j < FUN; ++j) 401 OS << " const unsigned " << FUs[j]->getName() 402 << " = 1 << " << j << ";\n"; 403 404 OS << "}\n"; 405 406 std::vector<Record*> BPs = PI->ItinsDef->getValueAsListOfDefs("BP"); 407 if (BPs.size()) { 408 OS << "\n// Pipeline forwarding pathes for itineraries \"" << Name 409 << "\"\n" << "namespace " << Name << "Bypass {\n"; 410 411 OS << " const unsigned NoBypass = 0;\n"; 412 for (unsigned j = 0, BPN = BPs.size(); j < BPN; ++j) 413 OS << " const unsigned " << BPs[j]->getName() 414 << " = 1 << " << j << ";\n"; 415 416 OS << "}\n"; 417 } 418 } 419 420 // Begin stages table 421 std::string StageTable = "\nextern const llvm::InstrStage " + Target + 422 "Stages[] = {\n"; 423 StageTable += " { 0, 0, 0, llvm::InstrStage::Required }, // No itinerary\n"; 424 425 // Begin operand cycle table 426 std::string OperandCycleTable = "extern const unsigned " + Target + 427 "OperandCycles[] = {\n"; 428 OperandCycleTable += " 0, // No itinerary\n"; 429 430 // Begin pipeline bypass table 431 std::string BypassTable = "extern const unsigned " + Target + 432 "ForwardingPaths[] = {\n"; 433 BypassTable += " 0, // No itinerary\n"; 434 435 // For each Itinerary across all processors, add a unique entry to the stages, 436 // operand cycles, and pipepine bypess tables. Then add the new Itinerary 437 // object with computed offsets to the ProcItinLists result. 438 unsigned StageCount = 1, OperandCycleCount = 1; 439 std::map<std::string, unsigned> ItinStageMap, ItinOperandMap; 440 for (CodeGenSchedModels::ProcIter PI = SchedModels.procModelBegin(), 441 PE = SchedModels.procModelEnd(); PI != PE; ++PI) { 442 const CodeGenProcModel &ProcModel = *PI; 443 444 // Add process itinerary to the list. 445 ProcItinLists.resize(ProcItinLists.size()+1); 446 447 // If this processor defines no itineraries, then leave the itinerary list 448 // empty. 449 std::vector<InstrItinerary> &ItinList = ProcItinLists.back(); 450 if (!ProcModel.hasItineraries()) 451 continue; 452 453 const std::string &Name = ProcModel.ItinsDef->getName(); 454 455 ItinList.resize(SchedModels.numInstrSchedClasses()); 456 assert(ProcModel.ItinDefList.size() == ItinList.size() && "bad Itins"); 457 458 for (unsigned SchedClassIdx = 0, SchedClassEnd = ItinList.size(); 459 SchedClassIdx < SchedClassEnd; ++SchedClassIdx) { 460 461 // Next itinerary data 462 Record *ItinData = ProcModel.ItinDefList[SchedClassIdx]; 463 464 // Get string and stage count 465 std::string ItinStageString; 466 unsigned NStages = 0; 467 if (ItinData) 468 FormItineraryStageString(Name, ItinData, ItinStageString, NStages); 469 470 // Get string and operand cycle count 471 std::string ItinOperandCycleString; 472 unsigned NOperandCycles = 0; 473 std::string ItinBypassString; 474 if (ItinData) { 475 FormItineraryOperandCycleString(ItinData, ItinOperandCycleString, 476 NOperandCycles); 477 478 FormItineraryBypassString(Name, ItinData, ItinBypassString, 479 NOperandCycles); 480 } 481 482 // Check to see if stage already exists and create if it doesn't 483 unsigned FindStage = 0; 484 if (NStages > 0) { 485 FindStage = ItinStageMap[ItinStageString]; 486 if (FindStage == 0) { 487 // Emit as { cycles, u1 | u2 | ... | un, timeinc }, // indices 488 StageTable += ItinStageString + ", // " + itostr(StageCount); 489 if (NStages > 1) 490 StageTable += "-" + itostr(StageCount + NStages - 1); 491 StageTable += "\n"; 492 // Record Itin class number. 493 ItinStageMap[ItinStageString] = FindStage = StageCount; 494 StageCount += NStages; 495 } 496 } 497 498 // Check to see if operand cycle already exists and create if it doesn't 499 unsigned FindOperandCycle = 0; 500 if (NOperandCycles > 0) { 501 std::string ItinOperandString = ItinOperandCycleString+ItinBypassString; 502 FindOperandCycle = ItinOperandMap[ItinOperandString]; 503 if (FindOperandCycle == 0) { 504 // Emit as cycle, // index 505 OperandCycleTable += ItinOperandCycleString + ", // "; 506 std::string OperandIdxComment = itostr(OperandCycleCount); 507 if (NOperandCycles > 1) 508 OperandIdxComment += "-" 509 + itostr(OperandCycleCount + NOperandCycles - 1); 510 OperandCycleTable += OperandIdxComment + "\n"; 511 // Record Itin class number. 512 ItinOperandMap[ItinOperandCycleString] = 513 FindOperandCycle = OperandCycleCount; 514 // Emit as bypass, // index 515 BypassTable += ItinBypassString + ", // " + OperandIdxComment + "\n"; 516 OperandCycleCount += NOperandCycles; 517 } 518 } 519 520 // Set up itinerary as location and location + stage count 521 int NumUOps = ItinData ? ItinData->getValueAsInt("NumMicroOps") : 0; 522 InstrItinerary Intinerary = { NumUOps, FindStage, FindStage + NStages, 523 FindOperandCycle, 524 FindOperandCycle + NOperandCycles}; 525 526 // Inject - empty slots will be 0, 0 527 ItinList[SchedClassIdx] = Intinerary; 528 } 529 } 530 531 // Closing stage 532 StageTable += " { 0, 0, 0, llvm::InstrStage::Required } // End stages\n"; 533 StageTable += "};\n"; 534 535 // Closing operand cycles 536 OperandCycleTable += " 0 // End operand cycles\n"; 537 OperandCycleTable += "};\n"; 538 539 BypassTable += " 0 // End bypass tables\n"; 540 BypassTable += "};\n"; 541 542 // Emit tables. 543 OS << StageTable; 544 OS << OperandCycleTable; 545 OS << BypassTable; 546} 547 548// 549// EmitProcessorData - Generate data for processor itineraries that were 550// computed during EmitStageAndOperandCycleData(). ProcItinLists lists all 551// Itineraries for each processor. The Itinerary lists are indexed on 552// CodeGenSchedClass::Index. 553// 554void SubtargetEmitter:: 555EmitItineraries(raw_ostream &OS, 556 std::vector<std::vector<InstrItinerary> > &ProcItinLists) { 557 558 // Multiple processor models may share an itinerary record. Emit it once. 559 SmallPtrSet<Record*, 8> ItinsDefSet; 560 561 // For each processor's machine model 562 std::vector<std::vector<InstrItinerary> >::iterator 563 ProcItinListsIter = ProcItinLists.begin(); 564 for (CodeGenSchedModels::ProcIter PI = SchedModels.procModelBegin(), 565 PE = SchedModels.procModelEnd(); PI != PE; ++PI, ++ProcItinListsIter) { 566 567 Record *ItinsDef = PI->ItinsDef; 568 if (!ItinsDefSet.insert(ItinsDef)) 569 continue; 570 571 // Get processor itinerary name 572 const std::string &Name = ItinsDef->getName(); 573 574 // Get the itinerary list for the processor. 575 assert(ProcItinListsIter != ProcItinLists.end() && "bad iterator"); 576 std::vector<InstrItinerary> &ItinList = *ProcItinListsIter; 577 578 OS << "\n"; 579 OS << "static const llvm::InstrItinerary "; 580 if (ItinList.empty()) { 581 OS << '*' << Name << " = 0;\n"; 582 continue; 583 } 584 585 // Begin processor itinerary table 586 OS << Name << "[] = {\n"; 587 588 // For each itinerary class in CodeGenSchedClass::Index order. 589 for (unsigned j = 0, M = ItinList.size(); j < M; ++j) { 590 InstrItinerary &Intinerary = ItinList[j]; 591 592 // Emit Itinerary in the form of 593 // { firstStage, lastStage, firstCycle, lastCycle } // index 594 OS << " { " << 595 Intinerary.NumMicroOps << ", " << 596 Intinerary.FirstStage << ", " << 597 Intinerary.LastStage << ", " << 598 Intinerary.FirstOperandCycle << ", " << 599 Intinerary.LastOperandCycle << " }" << 600 ", // " << j << " " << SchedModels.getSchedClass(j).Name << "\n"; 601 } 602 // End processor itinerary table 603 OS << " { 0, ~0U, ~0U, ~0U, ~0U } // end marker\n"; 604 OS << "};\n"; 605 } 606} 607 608// Emit either the value defined in the TableGen Record, or the default 609// value defined in the C++ header. The Record is null if the processor does not 610// define a model. 611void SubtargetEmitter::EmitProcessorProp(raw_ostream &OS, const Record *R, 612 const char *Name, char Separator) { 613 OS << " "; 614 int V = R ? R->getValueAsInt(Name) : -1; 615 if (V >= 0) 616 OS << V << Separator << " // " << Name; 617 else 618 OS << "MCSchedModel::Default" << Name << Separator; 619 OS << '\n'; 620} 621 622void SubtargetEmitter::EmitProcessorResources(const CodeGenProcModel &ProcModel, 623 raw_ostream &OS) { 624 char Sep = ProcModel.ProcResourceDefs.empty() ? ' ' : ','; 625 626 OS << "\n// {Name, NumUnits, SuperIdx, IsBuffered}\n"; 627 OS << "static const llvm::MCProcResourceDesc " 628 << ProcModel.ModelName << "ProcResources" << "[] = {\n" 629 << " {DBGFIELD(\"InvalidUnit\") 0, 0, 0}" << Sep << "\n"; 630 631 for (unsigned i = 0, e = ProcModel.ProcResourceDefs.size(); i < e; ++i) { 632 Record *PRDef = ProcModel.ProcResourceDefs[i]; 633 634 Record *SuperDef = 0; 635 unsigned SuperIdx = 0; 636 unsigned NumUnits = 0; 637 bool IsBuffered = true; 638 if (PRDef->isSubClassOf("ProcResGroup")) { 639 RecVec ResUnits = PRDef->getValueAsListOfDefs("Resources"); 640 for (RecIter RUI = ResUnits.begin(), RUE = ResUnits.end(); 641 RUI != RUE; ++RUI) { 642 if (!NumUnits) 643 IsBuffered = (*RUI)->getValueAsBit("Buffered"); 644 else if(IsBuffered != (*RUI)->getValueAsBit("Buffered")) 645 PrintFatalError(PRDef->getLoc(), 646 "Mixing buffered and unbuffered resources."); 647 NumUnits += (*RUI)->getValueAsInt("NumUnits"); 648 } 649 } 650 else { 651 // Find the SuperIdx 652 if (PRDef->getValueInit("Super")->isComplete()) { 653 SuperDef = SchedModels.findProcResUnits( 654 PRDef->getValueAsDef("Super"), ProcModel); 655 SuperIdx = ProcModel.getProcResourceIdx(SuperDef); 656 } 657 NumUnits = PRDef->getValueAsInt("NumUnits"); 658 IsBuffered = PRDef->getValueAsBit("Buffered"); 659 } 660 // Emit the ProcResourceDesc 661 if (i+1 == e) 662 Sep = ' '; 663 OS << " {DBGFIELD(\"" << PRDef->getName() << "\") "; 664 if (PRDef->getName().size() < 15) 665 OS.indent(15 - PRDef->getName().size()); 666 OS << NumUnits << ", " << SuperIdx << ", " 667 << IsBuffered << "}" << Sep << " // #" << i+1; 668 if (SuperDef) 669 OS << ", Super=" << SuperDef->getName(); 670 OS << "\n"; 671 } 672 OS << "};\n"; 673} 674 675// Find the WriteRes Record that defines processor resources for this 676// SchedWrite. 677Record *SubtargetEmitter::FindWriteResources( 678 const CodeGenSchedRW &SchedWrite, const CodeGenProcModel &ProcModel) { 679 680 // Check if the SchedWrite is already subtarget-specific and directly 681 // specifies a set of processor resources. 682 if (SchedWrite.TheDef->isSubClassOf("SchedWriteRes")) 683 return SchedWrite.TheDef; 684 685 Record *AliasDef = 0; 686 for (RecIter AI = SchedWrite.Aliases.begin(), AE = SchedWrite.Aliases.end(); 687 AI != AE; ++AI) { 688 const CodeGenSchedRW &AliasRW = 689 SchedModels.getSchedRW((*AI)->getValueAsDef("AliasRW")); 690 if (AliasRW.TheDef->getValueInit("SchedModel")->isComplete()) { 691 Record *ModelDef = AliasRW.TheDef->getValueAsDef("SchedModel"); 692 if (&SchedModels.getProcModel(ModelDef) != &ProcModel) 693 continue; 694 } 695 if (AliasDef) 696 PrintFatalError(AliasRW.TheDef->getLoc(), "Multiple aliases " 697 "defined for processor " + ProcModel.ModelName + 698 " Ensure only one SchedAlias exists per RW."); 699 AliasDef = AliasRW.TheDef; 700 } 701 if (AliasDef && AliasDef->isSubClassOf("SchedWriteRes")) 702 return AliasDef; 703 704 // Check this processor's list of write resources. 705 Record *ResDef = 0; 706 for (RecIter WRI = ProcModel.WriteResDefs.begin(), 707 WRE = ProcModel.WriteResDefs.end(); WRI != WRE; ++WRI) { 708 if (!(*WRI)->isSubClassOf("WriteRes")) 709 continue; 710 if (AliasDef == (*WRI)->getValueAsDef("WriteType") 711 || SchedWrite.TheDef == (*WRI)->getValueAsDef("WriteType")) { 712 if (ResDef) { 713 PrintFatalError((*WRI)->getLoc(), "Resources are defined for both " 714 "SchedWrite and its alias on processor " + 715 ProcModel.ModelName); 716 } 717 ResDef = *WRI; 718 } 719 } 720 // TODO: If ProcModel has a base model (previous generation processor), 721 // then call FindWriteResources recursively with that model here. 722 if (!ResDef) { 723 PrintFatalError(ProcModel.ModelDef->getLoc(), 724 std::string("Processor does not define resources for ") 725 + SchedWrite.TheDef->getName()); 726 } 727 return ResDef; 728} 729 730/// Find the ReadAdvance record for the given SchedRead on this processor or 731/// return NULL. 732Record *SubtargetEmitter::FindReadAdvance(const CodeGenSchedRW &SchedRead, 733 const CodeGenProcModel &ProcModel) { 734 // Check for SchedReads that directly specify a ReadAdvance. 735 if (SchedRead.TheDef->isSubClassOf("SchedReadAdvance")) 736 return SchedRead.TheDef; 737 738 // Check this processor's list of aliases for SchedRead. 739 Record *AliasDef = 0; 740 for (RecIter AI = SchedRead.Aliases.begin(), AE = SchedRead.Aliases.end(); 741 AI != AE; ++AI) { 742 const CodeGenSchedRW &AliasRW = 743 SchedModels.getSchedRW((*AI)->getValueAsDef("AliasRW")); 744 if (AliasRW.TheDef->getValueInit("SchedModel")->isComplete()) { 745 Record *ModelDef = AliasRW.TheDef->getValueAsDef("SchedModel"); 746 if (&SchedModels.getProcModel(ModelDef) != &ProcModel) 747 continue; 748 } 749 if (AliasDef) 750 PrintFatalError(AliasRW.TheDef->getLoc(), "Multiple aliases " 751 "defined for processor " + ProcModel.ModelName + 752 " Ensure only one SchedAlias exists per RW."); 753 AliasDef = AliasRW.TheDef; 754 } 755 if (AliasDef && AliasDef->isSubClassOf("SchedReadAdvance")) 756 return AliasDef; 757 758 // Check this processor's ReadAdvanceList. 759 Record *ResDef = 0; 760 for (RecIter RAI = ProcModel.ReadAdvanceDefs.begin(), 761 RAE = ProcModel.ReadAdvanceDefs.end(); RAI != RAE; ++RAI) { 762 if (!(*RAI)->isSubClassOf("ReadAdvance")) 763 continue; 764 if (AliasDef == (*RAI)->getValueAsDef("ReadType") 765 || SchedRead.TheDef == (*RAI)->getValueAsDef("ReadType")) { 766 if (ResDef) { 767 PrintFatalError((*RAI)->getLoc(), "Resources are defined for both " 768 "SchedRead and its alias on processor " + 769 ProcModel.ModelName); 770 } 771 ResDef = *RAI; 772 } 773 } 774 // TODO: If ProcModel has a base model (previous generation processor), 775 // then call FindReadAdvance recursively with that model here. 776 if (!ResDef && SchedRead.TheDef->getName() != "ReadDefault") { 777 PrintFatalError(ProcModel.ModelDef->getLoc(), 778 std::string("Processor does not define resources for ") 779 + SchedRead.TheDef->getName()); 780 } 781 return ResDef; 782} 783 784// Expand an explicit list of processor resources into a full list of implied 785// resource groups that cover them. 786// 787// FIXME: Effectively consider a super-resource a group that include all of its 788// subresources to allow mixing and matching super-resources and groups. 789// 790// FIXME: Warn if two overlapping groups don't have a common supergroup. 791void SubtargetEmitter::ExpandProcResources(RecVec &PRVec, 792 std::vector<int64_t> &Cycles, 793 const CodeGenProcModel &ProcModel) { 794 // Default to 1 resource cycle. 795 Cycles.resize(PRVec.size(), 1); 796 for (unsigned i = 0, e = PRVec.size(); i != e; ++i) { 797 RecVec SubResources; 798 if (PRVec[i]->isSubClassOf("ProcResGroup")) { 799 SubResources = PRVec[i]->getValueAsListOfDefs("Resources"); 800 std::sort(SubResources.begin(), SubResources.end(), LessRecord()); 801 } 802 else { 803 SubResources.push_back(PRVec[i]); 804 } 805 for (RecIter PRI = ProcModel.ProcResourceDefs.begin(), 806 PRE = ProcModel.ProcResourceDefs.end(); 807 PRI != PRE; ++PRI) { 808 if (*PRI == PRVec[i] || !(*PRI)->isSubClassOf("ProcResGroup")) 809 continue; 810 RecVec SuperResources = (*PRI)->getValueAsListOfDefs("Resources"); 811 std::sort(SuperResources.begin(), SuperResources.end(), LessRecord()); 812 RecIter SubI = SubResources.begin(), SubE = SubResources.end(); 813 RecIter SuperI = SuperResources.begin(), SuperE = SuperResources.end(); 814 for ( ; SubI != SubE && SuperI != SuperE; ++SuperI) { 815 if (*SubI < *SuperI) 816 break; 817 else if (*SuperI < *SubI) 818 continue; 819 ++SubI; 820 } 821 if (SubI == SubE) { 822 PRVec.push_back(*PRI); 823 Cycles.push_back(Cycles[i]); 824 } 825 } 826 } 827} 828 829// Generate the SchedClass table for this processor and update global 830// tables. Must be called for each processor in order. 831void SubtargetEmitter::GenSchedClassTables(const CodeGenProcModel &ProcModel, 832 SchedClassTables &SchedTables) { 833 SchedTables.ProcSchedClasses.resize(SchedTables.ProcSchedClasses.size() + 1); 834 if (!ProcModel.hasInstrSchedModel()) 835 return; 836 837 std::vector<MCSchedClassDesc> &SCTab = SchedTables.ProcSchedClasses.back(); 838 for (CodeGenSchedModels::SchedClassIter SCI = SchedModels.schedClassBegin(), 839 SCE = SchedModels.schedClassEnd(); SCI != SCE; ++SCI) { 840 DEBUG(SCI->dump(&SchedModels)); 841 842 SCTab.resize(SCTab.size() + 1); 843 MCSchedClassDesc &SCDesc = SCTab.back(); 844 // SCDesc.Name is guarded by NDEBUG 845 SCDesc.NumMicroOps = 0; 846 SCDesc.BeginGroup = false; 847 SCDesc.EndGroup = false; 848 SCDesc.WriteProcResIdx = 0; 849 SCDesc.WriteLatencyIdx = 0; 850 SCDesc.ReadAdvanceIdx = 0; 851 852 // A Variant SchedClass has no resources of its own. 853 bool HasVariants = false; 854 for (std::vector<CodeGenSchedTransition>::const_iterator 855 TI = SCI->Transitions.begin(), TE = SCI->Transitions.end(); 856 TI != TE; ++TI) { 857 if (TI->ProcIndices[0] == 0) { 858 HasVariants = true; 859 break; 860 } 861 IdxIter PIPos = std::find(TI->ProcIndices.begin(), 862 TI->ProcIndices.end(), ProcModel.Index); 863 if (PIPos != TI->ProcIndices.end()) { 864 HasVariants = true; 865 break; 866 } 867 } 868 if (HasVariants) { 869 SCDesc.NumMicroOps = MCSchedClassDesc::VariantNumMicroOps; 870 continue; 871 } 872 873 // Determine if the SchedClass is actually reachable on this processor. If 874 // not don't try to locate the processor resources, it will fail. 875 // If ProcIndices contains 0, this class applies to all processors. 876 assert(!SCI->ProcIndices.empty() && "expect at least one procidx"); 877 if (SCI->ProcIndices[0] != 0) { 878 IdxIter PIPos = std::find(SCI->ProcIndices.begin(), 879 SCI->ProcIndices.end(), ProcModel.Index); 880 if (PIPos == SCI->ProcIndices.end()) 881 continue; 882 } 883 IdxVec Writes = SCI->Writes; 884 IdxVec Reads = SCI->Reads; 885 if (!SCI->InstRWs.empty()) { 886 // This class has a default ReadWrite list which can be overriden by 887 // InstRW definitions. 888 Record *RWDef = 0; 889 for (RecIter RWI = SCI->InstRWs.begin(), RWE = SCI->InstRWs.end(); 890 RWI != RWE; ++RWI) { 891 Record *RWModelDef = (*RWI)->getValueAsDef("SchedModel"); 892 if (&ProcModel == &SchedModels.getProcModel(RWModelDef)) { 893 RWDef = *RWI; 894 break; 895 } 896 } 897 if (RWDef) { 898 Writes.clear(); 899 Reads.clear(); 900 SchedModels.findRWs(RWDef->getValueAsListOfDefs("OperandReadWrites"), 901 Writes, Reads); 902 } 903 } 904 if (Writes.empty()) { 905 // Check this processor's itinerary class resources. 906 for (RecIter II = ProcModel.ItinRWDefs.begin(), 907 IE = ProcModel.ItinRWDefs.end(); II != IE; ++II) { 908 RecVec Matched = (*II)->getValueAsListOfDefs("MatchedItinClasses"); 909 if (std::find(Matched.begin(), Matched.end(), SCI->ItinClassDef) 910 != Matched.end()) { 911 SchedModels.findRWs((*II)->getValueAsListOfDefs("OperandReadWrites"), 912 Writes, Reads); 913 break; 914 } 915 } 916 if (Writes.empty()) { 917 DEBUG(dbgs() << ProcModel.ModelName 918 << " does not have resources for class " << SCI->Name << '\n'); 919 } 920 } 921 // Sum resources across all operand writes. 922 std::vector<MCWriteProcResEntry> WriteProcResources; 923 std::vector<MCWriteLatencyEntry> WriteLatencies; 924 std::vector<std::string> WriterNames; 925 std::vector<MCReadAdvanceEntry> ReadAdvanceEntries; 926 for (IdxIter WI = Writes.begin(), WE = Writes.end(); WI != WE; ++WI) { 927 IdxVec WriteSeq; 928 SchedModels.expandRWSeqForProc(*WI, WriteSeq, /*IsRead=*/false, 929 ProcModel); 930 931 // For each operand, create a latency entry. 932 MCWriteLatencyEntry WLEntry; 933 WLEntry.Cycles = 0; 934 unsigned WriteID = WriteSeq.back(); 935 WriterNames.push_back(SchedModels.getSchedWrite(WriteID).Name); 936 // If this Write is not referenced by a ReadAdvance, don't distinguish it 937 // from other WriteLatency entries. 938 if (!SchedModels.hasReadOfWrite( 939 SchedModels.getSchedWrite(WriteID).TheDef)) { 940 WriteID = 0; 941 } 942 WLEntry.WriteResourceID = WriteID; 943 944 for (IdxIter WSI = WriteSeq.begin(), WSE = WriteSeq.end(); 945 WSI != WSE; ++WSI) { 946 947 Record *WriteRes = 948 FindWriteResources(SchedModels.getSchedWrite(*WSI), ProcModel); 949 950 // Mark the parent class as invalid for unsupported write types. 951 if (WriteRes->getValueAsBit("Unsupported")) { 952 SCDesc.NumMicroOps = MCSchedClassDesc::InvalidNumMicroOps; 953 break; 954 } 955 WLEntry.Cycles += WriteRes->getValueAsInt("Latency"); 956 SCDesc.NumMicroOps += WriteRes->getValueAsInt("NumMicroOps"); 957 SCDesc.BeginGroup |= WriteRes->getValueAsBit("BeginGroup"); 958 SCDesc.EndGroup |= WriteRes->getValueAsBit("EndGroup"); 959 960 // Create an entry for each ProcResource listed in WriteRes. 961 RecVec PRVec = WriteRes->getValueAsListOfDefs("ProcResources"); 962 std::vector<int64_t> Cycles = 963 WriteRes->getValueAsListOfInts("ResourceCycles"); 964 965 ExpandProcResources(PRVec, Cycles, ProcModel); 966 967 for (unsigned PRIdx = 0, PREnd = PRVec.size(); 968 PRIdx != PREnd; ++PRIdx) { 969 MCWriteProcResEntry WPREntry; 970 WPREntry.ProcResourceIdx = ProcModel.getProcResourceIdx(PRVec[PRIdx]); 971 assert(WPREntry.ProcResourceIdx && "Bad ProcResourceIdx"); 972 WPREntry.Cycles = Cycles[PRIdx]; 973 // If this resource is already used in this sequence, add the current 974 // entry's cycles so that the same resource appears to be used 975 // serially, rather than multiple parallel uses. This is important for 976 // in-order machine where the resource consumption is a hazard. 977 unsigned WPRIdx = 0, WPREnd = WriteProcResources.size(); 978 for( ; WPRIdx != WPREnd; ++WPRIdx) { 979 if (WriteProcResources[WPRIdx].ProcResourceIdx 980 == WPREntry.ProcResourceIdx) { 981 WriteProcResources[WPRIdx].Cycles += WPREntry.Cycles; 982 break; 983 } 984 } 985 if (WPRIdx == WPREnd) 986 WriteProcResources.push_back(WPREntry); 987 } 988 } 989 WriteLatencies.push_back(WLEntry); 990 } 991 // Create an entry for each operand Read in this SchedClass. 992 // Entries must be sorted first by UseIdx then by WriteResourceID. 993 for (unsigned UseIdx = 0, EndIdx = Reads.size(); 994 UseIdx != EndIdx; ++UseIdx) { 995 Record *ReadAdvance = 996 FindReadAdvance(SchedModels.getSchedRead(Reads[UseIdx]), ProcModel); 997 if (!ReadAdvance) 998 continue; 999 1000 // Mark the parent class as invalid for unsupported write types. 1001 if (ReadAdvance->getValueAsBit("Unsupported")) { 1002 SCDesc.NumMicroOps = MCSchedClassDesc::InvalidNumMicroOps; 1003 break; 1004 } 1005 RecVec ValidWrites = ReadAdvance->getValueAsListOfDefs("ValidWrites"); 1006 IdxVec WriteIDs; 1007 if (ValidWrites.empty()) 1008 WriteIDs.push_back(0); 1009 else { 1010 for (RecIter VWI = ValidWrites.begin(), VWE = ValidWrites.end(); 1011 VWI != VWE; ++VWI) { 1012 WriteIDs.push_back(SchedModels.getSchedRWIdx(*VWI, /*IsRead=*/false)); 1013 } 1014 } 1015 std::sort(WriteIDs.begin(), WriteIDs.end()); 1016 for(IdxIter WI = WriteIDs.begin(), WE = WriteIDs.end(); WI != WE; ++WI) { 1017 MCReadAdvanceEntry RAEntry; 1018 RAEntry.UseIdx = UseIdx; 1019 RAEntry.WriteResourceID = *WI; 1020 RAEntry.Cycles = ReadAdvance->getValueAsInt("Cycles"); 1021 ReadAdvanceEntries.push_back(RAEntry); 1022 } 1023 } 1024 if (SCDesc.NumMicroOps == MCSchedClassDesc::InvalidNumMicroOps) { 1025 WriteProcResources.clear(); 1026 WriteLatencies.clear(); 1027 ReadAdvanceEntries.clear(); 1028 } 1029 // Add the information for this SchedClass to the global tables using basic 1030 // compression. 1031 // 1032 // WritePrecRes entries are sorted by ProcResIdx. 1033 std::sort(WriteProcResources.begin(), WriteProcResources.end(), 1034 LessWriteProcResources()); 1035 1036 SCDesc.NumWriteProcResEntries = WriteProcResources.size(); 1037 std::vector<MCWriteProcResEntry>::iterator WPRPos = 1038 std::search(SchedTables.WriteProcResources.begin(), 1039 SchedTables.WriteProcResources.end(), 1040 WriteProcResources.begin(), WriteProcResources.end()); 1041 if (WPRPos != SchedTables.WriteProcResources.end()) 1042 SCDesc.WriteProcResIdx = WPRPos - SchedTables.WriteProcResources.begin(); 1043 else { 1044 SCDesc.WriteProcResIdx = SchedTables.WriteProcResources.size(); 1045 SchedTables.WriteProcResources.insert(WPRPos, WriteProcResources.begin(), 1046 WriteProcResources.end()); 1047 } 1048 // Latency entries must remain in operand order. 1049 SCDesc.NumWriteLatencyEntries = WriteLatencies.size(); 1050 std::vector<MCWriteLatencyEntry>::iterator WLPos = 1051 std::search(SchedTables.WriteLatencies.begin(), 1052 SchedTables.WriteLatencies.end(), 1053 WriteLatencies.begin(), WriteLatencies.end()); 1054 if (WLPos != SchedTables.WriteLatencies.end()) { 1055 unsigned idx = WLPos - SchedTables.WriteLatencies.begin(); 1056 SCDesc.WriteLatencyIdx = idx; 1057 for (unsigned i = 0, e = WriteLatencies.size(); i < e; ++i) 1058 if (SchedTables.WriterNames[idx + i].find(WriterNames[i]) == 1059 std::string::npos) { 1060 SchedTables.WriterNames[idx + i] += std::string("_") + WriterNames[i]; 1061 } 1062 } 1063 else { 1064 SCDesc.WriteLatencyIdx = SchedTables.WriteLatencies.size(); 1065 SchedTables.WriteLatencies.insert(SchedTables.WriteLatencies.end(), 1066 WriteLatencies.begin(), 1067 WriteLatencies.end()); 1068 SchedTables.WriterNames.insert(SchedTables.WriterNames.end(), 1069 WriterNames.begin(), WriterNames.end()); 1070 } 1071 // ReadAdvanceEntries must remain in operand order. 1072 SCDesc.NumReadAdvanceEntries = ReadAdvanceEntries.size(); 1073 std::vector<MCReadAdvanceEntry>::iterator RAPos = 1074 std::search(SchedTables.ReadAdvanceEntries.begin(), 1075 SchedTables.ReadAdvanceEntries.end(), 1076 ReadAdvanceEntries.begin(), ReadAdvanceEntries.end()); 1077 if (RAPos != SchedTables.ReadAdvanceEntries.end()) 1078 SCDesc.ReadAdvanceIdx = RAPos - SchedTables.ReadAdvanceEntries.begin(); 1079 else { 1080 SCDesc.ReadAdvanceIdx = SchedTables.ReadAdvanceEntries.size(); 1081 SchedTables.ReadAdvanceEntries.insert(RAPos, ReadAdvanceEntries.begin(), 1082 ReadAdvanceEntries.end()); 1083 } 1084 } 1085} 1086 1087// Emit SchedClass tables for all processors and associated global tables. 1088void SubtargetEmitter::EmitSchedClassTables(SchedClassTables &SchedTables, 1089 raw_ostream &OS) { 1090 // Emit global WriteProcResTable. 1091 OS << "\n// {ProcResourceIdx, Cycles}\n" 1092 << "extern const llvm::MCWriteProcResEntry " 1093 << Target << "WriteProcResTable[] = {\n" 1094 << " { 0, 0}, // Invalid\n"; 1095 for (unsigned WPRIdx = 1, WPREnd = SchedTables.WriteProcResources.size(); 1096 WPRIdx != WPREnd; ++WPRIdx) { 1097 MCWriteProcResEntry &WPREntry = SchedTables.WriteProcResources[WPRIdx]; 1098 OS << " {" << format("%2d", WPREntry.ProcResourceIdx) << ", " 1099 << format("%2d", WPREntry.Cycles) << "}"; 1100 if (WPRIdx + 1 < WPREnd) 1101 OS << ','; 1102 OS << " // #" << WPRIdx << '\n'; 1103 } 1104 OS << "}; // " << Target << "WriteProcResTable\n"; 1105 1106 // Emit global WriteLatencyTable. 1107 OS << "\n// {Cycles, WriteResourceID}\n" 1108 << "extern const llvm::MCWriteLatencyEntry " 1109 << Target << "WriteLatencyTable[] = {\n" 1110 << " { 0, 0}, // Invalid\n"; 1111 for (unsigned WLIdx = 1, WLEnd = SchedTables.WriteLatencies.size(); 1112 WLIdx != WLEnd; ++WLIdx) { 1113 MCWriteLatencyEntry &WLEntry = SchedTables.WriteLatencies[WLIdx]; 1114 OS << " {" << format("%2d", WLEntry.Cycles) << ", " 1115 << format("%2d", WLEntry.WriteResourceID) << "}"; 1116 if (WLIdx + 1 < WLEnd) 1117 OS << ','; 1118 OS << " // #" << WLIdx << " " << SchedTables.WriterNames[WLIdx] << '\n'; 1119 } 1120 OS << "}; // " << Target << "WriteLatencyTable\n"; 1121 1122 // Emit global ReadAdvanceTable. 1123 OS << "\n// {UseIdx, WriteResourceID, Cycles}\n" 1124 << "extern const llvm::MCReadAdvanceEntry " 1125 << Target << "ReadAdvanceTable[] = {\n" 1126 << " {0, 0, 0}, // Invalid\n"; 1127 for (unsigned RAIdx = 1, RAEnd = SchedTables.ReadAdvanceEntries.size(); 1128 RAIdx != RAEnd; ++RAIdx) { 1129 MCReadAdvanceEntry &RAEntry = SchedTables.ReadAdvanceEntries[RAIdx]; 1130 OS << " {" << RAEntry.UseIdx << ", " 1131 << format("%2d", RAEntry.WriteResourceID) << ", " 1132 << format("%2d", RAEntry.Cycles) << "}"; 1133 if (RAIdx + 1 < RAEnd) 1134 OS << ','; 1135 OS << " // #" << RAIdx << '\n'; 1136 } 1137 OS << "}; // " << Target << "ReadAdvanceTable\n"; 1138 1139 // Emit a SchedClass table for each processor. 1140 for (CodeGenSchedModels::ProcIter PI = SchedModels.procModelBegin(), 1141 PE = SchedModels.procModelEnd(); PI != PE; ++PI) { 1142 if (!PI->hasInstrSchedModel()) 1143 continue; 1144 1145 std::vector<MCSchedClassDesc> &SCTab = 1146 SchedTables.ProcSchedClasses[1 + (PI - SchedModels.procModelBegin())]; 1147 1148 OS << "\n// {Name, NumMicroOps, BeginGroup, EndGroup," 1149 << " WriteProcResIdx,#, WriteLatencyIdx,#, ReadAdvanceIdx,#}\n"; 1150 OS << "static const llvm::MCSchedClassDesc " 1151 << PI->ModelName << "SchedClasses[] = {\n"; 1152 1153 // The first class is always invalid. We no way to distinguish it except by 1154 // name and position. 1155 assert(SchedModels.getSchedClass(0).Name == "NoInstrModel" 1156 && "invalid class not first"); 1157 OS << " {DBGFIELD(\"InvalidSchedClass\") " 1158 << MCSchedClassDesc::InvalidNumMicroOps 1159 << ", 0, 0, 0, 0, 0, 0, 0, 0},\n"; 1160 1161 for (unsigned SCIdx = 1, SCEnd = SCTab.size(); SCIdx != SCEnd; ++SCIdx) { 1162 MCSchedClassDesc &MCDesc = SCTab[SCIdx]; 1163 const CodeGenSchedClass &SchedClass = SchedModels.getSchedClass(SCIdx); 1164 OS << " {DBGFIELD(\"" << SchedClass.Name << "\") "; 1165 if (SchedClass.Name.size() < 18) 1166 OS.indent(18 - SchedClass.Name.size()); 1167 OS << MCDesc.NumMicroOps 1168 << ", " << MCDesc.BeginGroup << ", " << MCDesc.EndGroup 1169 << ", " << format("%2d", MCDesc.WriteProcResIdx) 1170 << ", " << MCDesc.NumWriteProcResEntries 1171 << ", " << format("%2d", MCDesc.WriteLatencyIdx) 1172 << ", " << MCDesc.NumWriteLatencyEntries 1173 << ", " << format("%2d", MCDesc.ReadAdvanceIdx) 1174 << ", " << MCDesc.NumReadAdvanceEntries << "}"; 1175 if (SCIdx + 1 < SCEnd) 1176 OS << ','; 1177 OS << " // #" << SCIdx << '\n'; 1178 } 1179 OS << "}; // " << PI->ModelName << "SchedClasses\n"; 1180 } 1181} 1182 1183void SubtargetEmitter::EmitProcessorModels(raw_ostream &OS) { 1184 // For each processor model. 1185 for (CodeGenSchedModels::ProcIter PI = SchedModels.procModelBegin(), 1186 PE = SchedModels.procModelEnd(); PI != PE; ++PI) { 1187 // Emit processor resource table. 1188 if (PI->hasInstrSchedModel()) 1189 EmitProcessorResources(*PI, OS); 1190 else if(!PI->ProcResourceDefs.empty()) 1191 PrintFatalError(PI->ModelDef->getLoc(), "SchedMachineModel defines " 1192 "ProcResources without defining WriteRes SchedWriteRes"); 1193 1194 // Begin processor itinerary properties 1195 OS << "\n"; 1196 OS << "static const llvm::MCSchedModel " << PI->ModelName << "(\n"; 1197 EmitProcessorProp(OS, PI->ModelDef, "IssueWidth", ','); 1198 EmitProcessorProp(OS, PI->ModelDef, "MinLatency", ','); 1199 EmitProcessorProp(OS, PI->ModelDef, "LoadLatency", ','); 1200 EmitProcessorProp(OS, PI->ModelDef, "HighLatency", ','); 1201 EmitProcessorProp(OS, PI->ModelDef, "ILPWindow", ','); 1202 EmitProcessorProp(OS, PI->ModelDef, "MispredictPenalty", ','); 1203 OS << " " << PI->Index << ", // Processor ID\n"; 1204 if (PI->hasInstrSchedModel()) 1205 OS << " " << PI->ModelName << "ProcResources" << ",\n" 1206 << " " << PI->ModelName << "SchedClasses" << ",\n" 1207 << " " << PI->ProcResourceDefs.size()+1 << ",\n" 1208 << " " << (SchedModels.schedClassEnd() 1209 - SchedModels.schedClassBegin()) << ",\n"; 1210 else 1211 OS << " 0, 0, 0, 0, // No instruction-level machine model.\n"; 1212 if (SchedModels.hasItineraries()) 1213 OS << " " << PI->ItinsDef->getName() << ");\n"; 1214 else 1215 OS << " 0); // No Itinerary\n"; 1216 } 1217} 1218 1219// 1220// EmitProcessorLookup - generate cpu name to itinerary lookup table. 1221// 1222void SubtargetEmitter::EmitProcessorLookup(raw_ostream &OS) { 1223 // Gather and sort processor information 1224 std::vector<Record*> ProcessorList = 1225 Records.getAllDerivedDefinitions("Processor"); 1226 std::sort(ProcessorList.begin(), ProcessorList.end(), LessRecordFieldName()); 1227 1228 // Begin processor table 1229 OS << "\n"; 1230 OS << "// Sorted (by key) array of itineraries for CPU subtype.\n" 1231 << "extern const llvm::SubtargetInfoKV " 1232 << Target << "ProcSchedKV[] = {\n"; 1233 1234 // For each processor 1235 for (unsigned i = 0, N = ProcessorList.size(); i < N;) { 1236 // Next processor 1237 Record *Processor = ProcessorList[i]; 1238 1239 const std::string &Name = Processor->getValueAsString("Name"); 1240 const std::string &ProcModelName = 1241 SchedModels.getModelForProc(Processor).ModelName; 1242 1243 // Emit as { "cpu", procinit }, 1244 OS << " { \"" << Name << "\", (const void *)&" << ProcModelName << " }"; 1245 1246 // Depending on ''if more in the list'' emit comma 1247 if (++i < N) OS << ","; 1248 1249 OS << "\n"; 1250 } 1251 1252 // End processor table 1253 OS << "};\n"; 1254} 1255 1256// 1257// EmitSchedModel - Emits all scheduling model tables, folding common patterns. 1258// 1259void SubtargetEmitter::EmitSchedModel(raw_ostream &OS) { 1260 OS << "#ifdef DBGFIELD\n" 1261 << "#error \"<target>GenSubtargetInfo.inc requires a DBGFIELD macro\"\n" 1262 << "#endif\n" 1263 << "#ifndef NDEBUG\n" 1264 << "#define DBGFIELD(x) x,\n" 1265 << "#else\n" 1266 << "#define DBGFIELD(x)\n" 1267 << "#endif\n"; 1268 1269 if (SchedModels.hasItineraries()) { 1270 std::vector<std::vector<InstrItinerary> > ProcItinLists; 1271 // Emit the stage data 1272 EmitStageAndOperandCycleData(OS, ProcItinLists); 1273 EmitItineraries(OS, ProcItinLists); 1274 } 1275 OS << "\n// ===============================================================\n" 1276 << "// Data tables for the new per-operand machine model.\n"; 1277 1278 SchedClassTables SchedTables; 1279 for (CodeGenSchedModels::ProcIter PI = SchedModels.procModelBegin(), 1280 PE = SchedModels.procModelEnd(); PI != PE; ++PI) { 1281 GenSchedClassTables(*PI, SchedTables); 1282 } 1283 EmitSchedClassTables(SchedTables, OS); 1284 1285 // Emit the processor machine model 1286 EmitProcessorModels(OS); 1287 // Emit the processor lookup data 1288 EmitProcessorLookup(OS); 1289 1290 OS << "#undef DBGFIELD"; 1291} 1292 1293void SubtargetEmitter::EmitSchedModelHelpers(std::string ClassName, 1294 raw_ostream &OS) { 1295 OS << "unsigned " << ClassName 1296 << "\n::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI," 1297 << " const TargetSchedModel *SchedModel) const {\n"; 1298 1299 std::vector<Record*> Prologs = Records.getAllDerivedDefinitions("PredicateProlog"); 1300 std::sort(Prologs.begin(), Prologs.end(), LessRecord()); 1301 for (std::vector<Record*>::const_iterator 1302 PI = Prologs.begin(), PE = Prologs.end(); PI != PE; ++PI) { 1303 OS << (*PI)->getValueAsString("Code") << '\n'; 1304 } 1305 IdxVec VariantClasses; 1306 for (CodeGenSchedModels::SchedClassIter SCI = SchedModels.schedClassBegin(), 1307 SCE = SchedModels.schedClassEnd(); SCI != SCE; ++SCI) { 1308 if (SCI->Transitions.empty()) 1309 continue; 1310 VariantClasses.push_back(SCI->Index); 1311 } 1312 if (!VariantClasses.empty()) { 1313 OS << " switch (SchedClass) {\n"; 1314 for (IdxIter VCI = VariantClasses.begin(), VCE = VariantClasses.end(); 1315 VCI != VCE; ++VCI) { 1316 const CodeGenSchedClass &SC = SchedModels.getSchedClass(*VCI); 1317 OS << " case " << *VCI << ": // " << SC.Name << '\n'; 1318 IdxVec ProcIndices; 1319 for (std::vector<CodeGenSchedTransition>::const_iterator 1320 TI = SC.Transitions.begin(), TE = SC.Transitions.end(); 1321 TI != TE; ++TI) { 1322 IdxVec PI; 1323 std::set_union(TI->ProcIndices.begin(), TI->ProcIndices.end(), 1324 ProcIndices.begin(), ProcIndices.end(), 1325 std::back_inserter(PI)); 1326 ProcIndices.swap(PI); 1327 } 1328 for (IdxIter PI = ProcIndices.begin(), PE = ProcIndices.end(); 1329 PI != PE; ++PI) { 1330 OS << " "; 1331 if (*PI != 0) 1332 OS << "if (SchedModel->getProcessorID() == " << *PI << ") "; 1333 OS << "{ // " << (SchedModels.procModelBegin() + *PI)->ModelName 1334 << '\n'; 1335 for (std::vector<CodeGenSchedTransition>::const_iterator 1336 TI = SC.Transitions.begin(), TE = SC.Transitions.end(); 1337 TI != TE; ++TI) { 1338 OS << " if ("; 1339 if (*PI != 0 && !std::count(TI->ProcIndices.begin(), 1340 TI->ProcIndices.end(), *PI)) { 1341 continue; 1342 } 1343 for (RecIter RI = TI->PredTerm.begin(), RE = TI->PredTerm.end(); 1344 RI != RE; ++RI) { 1345 if (RI != TI->PredTerm.begin()) 1346 OS << "\n && "; 1347 OS << "(" << (*RI)->getValueAsString("Predicate") << ")"; 1348 } 1349 OS << ")\n" 1350 << " return " << TI->ToClassIdx << "; // " 1351 << SchedModels.getSchedClass(TI->ToClassIdx).Name << '\n'; 1352 } 1353 OS << " }\n"; 1354 if (*PI == 0) 1355 break; 1356 } 1357 if (SC.isInferred()) 1358 OS << " return " << SC.Index << ";\n"; 1359 OS << " break;\n"; 1360 } 1361 OS << " };\n"; 1362 } 1363 OS << " report_fatal_error(\"Expected a variant SchedClass\");\n" 1364 << "} // " << ClassName << "::resolveSchedClass\n"; 1365} 1366 1367// 1368// ParseFeaturesFunction - Produces a subtarget specific function for parsing 1369// the subtarget features string. 1370// 1371void SubtargetEmitter::ParseFeaturesFunction(raw_ostream &OS, 1372 unsigned NumFeatures, 1373 unsigned NumProcs) { 1374 std::vector<Record*> Features = 1375 Records.getAllDerivedDefinitions("SubtargetFeature"); 1376 std::sort(Features.begin(), Features.end(), LessRecord()); 1377 1378 OS << "// ParseSubtargetFeatures - Parses features string setting specified\n" 1379 << "// subtarget options.\n" 1380 << "void llvm::"; 1381 OS << Target; 1382 OS << "Subtarget::ParseSubtargetFeatures(StringRef CPU, StringRef FS) {\n" 1383 << " DEBUG(dbgs() << \"\\nFeatures:\" << FS);\n" 1384 << " DEBUG(dbgs() << \"\\nCPU:\" << CPU << \"\\n\\n\");\n"; 1385 1386 if (Features.empty()) { 1387 OS << "}\n"; 1388 return; 1389 } 1390 1391 OS << " InitMCProcessorInfo(CPU, FS);\n" 1392 << " uint64_t Bits = getFeatureBits();\n"; 1393 1394 for (unsigned i = 0; i < Features.size(); i++) { 1395 // Next record 1396 Record *R = Features[i]; 1397 const std::string &Instance = R->getName(); 1398 const std::string &Value = R->getValueAsString("Value"); 1399 const std::string &Attribute = R->getValueAsString("Attribute"); 1400 1401 if (Value=="true" || Value=="false") 1402 OS << " if ((Bits & " << Target << "::" 1403 << Instance << ") != 0) " 1404 << Attribute << " = " << Value << ";\n"; 1405 else 1406 OS << " if ((Bits & " << Target << "::" 1407 << Instance << ") != 0 && " 1408 << Attribute << " < " << Value << ") " 1409 << Attribute << " = " << Value << ";\n"; 1410 } 1411 1412 OS << "}\n"; 1413} 1414 1415// 1416// SubtargetEmitter::run - Main subtarget enumeration emitter. 1417// 1418void SubtargetEmitter::run(raw_ostream &OS) { 1419 emitSourceFileHeader("Subtarget Enumeration Source Fragment", OS); 1420 1421 OS << "\n#ifdef GET_SUBTARGETINFO_ENUM\n"; 1422 OS << "#undef GET_SUBTARGETINFO_ENUM\n"; 1423 1424 OS << "namespace llvm {\n"; 1425 Enumeration(OS, "SubtargetFeature", true); 1426 OS << "} // End llvm namespace \n"; 1427 OS << "#endif // GET_SUBTARGETINFO_ENUM\n\n"; 1428 1429 OS << "\n#ifdef GET_SUBTARGETINFO_MC_DESC\n"; 1430 OS << "#undef GET_SUBTARGETINFO_MC_DESC\n"; 1431 1432 OS << "namespace llvm {\n"; 1433#if 0 1434 OS << "namespace {\n"; 1435#endif 1436 unsigned NumFeatures = FeatureKeyValues(OS); 1437 OS << "\n"; 1438 unsigned NumProcs = CPUKeyValues(OS); 1439 OS << "\n"; 1440 EmitSchedModel(OS); 1441 OS << "\n"; 1442#if 0 1443 OS << "}\n"; 1444#endif 1445 1446 // MCInstrInfo initialization routine. 1447 OS << "static inline void Init" << Target 1448 << "MCSubtargetInfo(MCSubtargetInfo *II, " 1449 << "StringRef TT, StringRef CPU, StringRef FS) {\n"; 1450 OS << " II->InitMCSubtargetInfo(TT, CPU, FS, "; 1451 if (NumFeatures) 1452 OS << Target << "FeatureKV, "; 1453 else 1454 OS << "0, "; 1455 if (NumProcs) 1456 OS << Target << "SubTypeKV, "; 1457 else 1458 OS << "0, "; 1459 OS << '\n'; OS.indent(22); 1460 OS << Target << "ProcSchedKV, " 1461 << Target << "WriteProcResTable, " 1462 << Target << "WriteLatencyTable, " 1463 << Target << "ReadAdvanceTable, "; 1464 if (SchedModels.hasItineraries()) { 1465 OS << '\n'; OS.indent(22); 1466 OS << Target << "Stages, " 1467 << Target << "OperandCycles, " 1468 << Target << "ForwardingPaths, "; 1469 } else 1470 OS << "0, 0, 0, "; 1471 OS << NumFeatures << ", " << NumProcs << ");\n}\n\n"; 1472 1473 OS << "} // End llvm namespace \n"; 1474 1475 OS << "#endif // GET_SUBTARGETINFO_MC_DESC\n\n"; 1476 1477 OS << "\n#ifdef GET_SUBTARGETINFO_TARGET_DESC\n"; 1478 OS << "#undef GET_SUBTARGETINFO_TARGET_DESC\n"; 1479 1480 OS << "#include \"llvm/Support/Debug.h\"\n"; 1481 OS << "#include \"llvm/Support/raw_ostream.h\"\n"; 1482 ParseFeaturesFunction(OS, NumFeatures, NumProcs); 1483 1484 OS << "#endif // GET_SUBTARGETINFO_TARGET_DESC\n\n"; 1485 1486 // Create a TargetSubtargetInfo subclass to hide the MC layer initialization. 1487 OS << "\n#ifdef GET_SUBTARGETINFO_HEADER\n"; 1488 OS << "#undef GET_SUBTARGETINFO_HEADER\n"; 1489 1490 std::string ClassName = Target + "GenSubtargetInfo"; 1491 OS << "namespace llvm {\n"; 1492 OS << "class DFAPacketizer;\n"; 1493 OS << "struct " << ClassName << " : public TargetSubtargetInfo {\n" 1494 << " explicit " << ClassName << "(StringRef TT, StringRef CPU, " 1495 << "StringRef FS);\n" 1496 << "public:\n" 1497 << " unsigned resolveSchedClass(unsigned SchedClass, const MachineInstr *DefMI," 1498 << " const TargetSchedModel *SchedModel) const;\n" 1499 << " DFAPacketizer *createDFAPacketizer(const InstrItineraryData *IID)" 1500 << " const;\n" 1501 << "};\n"; 1502 OS << "} // End llvm namespace \n"; 1503 1504 OS << "#endif // GET_SUBTARGETINFO_HEADER\n\n"; 1505 1506 OS << "\n#ifdef GET_SUBTARGETINFO_CTOR\n"; 1507 OS << "#undef GET_SUBTARGETINFO_CTOR\n"; 1508 1509 OS << "#include \"llvm/CodeGen/TargetSchedule.h\"\n"; 1510 OS << "namespace llvm {\n"; 1511 OS << "extern const llvm::SubtargetFeatureKV " << Target << "FeatureKV[];\n"; 1512 OS << "extern const llvm::SubtargetFeatureKV " << Target << "SubTypeKV[];\n"; 1513 OS << "extern const llvm::SubtargetInfoKV " << Target << "ProcSchedKV[];\n"; 1514 OS << "extern const llvm::MCWriteProcResEntry " 1515 << Target << "WriteProcResTable[];\n"; 1516 OS << "extern const llvm::MCWriteLatencyEntry " 1517 << Target << "WriteLatencyTable[];\n"; 1518 OS << "extern const llvm::MCReadAdvanceEntry " 1519 << Target << "ReadAdvanceTable[];\n"; 1520 1521 if (SchedModels.hasItineraries()) { 1522 OS << "extern const llvm::InstrStage " << Target << "Stages[];\n"; 1523 OS << "extern const unsigned " << Target << "OperandCycles[];\n"; 1524 OS << "extern const unsigned " << Target << "ForwardingPaths[];\n"; 1525 } 1526 1527 OS << ClassName << "::" << ClassName << "(StringRef TT, StringRef CPU, " 1528 << "StringRef FS)\n" 1529 << " : TargetSubtargetInfo() {\n" 1530 << " InitMCSubtargetInfo(TT, CPU, FS, "; 1531 if (NumFeatures) 1532 OS << Target << "FeatureKV, "; 1533 else 1534 OS << "0, "; 1535 if (NumProcs) 1536 OS << Target << "SubTypeKV, "; 1537 else 1538 OS << "0, "; 1539 OS << '\n'; OS.indent(22); 1540 OS << Target << "ProcSchedKV, " 1541 << Target << "WriteProcResTable, " 1542 << Target << "WriteLatencyTable, " 1543 << Target << "ReadAdvanceTable, "; 1544 OS << '\n'; OS.indent(22); 1545 if (SchedModels.hasItineraries()) { 1546 OS << Target << "Stages, " 1547 << Target << "OperandCycles, " 1548 << Target << "ForwardingPaths, "; 1549 } else 1550 OS << "0, 0, 0, "; 1551 OS << NumFeatures << ", " << NumProcs << ");\n}\n\n"; 1552 1553 EmitSchedModelHelpers(ClassName, OS); 1554 1555 OS << "} // End llvm namespace \n"; 1556 1557 OS << "#endif // GET_SUBTARGETINFO_CTOR\n\n"; 1558} 1559 1560namespace llvm { 1561 1562void EmitSubtarget(RecordKeeper &RK, raw_ostream &OS) { 1563 CodeGenTarget CGTarget(RK); 1564 SubtargetEmitter(RK, CGTarget).run(OS); 1565} 1566 1567} // End llvm namespace 1568