DisassemblerEmitter.cpp revision 226633
118334Speter//===- DisassemblerEmitter.cpp - Generate a disassembler ------------------===// 290075Sobrien// 3169689Skan// The LLVM Compiler Infrastructure 4169689Skan// 518334Speter// This file is distributed under the University of Illinois Open Source 690075Sobrien// License. See LICENSE.TXT for details. 718334Speter// 890075Sobrien//===----------------------------------------------------------------------===// 990075Sobrien 1090075Sobrien#include "DisassemblerEmitter.h" 1190075Sobrien#include "CodeGenTarget.h" 1218334Speter#include "X86DisassemblerTables.h" 1390075Sobrien#include "X86RecognizableInstr.h" 1490075Sobrien#include "ARMDecoderEmitter.h" 1590075Sobrien#include "FixedLenDecoderEmitter.h" 1690075Sobrien#include "llvm/TableGen/Error.h" 1718334Speter#include "llvm/TableGen/Record.h" 1818334Speter 1990075Sobrienusing namespace llvm; 20169689Skanusing namespace llvm::X86Disassembler; 21169689Skan 2218334Speter/// DisassemblerEmitter - Contains disassembler table emitters for various 23169689Skan/// architectures. 24169689Skan 25169689Skan/// X86 Disassembler Emitter 26169689Skan/// 27169689Skan/// *** IF YOU'RE HERE TO RESOLVE A "Primary decode conflict", LOOK DOWN NEAR 28169689Skan/// THE END OF THIS COMMENT! 29169689Skan/// 30169689Skan/// The X86 disassembler emitter is part of the X86 Disassembler, which is 31169689Skan/// documented in lib/Target/X86/X86Disassembler.h. 32169689Skan/// 33169689Skan/// The emitter produces the tables that the disassembler uses to translate 34169689Skan/// instructions. The emitter generates the following tables: 35169689Skan/// 36169689Skan/// - One table (CONTEXTS_SYM) that contains a mapping of attribute masks to 37169689Skan/// instruction contexts. Although for each attribute there are cases where 3818334Speter/// that attribute determines decoding, in the majority of cases decoding is 3918334Speter/// the same whether or not an attribute is present. For example, a 64-bit 4018334Speter/// instruction with an OPSIZE prefix and an XS prefix decodes the same way in 4118334Speter/// all cases as a 64-bit instruction with only OPSIZE set. (The XS prefix 4218334Speter/// may have effects on its execution, but does not change the instruction 4318334Speter/// returned.) This allows considerable space savings in other tables. 44117395Skan/// - Six tables (ONEBYTE_SYM, TWOBYTE_SYM, THREEBYTE38_SYM, THREEBYTE3A_SYM, 45169689Skan/// THREEBYTEA6_SYM, and THREEBYTEA7_SYM contain the hierarchy that the 4618334Speter/// decoder traverses while decoding an instruction. At the lowest level of 4718334Speter/// this hierarchy are instruction UIDs, 16-bit integers that can be used to 4818334Speter/// uniquely identify the instruction and correspond exactly to its position 4950397Sobrien/// in the list of CodeGenInstructions for the target. 50117395Skan/// - One table (INSTRUCTIONS_SYM) contains information about the operands of 51117395Skan/// each instruction and how to decode them. 52117395Skan/// 53169689Skan/// During table generation, there may be conflicts between instructions that 54117395Skan/// occupy the same space in the decode tables. These conflicts are resolved as 55117395Skan/// follows in setTableFields() (X86DisassemblerTables.cpp) 5618334Speter/// 5752284Sobrien/// - If the current context is the native context for one of the instructions 5852284Sobrien/// (that is, the attributes specified for it in the LLVM tables specify 5952284Sobrien/// precisely the current context), then it has priority. 6052284Sobrien/// - If the current context isn't native for either of the instructions, then 6152284Sobrien/// the higher-priority context wins (that is, the one that is more specific). 6252284Sobrien/// That hierarchy is determined by outranks() (X86DisassemblerTables.cpp) 6352284Sobrien/// - If the current context is native for both instructions, then the table 6418334Speter/// emitter reports a conflict and dies. 65132718Skan/// 66169689Skan/// *** RESOLUTION FOR "Primary decode conflict"S 67132718Skan/// 68132718Skan/// If two instructions collide, typically the solution is (in order of 69169689Skan/// likelihood): 70132718Skan/// 71132718Skan/// (1) to filter out one of the instructions by editing filter() 72132718Skan/// (X86RecognizableInstr.cpp). This is the most common resolution, but 73132718Skan/// check the Intel manuals first to make sure that (2) and (3) are not the 74132718Skan/// problem. 75132718Skan/// (2) to fix the tables (X86.td and its subsidiaries) so the opcodes are 76132718Skan/// accurate. Sometimes they are not. 77132718Skan/// (3) to fix the tables to reflect the actual context (for example, required 78169689Skan/// prefixes), and possibly to add a new context by editing 79132718Skan/// lib/Target/X86/X86DisassemblerDecoderCommon.h. This is unlikely to be 80132718Skan/// the cause. 81169689Skan/// 82132718Skan/// DisassemblerEmitter.cpp contains the implementation for the emitter, 83132718Skan/// which simply pulls out instructions from the CodeGenTarget and pushes them 84132718Skan/// into X86DisassemblerTables. 85132718Skan/// X86DisassemblerTables.h contains the interface for the instruction tables, 86132718Skan/// which manage and emit the structures discussed above. 87132718Skan/// X86DisassemblerTables.cpp contains the implementation for the instruction 88132718Skan/// tables. 89132718Skan/// X86ModRMFilters.h contains filters that can be used to determine which 90132718Skan/// ModR/M values are valid for a particular instruction. These are used to 9118334Speter/// populate ModRMDecisions. 9290075Sobrien/// X86RecognizableInstr.h contains the interface for a single instruction, 9390075Sobrien/// which knows how to translate itself from a CodeGenInstruction and provide 9490075Sobrien/// the information necessary for integration into the tables. 9518334Speter/// X86RecognizableInstr.cpp contains the implementation for a single 9618334Speter/// instruction. 9718334Speter 9850397Sobrienvoid DisassemblerEmitter::run(raw_ostream &OS) { 9918334Speter CodeGenTarget Target(Records); 10018334Speter 10118334Speter OS << "/*===- TableGen'erated file " 102132718Skan << "---------------------------------------*- C -*-===*\n" 103132718Skan << " *\n" 104132718Skan << " * " << Target.getName() << " Disassembler\n" 105132718Skan << " *\n" 106132718Skan << " * Automatically generated file, do not edit!\n" 107132718Skan << " *\n" 108132718Skan << " *===---------------------------------------------------------------" 109132718Skan << "-------===*/\n"; 110132718Skan 111132718Skan // X86 uses a custom disassembler. 112132718Skan if (Target.getName() == "X86") { 113132718Skan DisassemblerTables Tables; 114132718Skan 115132718Skan const std::vector<const CodeGenInstruction*> &numberedInstructions = 116132718Skan Target.getInstructionsByEnumValue(); 117132718Skan 118132718Skan for (unsigned i = 0, e = numberedInstructions.size(); i != e; ++i) 119132718Skan RecognizableInstr::processInstr(Tables, *numberedInstructions[i], i); 120169689Skan 121169689Skan // FIXME: As long as we are using exceptions, might as well drop this to the 122132718Skan // actual conflict site. 123132718Skan if (Tables.hasConflicts()) 12418334Speter throw TGError(Target.getTargetRecord()->getLoc(), 12518334Speter "Primary decode conflict"); 126169689Skan 127169689Skan Tables.emit(OS); 128169689Skan return; 129169689Skan } 130169689Skan 131169689Skan // ARM and Thumb have a CHECK() macro to deal with DecodeStatuses. 132169689Skan if (Target.getName() == "ARM" || 133169689Skan Target.getName() == "Thumb") { 134169689Skan FixedLenDecoderEmitter(Records, 135169689Skan "ARM", 13696263Sobrien "if (!Check(S, ", ")) return MCDisassembler::Fail;", 13718334Speter "S", "MCDisassembler::Fail", 138169689Skan " MCDisassembler::DecodeStatus S = MCDisassembler::Success;\n(void)S;").run(OS); 139169689Skan return; 140169689Skan } 141169689Skan 142169689Skan FixedLenDecoderEmitter(Records, Target.getName()).run(OS); 143169689Skan} 144169689Skan