DisassemblerEmitter.cpp revision 205407
1199989Srdivacky//===- DisassemblerEmitter.cpp - Generate a disassembler ------------------===// 2199989Srdivacky// 3199989Srdivacky// The LLVM Compiler Infrastructure 4199989Srdivacky// 5199989Srdivacky// This file is distributed under the University of Illinois Open Source 6199989Srdivacky// License. See LICENSE.TXT for details. 7199989Srdivacky// 8199989Srdivacky//===----------------------------------------------------------------------===// 9199989Srdivacky 10199989Srdivacky#include "DisassemblerEmitter.h" 11199989Srdivacky#include "CodeGenTarget.h" 12199989Srdivacky#include "Record.h" 13201360Srdivacky#include "X86DisassemblerTables.h" 14201360Srdivacky#include "X86RecognizableInstr.h" 15199989Srdivackyusing namespace llvm; 16201360Srdivackyusing namespace llvm::X86Disassembler; 17199989Srdivacky 18201360Srdivacky/// DisassemblerEmitter - Contains disassembler table emitters for various 19201360Srdivacky/// architectures. 20201360Srdivacky 21201360Srdivacky/// X86 Disassembler Emitter 22201360Srdivacky/// 23201360Srdivacky/// *** IF YOU'RE HERE TO RESOLVE A "Primary decode conflict", LOOK DOWN NEAR 24201360Srdivacky/// THE END OF THIS COMMENT! 25201360Srdivacky/// 26201360Srdivacky/// The X86 disassembler emitter is part of the X86 Disassembler, which is 27201360Srdivacky/// documented in lib/Target/X86/X86Disassembler.h. 28201360Srdivacky/// 29201360Srdivacky/// The emitter produces the tables that the disassembler uses to translate 30201360Srdivacky/// instructions. The emitter generates the following tables: 31201360Srdivacky/// 32201360Srdivacky/// - One table (CONTEXTS_SYM) that contains a mapping of attribute masks to 33201360Srdivacky/// instruction contexts. Although for each attribute there are cases where 34201360Srdivacky/// that attribute determines decoding, in the majority of cases decoding is 35201360Srdivacky/// the same whether or not an attribute is present. For example, a 64-bit 36201360Srdivacky/// instruction with an OPSIZE prefix and an XS prefix decodes the same way in 37201360Srdivacky/// all cases as a 64-bit instruction with only OPSIZE set. (The XS prefix 38201360Srdivacky/// may have effects on its execution, but does not change the instruction 39201360Srdivacky/// returned.) This allows considerable space savings in other tables. 40201360Srdivacky/// - Four tables (ONEBYTE_SYM, TWOBYTE_SYM, THREEBYTE38_SYM, and 41201360Srdivacky/// THREEBYTE3A_SYM) contain the hierarchy that the decoder traverses while 42201360Srdivacky/// decoding an instruction. At the lowest level of this hierarchy are 43201360Srdivacky/// instruction UIDs, 16-bit integers that can be used to uniquely identify 44201360Srdivacky/// the instruction and correspond exactly to its position in the list of 45201360Srdivacky/// CodeGenInstructions for the target. 46201360Srdivacky/// - One table (INSTRUCTIONS_SYM) contains information about the operands of 47201360Srdivacky/// each instruction and how to decode them. 48201360Srdivacky/// 49201360Srdivacky/// During table generation, there may be conflicts between instructions that 50201360Srdivacky/// occupy the same space in the decode tables. These conflicts are resolved as 51201360Srdivacky/// follows in setTableFields() (X86DisassemblerTables.cpp) 52201360Srdivacky/// 53201360Srdivacky/// - If the current context is the native context for one of the instructions 54201360Srdivacky/// (that is, the attributes specified for it in the LLVM tables specify 55201360Srdivacky/// precisely the current context), then it has priority. 56201360Srdivacky/// - If the current context isn't native for either of the instructions, then 57201360Srdivacky/// the higher-priority context wins (that is, the one that is more specific). 58201360Srdivacky/// That hierarchy is determined by outranks() (X86DisassemblerTables.cpp) 59201360Srdivacky/// - If the current context is native for both instructions, then the table 60201360Srdivacky/// emitter reports a conflict and dies. 61201360Srdivacky/// 62201360Srdivacky/// *** RESOLUTION FOR "Primary decode conflict"S 63201360Srdivacky/// 64201360Srdivacky/// If two instructions collide, typically the solution is (in order of 65201360Srdivacky/// likelihood): 66201360Srdivacky/// 67201360Srdivacky/// (1) to filter out one of the instructions by editing filter() 68201360Srdivacky/// (X86RecognizableInstr.cpp). This is the most common resolution, but 69201360Srdivacky/// check the Intel manuals first to make sure that (2) and (3) are not the 70201360Srdivacky/// problem. 71201360Srdivacky/// (2) to fix the tables (X86.td and its subsidiaries) so the opcodes are 72201360Srdivacky/// accurate. Sometimes they are not. 73201360Srdivacky/// (3) to fix the tables to reflect the actual context (for example, required 74201360Srdivacky/// prefixes), and possibly to add a new context by editing 75201360Srdivacky/// lib/Target/X86/X86DisassemblerDecoderCommon.h. This is unlikely to be 76201360Srdivacky/// the cause. 77201360Srdivacky/// 78201360Srdivacky/// DisassemblerEmitter.cpp contains the implementation for the emitter, 79201360Srdivacky/// which simply pulls out instructions from the CodeGenTarget and pushes them 80201360Srdivacky/// into X86DisassemblerTables. 81201360Srdivacky/// X86DisassemblerTables.h contains the interface for the instruction tables, 82201360Srdivacky/// which manage and emit the structures discussed above. 83201360Srdivacky/// X86DisassemblerTables.cpp contains the implementation for the instruction 84201360Srdivacky/// tables. 85201360Srdivacky/// X86ModRMFilters.h contains filters that can be used to determine which 86201360Srdivacky/// ModR/M values are valid for a particular instruction. These are used to 87201360Srdivacky/// populate ModRMDecisions. 88201360Srdivacky/// X86RecognizableInstr.h contains the interface for a single instruction, 89201360Srdivacky/// which knows how to translate itself from a CodeGenInstruction and provide 90201360Srdivacky/// the information necessary for integration into the tables. 91201360Srdivacky/// X86RecognizableInstr.cpp contains the implementation for a single 92201360Srdivacky/// instruction. 93201360Srdivacky 94199989Srdivackyvoid DisassemblerEmitter::run(raw_ostream &OS) { 95199989Srdivacky CodeGenTarget Target; 96199989Srdivacky 97199989Srdivacky OS << "/*===- TableGen'erated file " 98199989Srdivacky << "---------------------------------------*- C -*-===*\n" 99199989Srdivacky << " *\n" 100199989Srdivacky << " * " << Target.getName() << " Disassembler\n" 101199989Srdivacky << " *\n" 102199989Srdivacky << " * Automatically generated file, do not edit!\n" 103199989Srdivacky << " *\n" 104199989Srdivacky << " *===---------------------------------------------------------------" 105199989Srdivacky << "-------===*/\n"; 106199989Srdivacky 107201360Srdivacky // X86 uses a custom disassembler. 108201360Srdivacky if (Target.getName() == "X86") { 109201360Srdivacky DisassemblerTables Tables; 110201360Srdivacky 111205407Srdivacky const std::vector<const CodeGenInstruction*> &numberedInstructions = 112205407Srdivacky Target.getInstructionsByEnumValue(); 113201360Srdivacky 114201360Srdivacky for (unsigned i = 0, e = numberedInstructions.size(); i != e; ++i) 115201360Srdivacky RecognizableInstr::processInstr(Tables, *numberedInstructions[i], i); 116201360Srdivacky 117201360Srdivacky // FIXME: As long as we are using exceptions, might as well drop this to the 118201360Srdivacky // actual conflict site. 119201360Srdivacky if (Tables.hasConflicts()) 120201360Srdivacky throw TGError(Target.getTargetRecord()->getLoc(), 121201360Srdivacky "Primary decode conflict"); 122201360Srdivacky 123201360Srdivacky Tables.emit(OS); 124201360Srdivacky return; 125201360Srdivacky } 126201360Srdivacky 127199989Srdivacky throw TGError(Target.getTargetRecord()->getLoc(), 128199989Srdivacky "Unable to generate disassembler for this target"); 129199989Srdivacky} 130