XCoreInstrInfo.td revision 204642
1//===- XCoreInstrInfo.td - Target Description for XCore ----*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the XCore instructions in TableGen format. 11// 12//===----------------------------------------------------------------------===// 13 14// Uses of CP, DP are not currently reflected in the patterns, since 15// having a physical register as an operand prevents loop hoisting and 16// since the value of these registers never changes during the life of the 17// function. 18 19//===----------------------------------------------------------------------===// 20// Instruction format superclass. 21//===----------------------------------------------------------------------===// 22 23include "XCoreInstrFormats.td" 24 25//===----------------------------------------------------------------------===// 26// XCore specific DAG Nodes. 27// 28 29// Call 30def SDT_XCoreBranchLink : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>; 31def XCoreBranchLink : SDNode<"XCoreISD::BL",SDT_XCoreBranchLink, 32 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>; 33 34def XCoreRetsp : SDNode<"XCoreISD::RETSP", SDTNone, 35 [SDNPHasChain, SDNPOptInFlag]>; 36 37def SDT_XCoreBR_JT : SDTypeProfile<0, 2, 38 [SDTCisVT<0, i32>, SDTCisVT<1, i32>]>; 39 40def XCoreBR_JT : SDNode<"XCoreISD::BR_JT", SDT_XCoreBR_JT, 41 [SDNPHasChain]>; 42 43def XCoreBR_JT32 : SDNode<"XCoreISD::BR_JT32", SDT_XCoreBR_JT, 44 [SDNPHasChain]>; 45 46def SDT_XCoreAddress : SDTypeProfile<1, 1, 47 [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>; 48 49def pcrelwrapper : SDNode<"XCoreISD::PCRelativeWrapper", SDT_XCoreAddress, 50 []>; 51 52def dprelwrapper : SDNode<"XCoreISD::DPRelativeWrapper", SDT_XCoreAddress, 53 []>; 54 55def cprelwrapper : SDNode<"XCoreISD::CPRelativeWrapper", SDT_XCoreAddress, 56 []>; 57 58def SDT_XCoreStwsp : SDTypeProfile<0, 2, [SDTCisInt<1>]>; 59def XCoreStwsp : SDNode<"XCoreISD::STWSP", SDT_XCoreStwsp, 60 [SDNPHasChain]>; 61 62// These are target-independent nodes, but have target-specific formats. 63def SDT_XCoreCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>; 64def SDT_XCoreCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, 65 SDTCisVT<1, i32> ]>; 66 67def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_XCoreCallSeqStart, 68 [SDNPHasChain, SDNPOutFlag]>; 69def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_XCoreCallSeqEnd, 70 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>; 71 72//===----------------------------------------------------------------------===// 73// Instruction Pattern Stuff 74//===----------------------------------------------------------------------===// 75 76def div4_xform : SDNodeXForm<imm, [{ 77 // Transformation function: imm/4 78 assert(N->getZExtValue() % 4 == 0); 79 return getI32Imm(N->getZExtValue()/4); 80}]>; 81 82def msksize_xform : SDNodeXForm<imm, [{ 83 // Transformation function: get the size of a mask 84 assert(isMask_32(N->getZExtValue())); 85 // look for the first non-zero bit 86 return getI32Imm(32 - CountLeadingZeros_32(N->getZExtValue())); 87}]>; 88 89def neg_xform : SDNodeXForm<imm, [{ 90 // Transformation function: -imm 91 uint32_t value = N->getZExtValue(); 92 return getI32Imm(-value); 93}]>; 94 95def bpwsub_xform : SDNodeXForm<imm, [{ 96 // Transformation function: 32-imm 97 uint32_t value = N->getZExtValue(); 98 return getI32Imm(32-value); 99}]>; 100 101def div4neg_xform : SDNodeXForm<imm, [{ 102 // Transformation function: -imm/4 103 uint32_t value = N->getZExtValue(); 104 assert(-value % 4 == 0); 105 return getI32Imm(-value/4); 106}]>; 107 108def immUs4Neg : PatLeaf<(imm), [{ 109 uint32_t value = (uint32_t)N->getZExtValue(); 110 return (-value)%4 == 0 && (-value)/4 <= 11; 111}]>; 112 113def immUs4 : PatLeaf<(imm), [{ 114 uint32_t value = (uint32_t)N->getZExtValue(); 115 return value%4 == 0 && value/4 <= 11; 116}]>; 117 118def immUsNeg : PatLeaf<(imm), [{ 119 return -((uint32_t)N->getZExtValue()) <= 11; 120}]>; 121 122def immUs : PatLeaf<(imm), [{ 123 return (uint32_t)N->getZExtValue() <= 11; 124}]>; 125 126def immU6 : PatLeaf<(imm), [{ 127 return (uint32_t)N->getZExtValue() < (1 << 6); 128}]>; 129 130def immU10 : PatLeaf<(imm), [{ 131 return (uint32_t)N->getZExtValue() < (1 << 10); 132}]>; 133 134def immU16 : PatLeaf<(imm), [{ 135 return (uint32_t)N->getZExtValue() < (1 << 16); 136}]>; 137 138def immU20 : PatLeaf<(imm), [{ 139 return (uint32_t)N->getZExtValue() < (1 << 20); 140}]>; 141 142def immMskBitp : PatLeaf<(imm), [{ 143 uint32_t value = (uint32_t)N->getZExtValue(); 144 if (!isMask_32(value)) { 145 return false; 146 } 147 int msksize = 32 - CountLeadingZeros_32(value); 148 return (msksize >= 1 && msksize <= 8) 149 || msksize == 16 150 || msksize == 24 151 || msksize == 32; 152}]>; 153 154def immBitp : PatLeaf<(imm), [{ 155 uint32_t value = (uint32_t)N->getZExtValue(); 156 return (value >= 1 && value <= 8) 157 || value == 16 158 || value == 24 159 || value == 32; 160}]>; 161 162def immBpwSubBitp : PatLeaf<(imm), [{ 163 uint32_t value = (uint32_t)N->getZExtValue(); 164 return (value >= 24 && value <= 31) 165 || value == 16 166 || value == 8 167 || value == 0; 168}]>; 169 170def lda16f : PatFrag<(ops node:$addr, node:$offset), 171 (add node:$addr, (shl node:$offset, 1))>; 172def lda16b : PatFrag<(ops node:$addr, node:$offset), 173 (sub node:$addr, (shl node:$offset, 1))>; 174def ldawf : PatFrag<(ops node:$addr, node:$offset), 175 (add node:$addr, (shl node:$offset, 2))>; 176def ldawb : PatFrag<(ops node:$addr, node:$offset), 177 (sub node:$addr, (shl node:$offset, 2))>; 178 179// Instruction operand types 180def calltarget : Operand<i32>; 181def brtarget : Operand<OtherVT>; 182def pclabel : Operand<i32>; 183 184// Addressing modes 185def ADDRspii : ComplexPattern<i32, 2, "SelectADDRspii", [add, frameindex], []>; 186def ADDRdpii : ComplexPattern<i32, 2, "SelectADDRdpii", [add, dprelwrapper], 187 []>; 188def ADDRcpii : ComplexPattern<i32, 2, "SelectADDRcpii", [add, cprelwrapper], 189 []>; 190 191// Address operands 192def MEMii : Operand<i32> { 193 let PrintMethod = "printMemOperand"; 194 let MIOperandInfo = (ops i32imm, i32imm); 195} 196 197// Jump tables. 198def InlineJT : Operand<i32> { 199 let PrintMethod = "printInlineJT"; 200} 201 202def InlineJT32 : Operand<i32> { 203 let PrintMethod = "printInlineJT32"; 204} 205 206//===----------------------------------------------------------------------===// 207// Instruction Class Templates 208//===----------------------------------------------------------------------===// 209 210// Three operand short 211 212multiclass F3R_2RUS<string OpcStr, SDNode OpNode> { 213 def _3r: _F3R< 214 (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), 215 !strconcat(OpcStr, " $dst, $b, $c"), 216 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>; 217 def _2rus : _F2RUS< 218 (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c), 219 !strconcat(OpcStr, " $dst, $b, $c"), 220 [(set GRRegs:$dst, (OpNode GRRegs:$b, immUs:$c))]>; 221} 222 223multiclass F3R_2RUS_np<string OpcStr> { 224 def _3r: _F3R< 225 (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), 226 !strconcat(OpcStr, " $dst, $b, $c"), 227 []>; 228 def _2rus : _F2RUS< 229 (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c), 230 !strconcat(OpcStr, " $dst, $b, $c"), 231 []>; 232} 233 234multiclass F3R_2RBITP<string OpcStr, SDNode OpNode> { 235 def _3r: _F3R< 236 (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), 237 !strconcat(OpcStr, " $dst, $b, $c"), 238 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>; 239 def _2rus : _F2RUS< 240 (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c), 241 !strconcat(OpcStr, " $dst, $b, $c"), 242 [(set GRRegs:$dst, (OpNode GRRegs:$b, immBitp:$c))]>; 243} 244 245class F3R<string OpcStr, SDNode OpNode> : _F3R< 246 (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), 247 !strconcat(OpcStr, " $dst, $b, $c"), 248 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>; 249 250class F3R_np<string OpcStr> : _F3R< 251 (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), 252 !strconcat(OpcStr, " $dst, $b, $c"), 253 []>; 254// Three operand long 255 256/// FL3R_L2RUS multiclass - Define a normal FL3R/FL2RUS pattern in one shot. 257multiclass FL3R_L2RUS<string OpcStr, SDNode OpNode> { 258 def _l3r: _FL3R< 259 (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), 260 !strconcat(OpcStr, " $dst, $b, $c"), 261 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>; 262 def _l2rus : _FL2RUS< 263 (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c), 264 !strconcat(OpcStr, " $dst, $b, $c"), 265 [(set GRRegs:$dst, (OpNode GRRegs:$b, immUs:$c))]>; 266} 267 268/// FL3R_L2RUS multiclass - Define a normal FL3R/FL2RUS pattern in one shot. 269multiclass FL3R_L2RBITP<string OpcStr, SDNode OpNode> { 270 def _l3r: _FL3R< 271 (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), 272 !strconcat(OpcStr, " $dst, $b, $c"), 273 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>; 274 def _l2rus : _FL2RUS< 275 (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c), 276 !strconcat(OpcStr, " $dst, $b, $c"), 277 [(set GRRegs:$dst, (OpNode GRRegs:$b, immBitp:$c))]>; 278} 279 280class FL3R<string OpcStr, SDNode OpNode> : _FL3R< 281 (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), 282 !strconcat(OpcStr, " $dst, $b, $c"), 283 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>; 284 285// Register - U6 286// Operand register - U6 287multiclass FRU6_LRU6_branch<string OpcStr> { 288 def _ru6: _FRU6< 289 (outs), (ins GRRegs:$cond, brtarget:$dest), 290 !strconcat(OpcStr, " $cond, $dest"), 291 []>; 292 def _lru6: _FLRU6< 293 (outs), (ins GRRegs:$cond, brtarget:$dest), 294 !strconcat(OpcStr, " $cond, $dest"), 295 []>; 296} 297 298multiclass FRU6_LRU6_cp<string OpcStr> { 299 def _ru6: _FRU6< 300 (outs GRRegs:$dst), (ins i32imm:$a), 301 !strconcat(OpcStr, " $dst, cp[$a]"), 302 []>; 303 def _lru6: _FLRU6< 304 (outs GRRegs:$dst), (ins i32imm:$a), 305 !strconcat(OpcStr, " $dst, cp[$a]"), 306 []>; 307} 308 309// U6 310multiclass FU6_LU6<string OpcStr, SDNode OpNode> { 311 def _u6: _FU6< 312 (outs), (ins i32imm:$b), 313 !strconcat(OpcStr, " $b"), 314 [(OpNode immU6:$b)]>; 315 def _lu6: _FLU6< 316 (outs), (ins i32imm:$b), 317 !strconcat(OpcStr, " $b"), 318 [(OpNode immU16:$b)]>; 319} 320 321multiclass FU6_LU6_np<string OpcStr> { 322 def _u6: _FU6< 323 (outs), (ins i32imm:$b), 324 !strconcat(OpcStr, " $b"), 325 []>; 326 def _lu6: _FLU6< 327 (outs), (ins i32imm:$b), 328 !strconcat(OpcStr, " $b"), 329 []>; 330} 331 332// U10 333multiclass FU10_LU10_np<string OpcStr> { 334 def _u10: _FU10< 335 (outs), (ins i32imm:$b), 336 !strconcat(OpcStr, " $b"), 337 []>; 338 def _lu10: _FLU10< 339 (outs), (ins i32imm:$b), 340 !strconcat(OpcStr, " $b"), 341 []>; 342} 343 344// Two operand short 345 346class F2R_np<string OpcStr> : _F2R< 347 (outs GRRegs:$dst), (ins GRRegs:$b), 348 !strconcat(OpcStr, " $dst, $b"), 349 []>; 350 351// Two operand long 352 353//===----------------------------------------------------------------------===// 354// Pseudo Instructions 355//===----------------------------------------------------------------------===// 356 357let Defs = [SP], Uses = [SP] in { 358def ADJCALLSTACKDOWN : PseudoInstXCore<(outs), (ins i32imm:$amt), 359 "${:comment} ADJCALLSTACKDOWN $amt", 360 [(callseq_start timm:$amt)]>; 361def ADJCALLSTACKUP : PseudoInstXCore<(outs), (ins i32imm:$amt1, i32imm:$amt2), 362 "${:comment} ADJCALLSTACKUP $amt1", 363 [(callseq_end timm:$amt1, timm:$amt2)]>; 364} 365 366def LDWFI : PseudoInstXCore<(outs GRRegs:$dst), (ins MEMii:$addr), 367 "${:comment} LDWFI $dst, $addr", 368 [(set GRRegs:$dst, (load ADDRspii:$addr))]>; 369 370def LDAWFI : PseudoInstXCore<(outs GRRegs:$dst), (ins MEMii:$addr), 371 "${:comment} LDAWFI $dst, $addr", 372 [(set GRRegs:$dst, ADDRspii:$addr)]>; 373 374def STWFI : PseudoInstXCore<(outs), (ins GRRegs:$src, MEMii:$addr), 375 "${:comment} STWFI $src, $addr", 376 [(store GRRegs:$src, ADDRspii:$addr)]>; 377 378// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after 379// instruction selection into a branch sequence. 380let usesCustomInserter = 1 in { 381 def SELECT_CC : PseudoInstXCore<(outs GRRegs:$dst), 382 (ins GRRegs:$cond, GRRegs:$T, GRRegs:$F), 383 "${:comment} SELECT_CC PSEUDO!", 384 [(set GRRegs:$dst, 385 (select GRRegs:$cond, GRRegs:$T, GRRegs:$F))]>; 386} 387 388//===----------------------------------------------------------------------===// 389// Instructions 390//===----------------------------------------------------------------------===// 391 392// Three operand short 393defm ADD : F3R_2RUS<"add", add>; 394defm SUB : F3R_2RUS<"sub", sub>; 395let neverHasSideEffects = 1 in { 396defm EQ : F3R_2RUS_np<"eq">; 397def LSS_3r : F3R_np<"lss">; 398def LSU_3r : F3R_np<"lsu">; 399} 400def AND_3r : F3R<"and", and>; 401def OR_3r : F3R<"or", or>; 402 403let mayLoad=1 in { 404def LDW_3r : _F3R<(outs GRRegs:$dst), (ins GRRegs:$addr, GRRegs:$offset), 405 "ldw $dst, $addr[$offset]", 406 []>; 407 408def LDW_2rus : _F2RUS<(outs GRRegs:$dst), (ins GRRegs:$addr, i32imm:$offset), 409 "ldw $dst, $addr[$offset]", 410 []>; 411 412def LD16S_3r : _F3R<(outs GRRegs:$dst), (ins GRRegs:$addr, GRRegs:$offset), 413 "ld16s $dst, $addr[$offset]", 414 []>; 415 416def LD8U_3r : _F3R<(outs GRRegs:$dst), (ins GRRegs:$addr, GRRegs:$offset), 417 "ld8u $dst, $addr[$offset]", 418 []>; 419} 420 421let mayStore=1 in { 422def STW_3r : _F3R<(outs), (ins GRRegs:$val, GRRegs:$addr, GRRegs:$offset), 423 "stw $val, $addr[$offset]", 424 []>; 425 426def STW_2rus : _F2RUS<(outs), (ins GRRegs:$val, GRRegs:$addr, i32imm:$offset), 427 "stw $val, $addr[$offset]", 428 []>; 429} 430 431defm SHL : F3R_2RBITP<"shl", shl>; 432defm SHR : F3R_2RBITP<"shr", srl>; 433// TODO tsetr 434 435// Three operand long 436def LDAWF_l3r : _FL3R<(outs GRRegs:$dst), (ins GRRegs:$addr, GRRegs:$offset), 437 "ldaw $dst, $addr[$offset]", 438 [(set GRRegs:$dst, (ldawf GRRegs:$addr, GRRegs:$offset))]>; 439 440let neverHasSideEffects = 1 in 441def LDAWF_l2rus : _FL2RUS<(outs GRRegs:$dst), 442 (ins GRRegs:$addr, i32imm:$offset), 443 "ldaw $dst, $addr[$offset]", 444 []>; 445 446def LDAWB_l3r : _FL3R<(outs GRRegs:$dst), (ins GRRegs:$addr, GRRegs:$offset), 447 "ldaw $dst, $addr[-$offset]", 448 [(set GRRegs:$dst, (ldawb GRRegs:$addr, GRRegs:$offset))]>; 449 450let neverHasSideEffects = 1 in 451def LDAWB_l2rus : _FL2RUS<(outs GRRegs:$dst), 452 (ins GRRegs:$addr, i32imm:$offset), 453 "ldaw $dst, $addr[-$offset]", 454 []>; 455 456def LDA16F_l3r : _FL3R<(outs GRRegs:$dst), (ins GRRegs:$addr, GRRegs:$offset), 457 "lda16 $dst, $addr[$offset]", 458 [(set GRRegs:$dst, (lda16f GRRegs:$addr, GRRegs:$offset))]>; 459 460def LDA16B_l3r : _FL3R<(outs GRRegs:$dst), (ins GRRegs:$addr, GRRegs:$offset), 461 "lda16 $dst, $addr[-$offset]", 462 [(set GRRegs:$dst, (lda16b GRRegs:$addr, GRRegs:$offset))]>; 463 464def MUL_l3r : FL3R<"mul", mul>; 465// Instructions which may trap are marked as side effecting. 466let hasSideEffects = 1 in { 467def DIVS_l3r : FL3R<"divs", sdiv>; 468def DIVU_l3r : FL3R<"divu", udiv>; 469def REMS_l3r : FL3R<"rems", srem>; 470def REMU_l3r : FL3R<"remu", urem>; 471} 472def XOR_l3r : FL3R<"xor", xor>; 473defm ASHR : FL3R_L2RBITP<"ashr", sra>; 474// TODO crc32, crc8, inpw, outpw 475let mayStore=1 in { 476def ST16_l3r : _FL3R<(outs), (ins GRRegs:$val, GRRegs:$addr, GRRegs:$offset), 477 "st16 $val, $addr[$offset]", 478 []>; 479 480def ST8_l3r : _FL3R<(outs), (ins GRRegs:$val, GRRegs:$addr, GRRegs:$offset), 481 "st8 $val, $addr[$offset]", 482 []>; 483} 484 485// Four operand long 486let Constraints = "$src1 = $dst1,$src2 = $dst2" in { 487def MACCU_l4r : _L4R<(outs GRRegs:$dst1, GRRegs:$dst2), 488 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3, 489 GRRegs:$src4), 490 "maccu $dst1, $dst2, $src3, $src4", 491 []>; 492 493def MACCS_l4r : _L4R<(outs GRRegs:$dst1, GRRegs:$dst2), 494 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3, 495 GRRegs:$src4), 496 "maccs $dst1, $dst2, $src3, $src4", 497 []>; 498} 499 500// Five operand long 501 502def LADD_l5r : _L5R<(outs GRRegs:$dst1, GRRegs:$dst2), 503 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3), 504 "ladd $dst1, $dst2, $src1, $src2, $src3", 505 []>; 506 507def LSUB_l5r : _L5R<(outs GRRegs:$dst1, GRRegs:$dst2), 508 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3), 509 "lsub $dst1, $dst2, $src1, $src2, $src3", 510 []>; 511 512def LDIV_l5r : _L5R<(outs GRRegs:$dst1, GRRegs:$dst2), 513 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3), 514 "ldiv $dst1, $dst2, $src1, $src2, $src3", 515 []>; 516 517// Six operand long 518 519def LMUL_l6r : _L6R<(outs GRRegs:$dst1, GRRegs:$dst2), 520 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3, 521 GRRegs:$src4), 522 "lmul $dst1, $dst2, $src1, $src2, $src3, $src4", 523 []>; 524 525// Register - U6 526 527//let Uses = [DP] in ... 528let neverHasSideEffects = 1, isReMaterializable = 1 in 529def LDAWDP_ru6: _FRU6<(outs GRRegs:$dst), (ins MEMii:$a), 530 "ldaw $dst, dp[$a]", 531 []>; 532 533let isReMaterializable = 1 in 534def LDAWDP_lru6: _FLRU6< 535 (outs GRRegs:$dst), (ins MEMii:$a), 536 "ldaw $dst, dp[$a]", 537 [(set GRRegs:$dst, ADDRdpii:$a)]>; 538 539let mayLoad=1 in 540def LDWDP_ru6: _FRU6<(outs GRRegs:$dst), (ins MEMii:$a), 541 "ldw $dst, dp[$a]", 542 []>; 543 544def LDWDP_lru6: _FLRU6< 545 (outs GRRegs:$dst), (ins MEMii:$a), 546 "ldw $dst, dp[$a]", 547 [(set GRRegs:$dst, (load ADDRdpii:$a))]>; 548 549let mayStore=1 in 550def STWDP_ru6 : _FRU6<(outs), (ins GRRegs:$val, MEMii:$addr), 551 "stw $val, dp[$addr]", 552 []>; 553 554def STWDP_lru6 : _FLRU6<(outs), (ins GRRegs:$val, MEMii:$addr), 555 "stw $val, dp[$addr]", 556 [(store GRRegs:$val, ADDRdpii:$addr)]>; 557 558//let Uses = [CP] in .. 559let mayLoad = 1, isReMaterializable = 1 in 560defm LDWCP : FRU6_LRU6_cp<"ldw">; 561 562let Uses = [SP] in { 563let mayStore=1 in { 564def STWSP_ru6 : _FRU6< 565 (outs), (ins GRRegs:$val, i32imm:$index), 566 "stw $val, sp[$index]", 567 [(XCoreStwsp GRRegs:$val, immU6:$index)]>; 568 569def STWSP_lru6 : _FLRU6< 570 (outs), (ins GRRegs:$val, i32imm:$index), 571 "stw $val, sp[$index]", 572 [(XCoreStwsp GRRegs:$val, immU16:$index)]>; 573} 574 575let mayLoad=1 in { 576def LDWSP_ru6 : _FRU6< 577 (outs GRRegs:$dst), (ins i32imm:$b), 578 "ldw $dst, sp[$b]", 579 []>; 580 581def LDWSP_lru6 : _FLRU6< 582 (outs GRRegs:$dst), (ins i32imm:$b), 583 "ldw $dst, sp[$b]", 584 []>; 585} 586 587let neverHasSideEffects = 1 in { 588def LDAWSP_ru6 : _FRU6< 589 (outs GRRegs:$dst), (ins i32imm:$b), 590 "ldaw $dst, sp[$b]", 591 []>; 592 593def LDAWSP_lru6 : _FLRU6< 594 (outs GRRegs:$dst), (ins i32imm:$b), 595 "ldaw $dst, sp[$b]", 596 []>; 597 598def LDAWSP_ru6_RRegs : _FRU6< 599 (outs RRegs:$dst), (ins i32imm:$b), 600 "ldaw $dst, sp[$b]", 601 []>; 602 603def LDAWSP_lru6_RRegs : _FLRU6< 604 (outs RRegs:$dst), (ins i32imm:$b), 605 "ldaw $dst, sp[$b]", 606 []>; 607} 608} 609 610let isReMaterializable = 1 in { 611def LDC_ru6 : _FRU6< 612 (outs GRRegs:$dst), (ins i32imm:$b), 613 "ldc $dst, $b", 614 [(set GRRegs:$dst, immU6:$b)]>; 615 616def LDC_lru6 : _FLRU6< 617 (outs GRRegs:$dst), (ins i32imm:$b), 618 "ldc $dst, $b", 619 [(set GRRegs:$dst, immU16:$b)]>; 620} 621 622// Operand register - U6 623// TODO setc 624let isBranch = 1, isTerminator = 1 in { 625defm BRFT: FRU6_LRU6_branch<"bt">; 626defm BRBT: FRU6_LRU6_branch<"bt">; 627defm BRFF: FRU6_LRU6_branch<"bf">; 628defm BRBF: FRU6_LRU6_branch<"bf">; 629} 630 631// U6 632let Defs = [SP], Uses = [SP] in { 633let neverHasSideEffects = 1 in 634defm EXTSP : FU6_LU6_np<"extsp">; 635let mayStore = 1 in 636defm ENTSP : FU6_LU6_np<"entsp">; 637 638let isReturn = 1, isTerminator = 1, mayLoad = 1, isBarrier = 1 in { 639defm RETSP : FU6_LU6<"retsp", XCoreRetsp>; 640} 641} 642 643// TODO extdp, kentsp, krestsp, blat, setsr 644// clrsr, getsr, kalli 645let isBranch = 1, isTerminator = 1, isBarrier = 1 in { 646def BRBU_u6 : _FU6< 647 (outs), 648 (ins brtarget:$target), 649 "bu $target", 650 []>; 651 652def BRBU_lu6 : _FLU6< 653 (outs), 654 (ins brtarget:$target), 655 "bu $target", 656 []>; 657 658def BRFU_u6 : _FU6< 659 (outs), 660 (ins brtarget:$target), 661 "bu $target", 662 []>; 663 664def BRFU_lu6 : _FLU6< 665 (outs), 666 (ins brtarget:$target), 667 "bu $target", 668 []>; 669} 670 671//let Uses = [CP] in ... 672let Defs = [R11], neverHasSideEffects = 1, isReMaterializable = 1 in 673def LDAWCP_u6: _FRU6<(outs), (ins MEMii:$a), 674 "ldaw r11, cp[$a]", 675 []>; 676 677let Defs = [R11], isReMaterializable = 1 in 678def LDAWCP_lu6: _FLRU6< 679 (outs), (ins MEMii:$a), 680 "ldaw r11, cp[$a]", 681 [(set R11, ADDRcpii:$a)]>; 682 683// U10 684// TODO ldwcpl, blacp 685 686let Defs = [R11], isReMaterializable = 1, neverHasSideEffects = 1 in 687def LDAP_u10 : _FU10< 688 (outs), 689 (ins i32imm:$addr), 690 "ldap r11, $addr", 691 []>; 692 693let Defs = [R11], isReMaterializable = 1 in 694def LDAP_lu10 : _FLU10< 695 (outs), 696 (ins i32imm:$addr), 697 "ldap r11, $addr", 698 [(set R11, (pcrelwrapper tglobaladdr:$addr))]>; 699 700let Defs = [R11], isReMaterializable = 1 in 701def LDAP_lu10_ba : _FLU10<(outs), 702 (ins i32imm:$addr), 703 "ldap r11, $addr", 704 [(set R11, (pcrelwrapper tblockaddress:$addr))]>; 705 706let isCall=1, 707// All calls clobber the link register and the non-callee-saved registers: 708Defs = [R0, R1, R2, R3, R11, LR] in { 709def BL_u10 : _FU10< 710 (outs), 711 (ins calltarget:$target, variable_ops), 712 "bl $target", 713 [(XCoreBranchLink immU10:$target)]>; 714 715def BL_lu10 : _FLU10< 716 (outs), 717 (ins calltarget:$target, variable_ops), 718 "bl $target", 719 [(XCoreBranchLink immU20:$target)]>; 720} 721 722// Two operand short 723// TODO getr, getst 724def NOT : _F2R<(outs GRRegs:$dst), (ins GRRegs:$b), 725 "not $dst, $b", 726 [(set GRRegs:$dst, (not GRRegs:$b))]>; 727 728def NEG : _F2R<(outs GRRegs:$dst), (ins GRRegs:$b), 729 "neg $dst, $b", 730 [(set GRRegs:$dst, (ineg GRRegs:$b))]>; 731 732// TODO setd, eet, eef, getts, setpt, outct, inct, chkct, outt, intt, out, 733// in, outshr, inshr, testct, testwct, tinitpc, tinitdp, tinitsp, tinitcp, 734// tsetmr, sext (reg), zext (reg) 735let isTwoAddress = 1 in { 736let neverHasSideEffects = 1 in 737def SEXT_rus : _FRUS<(outs GRRegs:$dst), (ins GRRegs:$src1, i32imm:$src2), 738 "sext $dst, $src2", 739 []>; 740 741let neverHasSideEffects = 1 in 742def ZEXT_rus : _FRUS<(outs GRRegs:$dst), (ins GRRegs:$src1, i32imm:$src2), 743 "zext $dst, $src2", 744 []>; 745 746def ANDNOT_2r : _F2R<(outs GRRegs:$dst), (ins GRRegs:$src1, GRRegs:$src2), 747 "andnot $dst, $src2", 748 [(set GRRegs:$dst, (and GRRegs:$src1, (not GRRegs:$src2)))]>; 749} 750 751let isReMaterializable = 1, neverHasSideEffects = 1 in 752def MKMSK_rus : _FRUS<(outs GRRegs:$dst), (ins i32imm:$size), 753 "mkmsk $dst, $size", 754 []>; 755 756def MKMSK_2r : _FRUS<(outs GRRegs:$dst), (ins GRRegs:$size), 757 "mkmsk $dst, $size", 758 [(set GRRegs:$dst, (add (shl 1, GRRegs:$size), 0xffffffff))]>; 759 760// Two operand long 761// TODO settw, setclk, setrdy, setpsc, endin, peek, 762// getd, testlcl, tinitlr, getps, setps 763def BITREV_l2r : _FL2R<(outs GRRegs:$dst), (ins GRRegs:$src), 764 "bitrev $dst, $src", 765 [(set GRRegs:$dst, (int_xcore_bitrev GRRegs:$src))]>; 766 767def BYTEREV_l2r : _FL2R<(outs GRRegs:$dst), (ins GRRegs:$src), 768 "byterev $dst, $src", 769 [(set GRRegs:$dst, (bswap GRRegs:$src))]>; 770 771def CLZ_l2r : _FL2R<(outs GRRegs:$dst), (ins GRRegs:$src), 772 "clz $dst, $src", 773 [(set GRRegs:$dst, (ctlz GRRegs:$src))]>; 774 775// One operand short 776// TODO edu, eeu, waitet, waitef, freer, tstart, msync, mjoin, syncr, clrtp 777// setdp, setcp, setv, setev, kcall 778// dgetreg 779let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in 780def BAU_1r : _F1R<(outs), (ins GRRegs:$addr), 781 "bau $addr", 782 [(brind GRRegs:$addr)]>; 783 784let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in 785def BR_JT : PseudoInstXCore<(outs), (ins InlineJT:$t, GRRegs:$i), 786 "bru $i\n$t", 787 [(XCoreBR_JT tjumptable:$t, GRRegs:$i)]>; 788 789let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in 790def BR_JT32 : PseudoInstXCore<(outs), (ins InlineJT32:$t, GRRegs:$i), 791 "bru $i\n$t", 792 [(XCoreBR_JT32 tjumptable:$t, GRRegs:$i)]>; 793 794let Defs=[SP], neverHasSideEffects=1 in 795def SETSP_1r : _F1R<(outs), (ins GRRegs:$src), 796 "set sp, $src", 797 []>; 798 799let hasCtrlDep = 1 in 800def ECALLT_1r : _F1R<(outs), (ins GRRegs:$src), 801 "ecallt $src", 802 []>; 803 804let hasCtrlDep = 1 in 805def ECALLF_1r : _F1R<(outs), (ins GRRegs:$src), 806 "ecallf $src", 807 []>; 808 809let isCall=1, 810// All calls clobber the link register and the non-callee-saved registers: 811Defs = [R0, R1, R2, R3, R11, LR] in { 812def BLA_1r : _F1R<(outs), (ins GRRegs:$addr, variable_ops), 813 "bla $addr", 814 [(XCoreBranchLink GRRegs:$addr)]>; 815} 816 817// Zero operand short 818// TODO waiteu, clre, ssync, freet, ldspc, stspc, ldssr, stssr, ldsed, stsed, 819// stet, geted, getet, getkep, getksp, setkep, getid, kret, dcall, dret, 820// dentsp, drestsp 821 822let Defs = [R11] in 823def GETID_0R : _F0R<(outs), (ins), 824 "get r11, id", 825 [(set R11, (int_xcore_getid))]>; 826 827//===----------------------------------------------------------------------===// 828// Non-Instruction Patterns 829//===----------------------------------------------------------------------===// 830 831def : Pat<(XCoreBranchLink tglobaladdr:$addr), (BL_lu10 tglobaladdr:$addr)>; 832def : Pat<(XCoreBranchLink texternalsym:$addr), (BL_lu10 texternalsym:$addr)>; 833 834/// sext_inreg 835def : Pat<(sext_inreg GRRegs:$b, i1), (SEXT_rus GRRegs:$b, 1)>; 836def : Pat<(sext_inreg GRRegs:$b, i8), (SEXT_rus GRRegs:$b, 8)>; 837def : Pat<(sext_inreg GRRegs:$b, i16), (SEXT_rus GRRegs:$b, 16)>; 838 839/// loads 840def : Pat<(zextloadi8 (add GRRegs:$addr, GRRegs:$offset)), 841 (LD8U_3r GRRegs:$addr, GRRegs:$offset)>; 842def : Pat<(zextloadi8 GRRegs:$addr), (LD8U_3r GRRegs:$addr, (LDC_ru6 0))>; 843 844def : Pat<(sextloadi16 (lda16f GRRegs:$addr, GRRegs:$offset)), 845 (LD16S_3r GRRegs:$addr, GRRegs:$offset)>; 846def : Pat<(sextloadi16 GRRegs:$addr), (LD16S_3r GRRegs:$addr, (LDC_ru6 0))>; 847 848def : Pat<(load (ldawf GRRegs:$addr, GRRegs:$offset)), 849 (LDW_3r GRRegs:$addr, GRRegs:$offset)>; 850def : Pat<(load (add GRRegs:$addr, immUs4:$offset)), 851 (LDW_2rus GRRegs:$addr, (div4_xform immUs4:$offset))>; 852def : Pat<(load GRRegs:$addr), (LDW_2rus GRRegs:$addr, 0)>; 853 854/// anyext 855def : Pat<(extloadi8 (add GRRegs:$addr, GRRegs:$offset)), 856 (LD8U_3r GRRegs:$addr, GRRegs:$offset)>; 857def : Pat<(extloadi8 GRRegs:$addr), (LD8U_3r GRRegs:$addr, (LDC_ru6 0))>; 858def : Pat<(extloadi16 (lda16f GRRegs:$addr, GRRegs:$offset)), 859 (LD16S_3r GRRegs:$addr, GRRegs:$offset)>; 860def : Pat<(extloadi16 GRRegs:$addr), (LD16S_3r GRRegs:$addr, (LDC_ru6 0))>; 861 862/// stores 863def : Pat<(truncstorei8 GRRegs:$val, (add GRRegs:$addr, GRRegs:$offset)), 864 (ST8_l3r GRRegs:$val, GRRegs:$addr, GRRegs:$offset)>; 865def : Pat<(truncstorei8 GRRegs:$val, GRRegs:$addr), 866 (ST8_l3r GRRegs:$val, GRRegs:$addr, (LDC_ru6 0))>; 867 868def : Pat<(truncstorei16 GRRegs:$val, (lda16f GRRegs:$addr, GRRegs:$offset)), 869 (ST16_l3r GRRegs:$val, GRRegs:$addr, GRRegs:$offset)>; 870def : Pat<(truncstorei16 GRRegs:$val, GRRegs:$addr), 871 (ST16_l3r GRRegs:$val, GRRegs:$addr, (LDC_ru6 0))>; 872 873def : Pat<(store GRRegs:$val, (ldawf GRRegs:$addr, GRRegs:$offset)), 874 (STW_3r GRRegs:$val, GRRegs:$addr, GRRegs:$offset)>; 875def : Pat<(store GRRegs:$val, (add GRRegs:$addr, immUs4:$offset)), 876 (STW_2rus GRRegs:$val, GRRegs:$addr, (div4_xform immUs4:$offset))>; 877def : Pat<(store GRRegs:$val, GRRegs:$addr), 878 (STW_2rus GRRegs:$val, GRRegs:$addr, 0)>; 879 880/// cttz 881def : Pat<(cttz GRRegs:$src), (CLZ_l2r (BITREV_l2r GRRegs:$src))>; 882 883/// trap 884def : Pat<(trap), (ECALLF_1r (LDC_ru6 0))>; 885 886/// 887/// branch patterns 888/// 889 890// unconditional branch 891def : Pat<(br bb:$addr), (BRFU_lu6 bb:$addr)>; 892 893// direct match equal/notequal zero brcond 894def : Pat<(brcond (setne GRRegs:$lhs, 0), bb:$dst), 895 (BRFT_lru6 GRRegs:$lhs, bb:$dst)>; 896def : Pat<(brcond (seteq GRRegs:$lhs, 0), bb:$dst), 897 (BRFF_lru6 GRRegs:$lhs, bb:$dst)>; 898 899def : Pat<(brcond (setle GRRegs:$lhs, GRRegs:$rhs), bb:$dst), 900 (BRFF_lru6 (LSS_3r GRRegs:$rhs, GRRegs:$lhs), bb:$dst)>; 901def : Pat<(brcond (setule GRRegs:$lhs, GRRegs:$rhs), bb:$dst), 902 (BRFF_lru6 (LSU_3r GRRegs:$rhs, GRRegs:$lhs), bb:$dst)>; 903def : Pat<(brcond (setge GRRegs:$lhs, GRRegs:$rhs), bb:$dst), 904 (BRFF_lru6 (LSS_3r GRRegs:$lhs, GRRegs:$rhs), bb:$dst)>; 905def : Pat<(brcond (setuge GRRegs:$lhs, GRRegs:$rhs), bb:$dst), 906 (BRFF_lru6 (LSU_3r GRRegs:$lhs, GRRegs:$rhs), bb:$dst)>; 907def : Pat<(brcond (setne GRRegs:$lhs, GRRegs:$rhs), bb:$dst), 908 (BRFF_lru6 (EQ_3r GRRegs:$lhs, GRRegs:$rhs), bb:$dst)>; 909def : Pat<(brcond (setne GRRegs:$lhs, immUs:$rhs), bb:$dst), 910 (BRFF_lru6 (EQ_2rus GRRegs:$lhs, immUs:$rhs), bb:$dst)>; 911 912// generic brcond pattern 913def : Pat<(brcond GRRegs:$cond, bb:$addr), (BRFT_lru6 GRRegs:$cond, bb:$addr)>; 914 915 916/// 917/// Select patterns 918/// 919 920// direct match equal/notequal zero select 921def : Pat<(select (setne GRRegs:$lhs, 0), GRRegs:$T, GRRegs:$F), 922 (SELECT_CC GRRegs:$lhs, GRRegs:$T, GRRegs:$F)>; 923 924def : Pat<(select (seteq GRRegs:$lhs, 0), GRRegs:$T, GRRegs:$F), 925 (SELECT_CC GRRegs:$lhs, GRRegs:$F, GRRegs:$T)>; 926 927def : Pat<(select (setle GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F), 928 (SELECT_CC (LSS_3r GRRegs:$rhs, GRRegs:$lhs), GRRegs:$F, GRRegs:$T)>; 929def : Pat<(select (setule GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F), 930 (SELECT_CC (LSU_3r GRRegs:$rhs, GRRegs:$lhs), GRRegs:$F, GRRegs:$T)>; 931def : Pat<(select (setge GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F), 932 (SELECT_CC (LSS_3r GRRegs:$lhs, GRRegs:$rhs), GRRegs:$F, GRRegs:$T)>; 933def : Pat<(select (setuge GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F), 934 (SELECT_CC (LSU_3r GRRegs:$lhs, GRRegs:$rhs), GRRegs:$F, GRRegs:$T)>; 935def : Pat<(select (setne GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F), 936 (SELECT_CC (EQ_3r GRRegs:$lhs, GRRegs:$rhs), GRRegs:$F, GRRegs:$T)>; 937def : Pat<(select (setne GRRegs:$lhs, immUs:$rhs), GRRegs:$T, GRRegs:$F), 938 (SELECT_CC (EQ_2rus GRRegs:$lhs, immUs:$rhs), GRRegs:$F, GRRegs:$T)>; 939 940/// 941/// setcc patterns, only matched when none of the above brcond 942/// patterns match 943/// 944 945// setcc 2 register operands 946def : Pat<(setle GRRegs:$lhs, GRRegs:$rhs), 947 (EQ_2rus (LSS_3r GRRegs:$rhs, GRRegs:$lhs), 0)>; 948def : Pat<(setule GRRegs:$lhs, GRRegs:$rhs), 949 (EQ_2rus (LSU_3r GRRegs:$rhs, GRRegs:$lhs), 0)>; 950 951def : Pat<(setgt GRRegs:$lhs, GRRegs:$rhs), 952 (LSS_3r GRRegs:$rhs, GRRegs:$lhs)>; 953def : Pat<(setugt GRRegs:$lhs, GRRegs:$rhs), 954 (LSU_3r GRRegs:$rhs, GRRegs:$lhs)>; 955 956def : Pat<(setge GRRegs:$lhs, GRRegs:$rhs), 957 (EQ_2rus (LSS_3r GRRegs:$lhs, GRRegs:$rhs), 0)>; 958def : Pat<(setuge GRRegs:$lhs, GRRegs:$rhs), 959 (EQ_2rus (LSU_3r GRRegs:$lhs, GRRegs:$rhs), 0)>; 960 961def : Pat<(setlt GRRegs:$lhs, GRRegs:$rhs), 962 (LSS_3r GRRegs:$lhs, GRRegs:$rhs)>; 963def : Pat<(setult GRRegs:$lhs, GRRegs:$rhs), 964 (LSU_3r GRRegs:$lhs, GRRegs:$rhs)>; 965 966def : Pat<(setne GRRegs:$lhs, GRRegs:$rhs), 967 (EQ_2rus (EQ_3r GRRegs:$lhs, GRRegs:$rhs), 0)>; 968 969def : Pat<(seteq GRRegs:$lhs, GRRegs:$rhs), 970 (EQ_3r GRRegs:$lhs, GRRegs:$rhs)>; 971 972// setcc reg/imm operands 973def : Pat<(seteq GRRegs:$lhs, immUs:$rhs), 974 (EQ_2rus GRRegs:$lhs, immUs:$rhs)>; 975def : Pat<(setne GRRegs:$lhs, immUs:$rhs), 976 (EQ_2rus (EQ_2rus GRRegs:$lhs, immUs:$rhs), 0)>; 977 978// misc 979def : Pat<(add GRRegs:$addr, immUs4:$offset), 980 (LDAWF_l2rus GRRegs:$addr, (div4_xform immUs4:$offset))>; 981 982def : Pat<(sub GRRegs:$addr, immUs4:$offset), 983 (LDAWB_l2rus GRRegs:$addr, (div4_xform immUs4:$offset))>; 984 985def : Pat<(and GRRegs:$val, immMskBitp:$mask), 986 (ZEXT_rus GRRegs:$val, (msksize_xform immMskBitp:$mask))>; 987 988// (sub X, imm) gets canonicalized to (add X, -imm). Match this form. 989def : Pat<(add GRRegs:$src1, immUsNeg:$src2), 990 (SUB_2rus GRRegs:$src1, (neg_xform immUsNeg:$src2))>; 991 992def : Pat<(add GRRegs:$src1, immUs4Neg:$src2), 993 (LDAWB_l2rus GRRegs:$src1, (div4neg_xform immUs4Neg:$src2))>; 994 995/// 996/// Some peepholes 997/// 998 999def : Pat<(mul GRRegs:$src, 3), 1000 (LDA16F_l3r GRRegs:$src, GRRegs:$src)>; 1001 1002def : Pat<(mul GRRegs:$src, 5), 1003 (LDAWF_l3r GRRegs:$src, GRRegs:$src)>; 1004 1005def : Pat<(mul GRRegs:$src, -3), 1006 (LDAWB_l3r GRRegs:$src, GRRegs:$src)>; 1007 1008// ashr X, 32 is equivalent to ashr X, 31 on the XCore. 1009def : Pat<(sra GRRegs:$src, 31), 1010 (ASHR_l2rus GRRegs:$src, 32)>; 1011 1012def : Pat<(brcond (setlt GRRegs:$lhs, 0), bb:$dst), 1013 (BRFT_lru6 (ASHR_l2rus GRRegs:$lhs, 32), bb:$dst)>; 1014 1015// setge X, 0 is canonicalized to setgt X, -1 1016def : Pat<(brcond (setgt GRRegs:$lhs, -1), bb:$dst), 1017 (BRFF_lru6 (ASHR_l2rus GRRegs:$lhs, 32), bb:$dst)>; 1018 1019def : Pat<(select (setlt GRRegs:$lhs, 0), GRRegs:$T, GRRegs:$F), 1020 (SELECT_CC (ASHR_l2rus GRRegs:$lhs, 32), GRRegs:$T, GRRegs:$F)>; 1021 1022def : Pat<(select (setgt GRRegs:$lhs, -1), GRRegs:$T, GRRegs:$F), 1023 (SELECT_CC (ASHR_l2rus GRRegs:$lhs, 32), GRRegs:$F, GRRegs:$T)>; 1024 1025def : Pat<(setgt GRRegs:$lhs, -1), 1026 (EQ_2rus (ASHR_l2rus GRRegs:$lhs, 32), 0)>; 1027 1028def : Pat<(sra (shl GRRegs:$src, immBpwSubBitp:$imm), immBpwSubBitp:$imm), 1029 (SEXT_rus GRRegs:$src, (bpwsub_xform immBpwSubBitp:$imm))>; 1030