XCoreInstrInfo.td revision 239462
1105756Srwatson//===-- XCoreInstrInfo.td - Target Description for XCore ---*- tablegen -*-===// 2330449Seadler// 3330449Seadler// The LLVM Compiler Infrastructure 4125959Srwatson// 5105756Srwatson// This file is distributed under the University of Illinois Open Source 6105756Srwatson// License. See LICENSE.TXT for details. 7105756Srwatson// 8105756Srwatson//===----------------------------------------------------------------------===// 9105756Srwatson// 10105756Srwatson// This file describes the XCore instructions in TableGen format. 11105756Srwatson// 12105756Srwatson//===----------------------------------------------------------------------===// 13105756Srwatson 14105756Srwatson// Uses of CP, DP are not currently reflected in the patterns, since 15105756Srwatson// having a physical register as an operand prevents loop hoisting and 16105756Srwatson// since the value of these registers never changes during the life of the 17105756Srwatson// function. 18105756Srwatson 19105756Srwatson//===----------------------------------------------------------------------===// 20105756Srwatson// Instruction format superclass. 21105756Srwatson//===----------------------------------------------------------------------===// 22105756Srwatson 23105756Srwatsoninclude "XCoreInstrFormats.td" 24105756Srwatson 25105756Srwatson//===----------------------------------------------------------------------===// 26105756Srwatson// XCore specific DAG Nodes. 27105756Srwatson// 28105756Srwatson 29105756Srwatson// Call 30105756Srwatsondef SDT_XCoreBranchLink : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>; 31105756Srwatsondef XCoreBranchLink : SDNode<"XCoreISD::BL",SDT_XCoreBranchLink, 32105756Srwatson [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 33105756Srwatson SDNPVariadic]>; 34105756Srwatson 35107489Srwatsondef XCoreRetsp : SDNode<"XCoreISD::RETSP", SDTBrind, 36105756Srwatson [SDNPHasChain, SDNPOptInGlue]>; 37105756Srwatson 38107489Srwatsondef SDT_XCoreBR_JT : SDTypeProfile<0, 2, 39107489Srwatson [SDTCisVT<0, i32>, SDTCisVT<1, i32>]>; 40105756Srwatson 41107489Srwatsondef XCoreBR_JT : SDNode<"XCoreISD::BR_JT", SDT_XCoreBR_JT, 42105756Srwatson [SDNPHasChain]>; 43107489Srwatson 44107489Srwatsondef XCoreBR_JT32 : SDNode<"XCoreISD::BR_JT32", SDT_XCoreBR_JT, 45107489Srwatson [SDNPHasChain]>; 46107489Srwatson 47105756Srwatsondef SDT_XCoreAddress : SDTypeProfile<1, 1, 48105756Srwatson [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>; 49105756Srwatson 50105756Srwatsondef pcrelwrapper : SDNode<"XCoreISD::PCRelativeWrapper", SDT_XCoreAddress, 51105756Srwatson []>; 52107489Srwatson 53107489Srwatsondef dprelwrapper : SDNode<"XCoreISD::DPRelativeWrapper", SDT_XCoreAddress, 54107489Srwatson []>; 55107489Srwatson 56107489Srwatsondef cprelwrapper : SDNode<"XCoreISD::CPRelativeWrapper", SDT_XCoreAddress, 57140907Sdelphij []>; 58107489Srwatson 59107489Srwatsondef SDT_XCoreStwsp : SDTypeProfile<0, 2, [SDTCisInt<1>]>; 60107489Srwatsondef XCoreStwsp : SDNode<"XCoreISD::STWSP", SDT_XCoreStwsp, 61107489Srwatson [SDNPHasChain]>; 62107489Srwatson 63107489Srwatson// These are target-independent nodes, but have target-specific formats. 64107489Srwatsondef SDT_XCoreCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>; 65107489Srwatsondef SDT_XCoreCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, 66107489Srwatson SDTCisVT<1, i32> ]>; 67105756Srwatson 68107489Srwatsondef callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_XCoreCallSeqStart, 69107489Srwatson [SDNPHasChain, SDNPOutGlue]>; 70107489Srwatsondef callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_XCoreCallSeqEnd, 71105756Srwatson [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 72107489Srwatson 73107489Srwatson//===----------------------------------------------------------------------===// 74107489Srwatson// Instruction Pattern Stuff 75107489Srwatson//===----------------------------------------------------------------------===// 76107489Srwatson 77107489Srwatsondef div4_xform : SDNodeXForm<imm, [{ 78107489Srwatson // Transformation function: imm/4 79105756Srwatson assert(N->getZExtValue() % 4 == 0); 80125959Srwatson return getI32Imm(N->getZExtValue()/4); 81125959Srwatson}]>; 82105756Srwatson 83107489Srwatsondef msksize_xform : SDNodeXForm<imm, [{ 84105756Srwatson // Transformation function: get the size of a mask 85107489Srwatson assert(isMask_32(N->getZExtValue())); 86107489Srwatson // look for the first non-zero bit 87107489Srwatson return getI32Imm(32 - CountLeadingZeros_32(N->getZExtValue())); 88107489Srwatson}]>; 89107489Srwatson 90107489Srwatsondef neg_xform : SDNodeXForm<imm, [{ 91105756Srwatson // Transformation function: -imm 92107489Srwatson uint32_t value = N->getZExtValue(); 93107489Srwatson return getI32Imm(-value); 94107489Srwatson}]>; 95107489Srwatson 96107489Srwatsondef bpwsub_xform : SDNodeXForm<imm, [{ 97107489Srwatson // Transformation function: 32-imm 98125959Srwatson uint32_t value = N->getZExtValue(); 99125959Srwatson return getI32Imm(32-value); 100105756Srwatson}]>; 101107489Srwatson 102107489Srwatsondef div4neg_xform : SDNodeXForm<imm, [{ 103107489Srwatson // Transformation function: -imm/4 104107489Srwatson uint32_t value = N->getZExtValue(); 105107489Srwatson assert(-value % 4 == 0); 106107489Srwatson return getI32Imm(-value/4); 107107489Srwatson}]>; 108107489Srwatson 109107489Srwatsondef immUs4Neg : PatLeaf<(imm), [{ 110105756Srwatson uint32_t value = (uint32_t)N->getZExtValue(); 111107489Srwatson return (-value)%4 == 0 && (-value)/4 <= 11; 112105756Srwatson}]>; 113125959Srwatson 114125959Srwatsondef immUs4 : PatLeaf<(imm), [{ 115125959Srwatson uint32_t value = (uint32_t)N->getZExtValue(); 116107489Srwatson return value%4 == 0 && value/4 <= 11; 117107489Srwatson}]>; 118107489Srwatson 119107489Srwatsondef immUsNeg : PatLeaf<(imm), [{ 120107489Srwatson return -((uint32_t)N->getZExtValue()) <= 11; 121107489Srwatson}]>; 122107489Srwatson 123107489Srwatsondef immUs : PatLeaf<(imm), [{ 124107489Srwatson return (uint32_t)N->getZExtValue() <= 11; 125105756Srwatson}]>; 126107489Srwatson 127105756Srwatsondef immU6 : PatLeaf<(imm), [{ 128105756Srwatson return (uint32_t)N->getZExtValue() < (1 << 6); 129107489Srwatson}]>; 130105756Srwatson 131105756Srwatsondef immU10 : PatLeaf<(imm), [{ 132107489Srwatson return (uint32_t)N->getZExtValue() < (1 << 10); 133107489Srwatson}]>; 134107489Srwatson 135107489Srwatsondef immU16 : PatLeaf<(imm), [{ 136107489Srwatson return (uint32_t)N->getZExtValue() < (1 << 16); 137107489Srwatson}]>; 138107489Srwatson 139107489Srwatsondef immU20 : PatLeaf<(imm), [{ 140107489Srwatson return (uint32_t)N->getZExtValue() < (1 << 20); 141107489Srwatson}]>; 142107489Srwatson 143107489Srwatsondef immMskBitp : PatLeaf<(imm), [{ return immMskBitp(N); }]>; 144107489Srwatson 145107489Srwatsondef immBitp : PatLeaf<(imm), [{ 146107489Srwatson uint32_t value = (uint32_t)N->getZExtValue(); 147107489Srwatson return (value >= 1 && value <= 8) 148107489Srwatson || value == 16 149107489Srwatson || value == 24 150107489Srwatson || value == 32; 151107489Srwatson}]>; 152107489Srwatson 153107489Srwatsondef immBpwSubBitp : PatLeaf<(imm), [{ 154107489Srwatson uint32_t value = (uint32_t)N->getZExtValue(); 155107489Srwatson return (value >= 24 && value <= 31) 156107489Srwatson || value == 16 157107794Sgreen || value == 8 158107489Srwatson || value == 0; 159107489Srwatson}]>; 160107489Srwatson 161175796Syardef lda16f : PatFrag<(ops node:$addr, node:$offset), 162107489Srwatson (add node:$addr, (shl node:$offset, 1))>; 163107489Srwatsondef lda16b : PatFrag<(ops node:$addr, node:$offset), 164125959Srwatson (sub node:$addr, (shl node:$offset, 1))>; 165175796Syardef ldawf : PatFrag<(ops node:$addr, node:$offset), 166125959Srwatson (add node:$addr, (shl node:$offset, 2))>; 167107489Srwatsondef ldawb : PatFrag<(ops node:$addr, node:$offset), 168107489Srwatson (sub node:$addr, (shl node:$offset, 2))>; 169107489Srwatson 170107489Srwatson// Instruction operand types 171107489Srwatsondef calltarget : Operand<i32>; 172107489Srwatsondef brtarget : Operand<OtherVT>; 173175796Syardef pclabel : Operand<i32>; 174107489Srwatson 175175796Syar// Addressing modes 176175796Syardef ADDRspii : ComplexPattern<i32, 2, "SelectADDRspii", [add, frameindex], []>; 177107489Srwatsondef ADDRdpii : ComplexPattern<i32, 2, "SelectADDRdpii", [add, dprelwrapper], 178107489Srwatson []>; 179107489Srwatsondef ADDRcpii : ComplexPattern<i32, 2, "SelectADDRcpii", [add, cprelwrapper], 180107489Srwatson []>; 181107489Srwatson 182105756Srwatson// Address operands 183107489Srwatsondef MEMii : Operand<i32> { 184107489Srwatson let PrintMethod = "printMemOperand"; 185107489Srwatson let MIOperandInfo = (ops i32imm, i32imm); 186107489Srwatson} 187107489Srwatson 188125959Srwatson// Jump tables. 189107489Srwatsondef InlineJT : Operand<i32> { 190125959Srwatson let PrintMethod = "printInlineJT"; 191107489Srwatson} 192107489Srwatson 193107489Srwatsondef InlineJT32 : Operand<i32> { 194140907Sdelphij let PrintMethod = "printInlineJT32"; 195107489Srwatson} 196107489Srwatson 197107489Srwatson//===----------------------------------------------------------------------===// 198107489Srwatson// Instruction Class Templates 199107489Srwatson//===----------------------------------------------------------------------===// 200140907Sdelphij 201107489Srwatson// Three operand short 202107489Srwatson 203105756Srwatsonmulticlass F3R_2RUS<string OpcStr, SDNode OpNode> { 204107489Srwatson def _3r: _F3R< 205107489Srwatson (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), 206107489Srwatson !strconcat(OpcStr, " $dst, $b, $c"), 207107489Srwatson [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>; 208107489Srwatson def _2rus : _F2RUS< 209107489Srwatson (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c), 210107489Srwatson !strconcat(OpcStr, " $dst, $b, $c"), 211107489Srwatson [(set GRRegs:$dst, (OpNode GRRegs:$b, immUs:$c))]>; 212107489Srwatson} 213107489Srwatson 214107489Srwatsonmulticlass F3R_2RUS_np<string OpcStr> { 215107489Srwatson def _3r: _F3R< 216107489Srwatson (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), 217107489Srwatson !strconcat(OpcStr, " $dst, $b, $c"), 218107489Srwatson []>; 219107489Srwatson def _2rus : _F2RUS< 220107489Srwatson (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c), 221107489Srwatson !strconcat(OpcStr, " $dst, $b, $c"), 222107489Srwatson []>; 223107489Srwatson} 224107489Srwatson 225107489Srwatsonmulticlass F3R_2RBITP<string OpcStr, SDNode OpNode> { 226107489Srwatson def _3r: _F3R< 227107489Srwatson (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), 228105756Srwatson !strconcat(OpcStr, " $dst, $b, $c"), 229107489Srwatson [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>; 230107489Srwatson def _2rus : _F2RUS< 231107489Srwatson (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c), 232107489Srwatson !strconcat(OpcStr, " $dst, $b, $c"), 233107489Srwatson [(set GRRegs:$dst, (OpNode GRRegs:$b, immBitp:$c))]>; 234107489Srwatson} 235107489Srwatson 236107489Srwatsonclass F3R<string OpcStr, SDNode OpNode> : _F3R< 237107489Srwatson (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), 238107489Srwatson !strconcat(OpcStr, " $dst, $b, $c"), 239107489Srwatson [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>; 240107489Srwatson 241107489Srwatsonclass F3R_np<string OpcStr> : _F3R< 242107489Srwatson (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), 243107489Srwatson !strconcat(OpcStr, " $dst, $b, $c"), 244107489Srwatson []>; 245107489Srwatson// Three operand long 246107489Srwatson 247107489Srwatson/// FL3R_L2RUS multiclass - Define a normal FL3R/FL2RUS pattern in one shot. 248107489Srwatsonmulticlass FL3R_L2RUS<string OpcStr, SDNode OpNode> { 249107489Srwatson def _l3r: _FL3R< 250107489Srwatson (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), 251107489Srwatson !strconcat(OpcStr, " $dst, $b, $c"), 252107489Srwatson [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>; 253107489Srwatson def _l2rus : _FL2RUS< 254107489Srwatson (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c), 255107489Srwatson !strconcat(OpcStr, " $dst, $b, $c"), 256107489Srwatson [(set GRRegs:$dst, (OpNode GRRegs:$b, immUs:$c))]>; 257107489Srwatson} 258107489Srwatson 259107489Srwatson/// FL3R_L2RUS multiclass - Define a normal FL3R/FL2RUS pattern in one shot. 260107489Srwatsonmulticlass FL3R_L2RBITP<string OpcStr, SDNode OpNode> { 261107489Srwatson def _l3r: _FL3R< 262107489Srwatson (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), 263107489Srwatson !strconcat(OpcStr, " $dst, $b, $c"), 264107489Srwatson [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>; 265105756Srwatson def _l2rus : _FL2RUS< 266107489Srwatson (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c), 267107489Srwatson !strconcat(OpcStr, " $dst, $b, $c"), 268107489Srwatson [(set GRRegs:$dst, (OpNode GRRegs:$b, immBitp:$c))]>; 269107489Srwatson} 270107489Srwatson 271107489Srwatsonclass FL3R<string OpcStr, SDNode OpNode> : _FL3R< 272107489Srwatson (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), 273107489Srwatson !strconcat(OpcStr, " $dst, $b, $c"), 274107489Srwatson [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>; 275107489Srwatson 276107489Srwatson// Register - U6 277125959Srwatson// Operand register - U6 278125959Srwatsonmulticlass FRU6_LRU6_branch<string OpcStr> { 279125959Srwatson def _ru6: _FRU6< 280107489Srwatson (outs), (ins GRRegs:$cond, brtarget:$dest), 281107489Srwatson !strconcat(OpcStr, " $cond, $dest"), 282105756Srwatson []>; 283107489Srwatson def _lru6: _FLRU6< 284107489Srwatson (outs), (ins GRRegs:$cond, brtarget:$dest), 285107489Srwatson !strconcat(OpcStr, " $cond, $dest"), 286107489Srwatson []>; 287107489Srwatson} 288107489Srwatson 289107489Srwatsonmulticlass FRU6_LRU6_cp<string OpcStr> { 290107489Srwatson def _ru6: _FRU6< 291107489Srwatson (outs GRRegs:$dst), (ins i32imm:$a), 292107489Srwatson !strconcat(OpcStr, " $dst, cp[$a]"), 293107489Srwatson []>; 294107489Srwatson def _lru6: _FLRU6< 295107489Srwatson (outs GRRegs:$dst), (ins i32imm:$a), 296107489Srwatson !strconcat(OpcStr, " $dst, cp[$a]"), 297107489Srwatson []>; 298107489Srwatson} 299107489Srwatson 300107489Srwatson// U6 301107489Srwatsonmulticlass FU6_LU6<string OpcStr, SDNode OpNode> { 302107489Srwatson def _u6: _FU6< 303107489Srwatson (outs), (ins i32imm:$b), 304107489Srwatson !strconcat(OpcStr, " $b"), 305107489Srwatson [(OpNode immU6:$b)]>; 306107489Srwatson def _lu6: _FLU6< 307107489Srwatson (outs), (ins i32imm:$b), 308107489Srwatson !strconcat(OpcStr, " $b"), 309107489Srwatson [(OpNode immU16:$b)]>; 310107489Srwatson} 311107489Srwatsonmulticlass FU6_LU6_int<string OpcStr, Intrinsic Int> { 312107489Srwatson def _u6: _FU6< 313107489Srwatson (outs), (ins i32imm:$b), 314107489Srwatson !strconcat(OpcStr, " $b"), 315107489Srwatson [(Int immU6:$b)]>; 316107489Srwatson def _lu6: _FLU6< 317107489Srwatson (outs), (ins i32imm:$b), 318107489Srwatson !strconcat(OpcStr, " $b"), 319105756Srwatson [(Int immU16:$b)]>; 320107489Srwatson} 321107489Srwatson 322107489Srwatsonmulticlass FU6_LU6_np<string OpcStr> { 323107489Srwatson def _u6: _FU6< 324107489Srwatson (outs), (ins i32imm:$b), 325107489Srwatson !strconcat(OpcStr, " $b"), 326107489Srwatson []>; 327107489Srwatson def _lu6: _FLU6< 328107489Srwatson (outs), (ins i32imm:$b), 329107489Srwatson !strconcat(OpcStr, " $b"), 330107489Srwatson []>; 331107489Srwatson} 332107489Srwatson 333107489Srwatson// U10 334107489Srwatsonmulticlass FU10_LU10_np<string OpcStr> { 335107489Srwatson def _u10: _FU10< 336107489Srwatson (outs), (ins i32imm:$b), 337107489Srwatson !strconcat(OpcStr, " $b"), 338107489Srwatson []>; 339107489Srwatson def _lu10: _FLU10< 340107489Srwatson (outs), (ins i32imm:$b), 341107489Srwatson !strconcat(OpcStr, " $b"), 342107489Srwatson []>; 343107489Srwatson} 344107489Srwatson 345107489Srwatson// Two operand short 346107489Srwatson 347107489Srwatsonclass F2R_np<string OpcStr> : _F2R< 348107489Srwatson (outs GRRegs:$dst), (ins GRRegs:$b), 349107489Srwatson !strconcat(OpcStr, " $dst, $b"), 350107489Srwatson []>; 351107489Srwatson 352107489Srwatson// Two operand long 353107489Srwatson 354107489Srwatson//===----------------------------------------------------------------------===// 355107489Srwatson// Pseudo Instructions 356107489Srwatson//===----------------------------------------------------------------------===// 357107489Srwatson 358107489Srwatsonlet Defs = [SP], Uses = [SP] in { 359107489Srwatsondef ADJCALLSTACKDOWN : PseudoInstXCore<(outs), (ins i32imm:$amt), 360107489Srwatson "${:comment} ADJCALLSTACKDOWN $amt", 361107489Srwatson [(callseq_start timm:$amt)]>; 362107489Srwatsondef ADJCALLSTACKUP : PseudoInstXCore<(outs), (ins i32imm:$amt1, i32imm:$amt2), 363107489Srwatson "${:comment} ADJCALLSTACKUP $amt1", 364107489Srwatson [(callseq_end timm:$amt1, timm:$amt2)]>; 365107489Srwatson} 366107489Srwatson 367107489Srwatsondef LDWFI : PseudoInstXCore<(outs GRRegs:$dst), (ins MEMii:$addr), 368107489Srwatson "${:comment} LDWFI $dst, $addr", 369107489Srwatson [(set GRRegs:$dst, (load ADDRspii:$addr))]>; 370107489Srwatson 371107489Srwatsondef LDAWFI : PseudoInstXCore<(outs GRRegs:$dst), (ins MEMii:$addr), 372107489Srwatson "${:comment} LDAWFI $dst, $addr", 373107489Srwatson [(set GRRegs:$dst, ADDRspii:$addr)]>; 374107489Srwatson 375107489Srwatsondef STWFI : PseudoInstXCore<(outs), (ins GRRegs:$src, MEMii:$addr), 376107489Srwatson "${:comment} STWFI $src, $addr", 377107489Srwatson [(store GRRegs:$src, ADDRspii:$addr)]>; 378107489Srwatson 379107489Srwatson// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after 380107489Srwatson// instruction selection into a branch sequence. 381107489Srwatsonlet usesCustomInserter = 1 in { 382107489Srwatson def SELECT_CC : PseudoInstXCore<(outs GRRegs:$dst), 383107489Srwatson (ins GRRegs:$cond, GRRegs:$T, GRRegs:$F), 384105756Srwatson "${:comment} SELECT_CC PSEUDO!", 385107489Srwatson [(set GRRegs:$dst, 386107489Srwatson (select GRRegs:$cond, GRRegs:$T, GRRegs:$F))]>; 387107489Srwatson} 388105756Srwatson 389107489Srwatson//===----------------------------------------------------------------------===// 390105756Srwatson// Instructions 391107489Srwatson//===----------------------------------------------------------------------===// 392107489Srwatson 393107489Srwatson// Three operand short 394107489Srwatsondefm ADD : F3R_2RUS<"add", add>; 395107489Srwatsondefm SUB : F3R_2RUS<"sub", sub>; 396107489Srwatsonlet neverHasSideEffects = 1 in { 397107489Srwatsondefm EQ : F3R_2RUS_np<"eq">; 398107489Srwatsondef LSS_3r : F3R_np<"lss">; 399107489Srwatsondef LSU_3r : F3R_np<"lsu">; 400107489Srwatson} 401107489Srwatsondef AND_3r : F3R<"and", and>; 402107489Srwatsondef OR_3r : F3R<"or", or>; 403107489Srwatson 404107489Srwatsonlet mayLoad=1 in { 405107489Srwatsondef LDW_3r : _F3R<(outs GRRegs:$dst), (ins GRRegs:$addr, GRRegs:$offset), 406107489Srwatson "ldw $dst, $addr[$offset]", 407107489Srwatson []>; 408107489Srwatson 409107489Srwatsondef LDW_2rus : _F2RUS<(outs GRRegs:$dst), (ins GRRegs:$addr, i32imm:$offset), 410107489Srwatson "ldw $dst, $addr[$offset]", 411107489Srwatson []>; 412107489Srwatson 413107489Srwatsondef LD16S_3r : _F3R<(outs GRRegs:$dst), (ins GRRegs:$addr, GRRegs:$offset), 414107489Srwatson "ld16s $dst, $addr[$offset]", 415107489Srwatson []>; 416107489Srwatson 417107489Srwatsondef LD8U_3r : _F3R<(outs GRRegs:$dst), (ins GRRegs:$addr, GRRegs:$offset), 418107489Srwatson "ld8u $dst, $addr[$offset]", 419107489Srwatson []>; 420107489Srwatson} 421107489Srwatson 422107489Srwatsonlet mayStore=1 in { 423107489Srwatsondef STW_3r : _F3R<(outs), (ins GRRegs:$val, GRRegs:$addr, GRRegs:$offset), 424107489Srwatson "stw $val, $addr[$offset]", 425107489Srwatson []>; 426107489Srwatson 427107489Srwatsondef STW_2rus : _F2RUS<(outs), (ins GRRegs:$val, GRRegs:$addr, i32imm:$offset), 428107489Srwatson "stw $val, $addr[$offset]", 429107489Srwatson []>; 430107489Srwatson} 431107489Srwatson 432107489Srwatsondefm SHL : F3R_2RBITP<"shl", shl>; 433107489Srwatsondefm SHR : F3R_2RBITP<"shr", srl>; 434107489Srwatson// TODO tsetr 435107489Srwatson 436107489Srwatson// Three operand long 437107489Srwatsondef LDAWF_l3r : _FL3R<(outs GRRegs:$dst), (ins GRRegs:$addr, GRRegs:$offset), 438107489Srwatson "ldaw $dst, $addr[$offset]", 439175796Syar [(set GRRegs:$dst, (ldawf GRRegs:$addr, GRRegs:$offset))]>; 440107489Srwatson 441107489Srwatsonlet neverHasSideEffects = 1 in 442107489Srwatsondef LDAWF_l2rus : _FL2RUS<(outs GRRegs:$dst), 443107489Srwatson (ins GRRegs:$addr, i32imm:$offset), 444107489Srwatson "ldaw $dst, $addr[$offset]", 445107489Srwatson []>; 446107489Srwatson 447107489Srwatsondef LDAWB_l3r : _FL3R<(outs GRRegs:$dst), (ins GRRegs:$addr, GRRegs:$offset), 448107489Srwatson "ldaw $dst, $addr[-$offset]", 449107489Srwatson [(set GRRegs:$dst, (ldawb GRRegs:$addr, GRRegs:$offset))]>; 450107489Srwatson 451107489Srwatsonlet neverHasSideEffects = 1 in 452107489Srwatsondef LDAWB_l2rus : _FL2RUS<(outs GRRegs:$dst), 453107489Srwatson (ins GRRegs:$addr, i32imm:$offset), 454107489Srwatson "ldaw $dst, $addr[-$offset]", 455107489Srwatson []>; 456107489Srwatson 457107489Srwatsondef LDA16F_l3r : _FL3R<(outs GRRegs:$dst), (ins GRRegs:$addr, GRRegs:$offset), 458107489Srwatson "lda16 $dst, $addr[$offset]", 459107489Srwatson [(set GRRegs:$dst, (lda16f GRRegs:$addr, GRRegs:$offset))]>; 460107489Srwatson 461107489Srwatsondef LDA16B_l3r : _FL3R<(outs GRRegs:$dst), (ins GRRegs:$addr, GRRegs:$offset), 462107489Srwatson "lda16 $dst, $addr[-$offset]", 463107489Srwatson [(set GRRegs:$dst, (lda16b GRRegs:$addr, GRRegs:$offset))]>; 464107489Srwatson 465107489Srwatsondef MUL_l3r : FL3R<"mul", mul>; 466107489Srwatson// Instructions which may trap are marked as side effecting. 467107489Srwatsonlet hasSideEffects = 1 in { 468107489Srwatsondef DIVS_l3r : FL3R<"divs", sdiv>; 469107489Srwatsondef DIVU_l3r : FL3R<"divu", udiv>; 470107489Srwatsondef REMS_l3r : FL3R<"rems", srem>; 471107489Srwatsondef REMU_l3r : FL3R<"remu", urem>; 472107489Srwatson} 473107489Srwatsondef XOR_l3r : FL3R<"xor", xor>; 474107489Srwatsondefm ASHR : FL3R_L2RBITP<"ashr", sra>; 475107489Srwatson 476107489Srwatsonlet Constraints = "$src1 = $dst" in 477107489Srwatsondef CRC_l3r : _FL3R<(outs GRRegs:$dst), 478107489Srwatson (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3), 479107489Srwatson "crc32 $dst, $src2, $src3", 480107489Srwatson [(set GRRegs:$dst, 481107489Srwatson (int_xcore_crc32 GRRegs:$src1, GRRegs:$src2, 482107489Srwatson GRRegs:$src3))]>; 483175796Syar 484107489Srwatson// TODO inpw, outpw 485107489Srwatsonlet mayStore=1 in { 486107489Srwatsondef ST16_l3r : _FL3R<(outs), (ins GRRegs:$val, GRRegs:$addr, GRRegs:$offset), 487107489Srwatson "st16 $val, $addr[$offset]", 488107489Srwatson []>; 489107489Srwatson 490107489Srwatsondef ST8_l3r : _FL3R<(outs), (ins GRRegs:$val, GRRegs:$addr, GRRegs:$offset), 491107489Srwatson "st8 $val, $addr[$offset]", 492107489Srwatson []>; 493107489Srwatson} 494107489Srwatson 495107489Srwatson// Four operand long 496107489Srwatsonlet Constraints = "$src1 = $dst1,$src2 = $dst2" in { 497107489Srwatsondef MACCU_l4r : _L4R<(outs GRRegs:$dst1, GRRegs:$dst2), 498107489Srwatson (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3, 499107489Srwatson GRRegs:$src4), 500107489Srwatson "maccu $dst1, $dst2, $src3, $src4", 501 []>; 502 503def MACCS_l4r : _L4R<(outs GRRegs:$dst1, GRRegs:$dst2), 504 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3, 505 GRRegs:$src4), 506 "maccs $dst1, $dst2, $src3, $src4", 507 []>; 508} 509 510let Constraints = "$src1 = $dst1" in 511def CRC8_l4r : _L4R<(outs GRRegs:$dst1, GRRegs:$dst2), 512 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3), 513 "crc8 $dst1, $dst2, $src2, $src3", 514 []>; 515 516// Five operand long 517 518def LADD_l5r : _L5R<(outs GRRegs:$dst1, GRRegs:$dst2), 519 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3), 520 "ladd $dst1, $dst2, $src1, $src2, $src3", 521 []>; 522 523def LSUB_l5r : _L5R<(outs GRRegs:$dst1, GRRegs:$dst2), 524 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3), 525 "lsub $dst1, $dst2, $src1, $src2, $src3", 526 []>; 527 528def LDIV_l5r : _L5R<(outs GRRegs:$dst1, GRRegs:$dst2), 529 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3), 530 "ldiv $dst1, $dst2, $src1, $src2, $src3", 531 []>; 532 533// Six operand long 534 535def LMUL_l6r : _L6R<(outs GRRegs:$dst1, GRRegs:$dst2), 536 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3, 537 GRRegs:$src4), 538 "lmul $dst1, $dst2, $src1, $src2, $src3, $src4", 539 []>; 540 541// Register - U6 542 543//let Uses = [DP] in ... 544let neverHasSideEffects = 1, isReMaterializable = 1 in 545def LDAWDP_ru6: _FRU6<(outs GRRegs:$dst), (ins MEMii:$a), 546 "ldaw $dst, dp[$a]", 547 []>; 548 549let isReMaterializable = 1 in 550def LDAWDP_lru6: _FLRU6< 551 (outs GRRegs:$dst), (ins MEMii:$a), 552 "ldaw $dst, dp[$a]", 553 [(set GRRegs:$dst, ADDRdpii:$a)]>; 554 555let mayLoad=1 in 556def LDWDP_ru6: _FRU6<(outs GRRegs:$dst), (ins MEMii:$a), 557 "ldw $dst, dp[$a]", 558 []>; 559 560def LDWDP_lru6: _FLRU6< 561 (outs GRRegs:$dst), (ins MEMii:$a), 562 "ldw $dst, dp[$a]", 563 [(set GRRegs:$dst, (load ADDRdpii:$a))]>; 564 565let mayStore=1 in 566def STWDP_ru6 : _FRU6<(outs), (ins GRRegs:$val, MEMii:$addr), 567 "stw $val, dp[$addr]", 568 []>; 569 570def STWDP_lru6 : _FLRU6<(outs), (ins GRRegs:$val, MEMii:$addr), 571 "stw $val, dp[$addr]", 572 [(store GRRegs:$val, ADDRdpii:$addr)]>; 573 574//let Uses = [CP] in .. 575let mayLoad = 1, isReMaterializable = 1, neverHasSideEffects = 1 in 576defm LDWCP : FRU6_LRU6_cp<"ldw">; 577 578let Uses = [SP] in { 579let mayStore=1 in { 580def STWSP_ru6 : _FRU6< 581 (outs), (ins GRRegs:$val, i32imm:$index), 582 "stw $val, sp[$index]", 583 [(XCoreStwsp GRRegs:$val, immU6:$index)]>; 584 585def STWSP_lru6 : _FLRU6< 586 (outs), (ins GRRegs:$val, i32imm:$index), 587 "stw $val, sp[$index]", 588 [(XCoreStwsp GRRegs:$val, immU16:$index)]>; 589} 590 591let mayLoad=1 in { 592def LDWSP_ru6 : _FRU6< 593 (outs GRRegs:$dst), (ins i32imm:$b), 594 "ldw $dst, sp[$b]", 595 []>; 596 597def LDWSP_lru6 : _FLRU6< 598 (outs GRRegs:$dst), (ins i32imm:$b), 599 "ldw $dst, sp[$b]", 600 []>; 601} 602 603let neverHasSideEffects = 1 in { 604def LDAWSP_ru6 : _FRU6< 605 (outs GRRegs:$dst), (ins i32imm:$b), 606 "ldaw $dst, sp[$b]", 607 []>; 608 609def LDAWSP_lru6 : _FLRU6< 610 (outs GRRegs:$dst), (ins i32imm:$b), 611 "ldaw $dst, sp[$b]", 612 []>; 613 614def LDAWSP_ru6_RRegs : _FRU6< 615 (outs RRegs:$dst), (ins i32imm:$b), 616 "ldaw $dst, sp[$b]", 617 []>; 618 619def LDAWSP_lru6_RRegs : _FLRU6< 620 (outs RRegs:$dst), (ins i32imm:$b), 621 "ldaw $dst, sp[$b]", 622 []>; 623} 624} 625 626let isReMaterializable = 1 in { 627def LDC_ru6 : _FRU6< 628 (outs GRRegs:$dst), (ins i32imm:$b), 629 "ldc $dst, $b", 630 [(set GRRegs:$dst, immU6:$b)]>; 631 632def LDC_lru6 : _FLRU6< 633 (outs GRRegs:$dst), (ins i32imm:$b), 634 "ldc $dst, $b", 635 [(set GRRegs:$dst, immU16:$b)]>; 636} 637 638def SETC_ru6 : _FRU6<(outs), (ins GRRegs:$r, i32imm:$val), 639 "setc res[$r], $val", 640 [(int_xcore_setc GRRegs:$r, immU6:$val)]>; 641 642def SETC_lru6 : _FLRU6<(outs), (ins GRRegs:$r, i32imm:$val), 643 "setc res[$r], $val", 644 [(int_xcore_setc GRRegs:$r, immU16:$val)]>; 645 646// Operand register - U6 647let isBranch = 1, isTerminator = 1 in { 648defm BRFT: FRU6_LRU6_branch<"bt">; 649defm BRBT: FRU6_LRU6_branch<"bt">; 650defm BRFF: FRU6_LRU6_branch<"bf">; 651defm BRBF: FRU6_LRU6_branch<"bf">; 652} 653 654// U6 655let Defs = [SP], Uses = [SP] in { 656let neverHasSideEffects = 1 in 657defm EXTSP : FU6_LU6_np<"extsp">; 658let mayStore = 1 in 659defm ENTSP : FU6_LU6_np<"entsp">; 660 661let isReturn = 1, isTerminator = 1, mayLoad = 1, isBarrier = 1 in { 662defm RETSP : FU6_LU6<"retsp", XCoreRetsp>; 663} 664} 665 666// TODO extdp, kentsp, krestsp, blat 667// getsr, kalli 668let isBranch = 1, isTerminator = 1, isBarrier = 1 in { 669def BRBU_u6 : _FU6< 670 (outs), 671 (ins brtarget:$target), 672 "bu $target", 673 []>; 674 675def BRBU_lu6 : _FLU6< 676 (outs), 677 (ins brtarget:$target), 678 "bu $target", 679 []>; 680 681def BRFU_u6 : _FU6< 682 (outs), 683 (ins brtarget:$target), 684 "bu $target", 685 []>; 686 687def BRFU_lu6 : _FLU6< 688 (outs), 689 (ins brtarget:$target), 690 "bu $target", 691 []>; 692} 693 694//let Uses = [CP] in ... 695let Defs = [R11], neverHasSideEffects = 1, isReMaterializable = 1 in 696def LDAWCP_u6: _FRU6<(outs), (ins MEMii:$a), 697 "ldaw r11, cp[$a]", 698 []>; 699 700let Defs = [R11], isReMaterializable = 1 in 701def LDAWCP_lu6: _FLRU6< 702 (outs), (ins MEMii:$a), 703 "ldaw r11, cp[$a]", 704 [(set R11, ADDRcpii:$a)]>; 705 706defm SETSR : FU6_LU6_int<"setsr", int_xcore_setsr>; 707 708defm CLRSR : FU6_LU6_int<"clrsr", int_xcore_clrsr>; 709 710// setsr may cause a branch if it is used to enable events. clrsr may 711// branch if it is executed while events are enabled. 712let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in { 713defm SETSR_branch : FU6_LU6_np<"setsr">; 714defm CLRSR_branch : FU6_LU6_np<"clrsr">; 715} 716 717// U10 718// TODO ldwcpl, blacp 719 720let Defs = [R11], isReMaterializable = 1, neverHasSideEffects = 1 in 721def LDAP_u10 : _FU10< 722 (outs), 723 (ins i32imm:$addr), 724 "ldap r11, $addr", 725 []>; 726 727let Defs = [R11], isReMaterializable = 1 in 728def LDAP_lu10 : _FLU10< 729 (outs), 730 (ins i32imm:$addr), 731 "ldap r11, $addr", 732 [(set R11, (pcrelwrapper tglobaladdr:$addr))]>; 733 734let Defs = [R11], isReMaterializable = 1 in 735def LDAP_lu10_ba : _FLU10<(outs), 736 (ins i32imm:$addr), 737 "ldap r11, $addr", 738 [(set R11, (pcrelwrapper tblockaddress:$addr))]>; 739 740let isCall=1, 741// All calls clobber the link register and the non-callee-saved registers: 742Defs = [R0, R1, R2, R3, R11, LR], Uses = [SP] in { 743def BL_u10 : _FU10< 744 (outs), (ins calltarget:$target), 745 "bl $target", 746 [(XCoreBranchLink immU10:$target)]>; 747 748def BL_lu10 : _FLU10< 749 (outs), (ins calltarget:$target), 750 "bl $target", 751 [(XCoreBranchLink immU20:$target)]>; 752} 753 754// Two operand short 755// TODO eet, eef, tsetmr 756def NOT : _F2R<(outs GRRegs:$dst), (ins GRRegs:$b), 757 "not $dst, $b", 758 [(set GRRegs:$dst, (not GRRegs:$b))]>; 759 760def NEG : _F2R<(outs GRRegs:$dst), (ins GRRegs:$b), 761 "neg $dst, $b", 762 [(set GRRegs:$dst, (ineg GRRegs:$b))]>; 763 764let Constraints = "$src1 = $dst" in { 765def SEXT_rus : _FRUS<(outs GRRegs:$dst), (ins GRRegs:$src1, i32imm:$src2), 766 "sext $dst, $src2", 767 [(set GRRegs:$dst, (int_xcore_sext GRRegs:$src1, 768 immBitp:$src2))]>; 769 770def SEXT_2r : _FRUS<(outs GRRegs:$dst), (ins GRRegs:$src1, GRRegs:$src2), 771 "sext $dst, $src2", 772 [(set GRRegs:$dst, (int_xcore_sext GRRegs:$src1, 773 GRRegs:$src2))]>; 774 775def ZEXT_rus : _FRUS<(outs GRRegs:$dst), (ins GRRegs:$src1, i32imm:$src2), 776 "zext $dst, $src2", 777 [(set GRRegs:$dst, (int_xcore_zext GRRegs:$src1, 778 immBitp:$src2))]>; 779 780def ZEXT_2r : _FRUS<(outs GRRegs:$dst), (ins GRRegs:$src1, GRRegs:$src2), 781 "zext $dst, $src2", 782 [(set GRRegs:$dst, (int_xcore_zext GRRegs:$src1, 783 GRRegs:$src2))]>; 784 785def ANDNOT_2r : _F2R<(outs GRRegs:$dst), (ins GRRegs:$src1, GRRegs:$src2), 786 "andnot $dst, $src2", 787 [(set GRRegs:$dst, (and GRRegs:$src1, (not GRRegs:$src2)))]>; 788} 789 790let isReMaterializable = 1, neverHasSideEffects = 1 in 791def MKMSK_rus : _FRUS<(outs GRRegs:$dst), (ins i32imm:$size), 792 "mkmsk $dst, $size", 793 []>; 794 795def MKMSK_2r : _FRUS<(outs GRRegs:$dst), (ins GRRegs:$size), 796 "mkmsk $dst, $size", 797 [(set GRRegs:$dst, (add (shl 1, GRRegs:$size), -1))]>; 798 799def GETR_rus : _FRUS<(outs GRRegs:$dst), (ins i32imm:$type), 800 "getr $dst, $type", 801 [(set GRRegs:$dst, (int_xcore_getr immUs:$type))]>; 802 803def GETTS_2r : _F2R<(outs GRRegs:$dst), (ins GRRegs:$r), 804 "getts $dst, res[$r]", 805 [(set GRRegs:$dst, (int_xcore_getts GRRegs:$r))]>; 806 807def SETPT_2r : _F2R<(outs), (ins GRRegs:$r, GRRegs:$val), 808 "setpt res[$r], $val", 809 [(int_xcore_setpt GRRegs:$r, GRRegs:$val)]>; 810 811def OUTCT_2r : _F2R<(outs), (ins GRRegs:$r, GRRegs:$val), 812 "outct res[$r], $val", 813 [(int_xcore_outct GRRegs:$r, GRRegs:$val)]>; 814 815def OUTCT_rus : _F2R<(outs), (ins GRRegs:$r, i32imm:$val), 816 "outct res[$r], $val", 817 [(int_xcore_outct GRRegs:$r, immUs:$val)]>; 818 819def OUTT_2r : _F2R<(outs), (ins GRRegs:$r, GRRegs:$val), 820 "outt res[$r], $val", 821 [(int_xcore_outt GRRegs:$r, GRRegs:$val)]>; 822 823def OUT_2r : _F2R<(outs), (ins GRRegs:$r, GRRegs:$val), 824 "out res[$r], $val", 825 [(int_xcore_out GRRegs:$r, GRRegs:$val)]>; 826 827let Constraints = "$src = $dst" in 828def OUTSHR_2r : _F2R<(outs GRRegs:$dst), (ins GRRegs:$r, GRRegs:$src), 829 "outshr res[$r], $src", 830 [(set GRRegs:$dst, (int_xcore_outshr GRRegs:$r, 831 GRRegs:$src))]>; 832 833def INCT_2r : _F2R<(outs GRRegs:$dst), (ins GRRegs:$r), 834 "inct $dst, res[$r]", 835 [(set GRRegs:$dst, (int_xcore_inct GRRegs:$r))]>; 836 837def INT_2r : _F2R<(outs GRRegs:$dst), (ins GRRegs:$r), 838 "int $dst, res[$r]", 839 [(set GRRegs:$dst, (int_xcore_int GRRegs:$r))]>; 840 841def IN_2r : _F2R<(outs GRRegs:$dst), (ins GRRegs:$r), 842 "in $dst, res[$r]", 843 [(set GRRegs:$dst, (int_xcore_in GRRegs:$r))]>; 844 845let Constraints = "$src = $dst" in 846def INSHR_2r : _F2R<(outs GRRegs:$dst), (ins GRRegs:$r, GRRegs:$src), 847 "inshr $dst, res[$r]", 848 [(set GRRegs:$dst, (int_xcore_inshr GRRegs:$r, 849 GRRegs:$src))]>; 850 851def CHKCT_2r : _F2R<(outs), (ins GRRegs:$r, GRRegs:$val), 852 "chkct res[$r], $val", 853 [(int_xcore_chkct GRRegs:$r, GRRegs:$val)]>; 854 855def CHKCT_rus : _F2R<(outs), (ins GRRegs:$r, i32imm:$val), 856 "chkct res[$r], $val", 857 [(int_xcore_chkct GRRegs:$r, immUs:$val)]>; 858 859def TESTCT_2r : _F2R<(outs GRRegs:$dst), (ins GRRegs:$src), 860 "testct $dst, res[$src]", 861 [(set GRRegs:$dst, (int_xcore_testct GRRegs:$src))]>; 862 863def TESTWCT_2r : _F2R<(outs GRRegs:$dst), (ins GRRegs:$src), 864 "testwct $dst, res[$src]", 865 [(set GRRegs:$dst, (int_xcore_testwct GRRegs:$src))]>; 866 867def SETD_2r : _F2R<(outs), (ins GRRegs:$r, GRRegs:$val), 868 "setd res[$r], $val", 869 [(int_xcore_setd GRRegs:$r, GRRegs:$val)]>; 870 871def GETST_2r : _F2R<(outs GRRegs:$dst), (ins GRRegs:$r), 872 "getst $dst, res[$r]", 873 [(set GRRegs:$dst, (int_xcore_getst GRRegs:$r))]>; 874 875def INITSP_2r : _F2R<(outs), (ins GRRegs:$t, GRRegs:$src), 876 "init t[$t]:sp, $src", 877 [(int_xcore_initsp GRRegs:$t, GRRegs:$src)]>; 878 879def INITPC_2r : _F2R<(outs), (ins GRRegs:$t, GRRegs:$src), 880 "init t[$t]:pc, $src", 881 [(int_xcore_initpc GRRegs:$t, GRRegs:$src)]>; 882 883def INITCP_2r : _F2R<(outs), (ins GRRegs:$t, GRRegs:$src), 884 "init t[$t]:cp, $src", 885 [(int_xcore_initcp GRRegs:$t, GRRegs:$src)]>; 886 887def INITDP_2r : _F2R<(outs), (ins GRRegs:$t, GRRegs:$src), 888 "init t[$t]:dp, $src", 889 [(int_xcore_initdp GRRegs:$t, GRRegs:$src)]>; 890 891// Two operand long 892// getd, testlcl 893def BITREV_l2r : _FL2R<(outs GRRegs:$dst), (ins GRRegs:$src), 894 "bitrev $dst, $src", 895 [(set GRRegs:$dst, (int_xcore_bitrev GRRegs:$src))]>; 896 897def BYTEREV_l2r : _FL2R<(outs GRRegs:$dst), (ins GRRegs:$src), 898 "byterev $dst, $src", 899 [(set GRRegs:$dst, (bswap GRRegs:$src))]>; 900 901def CLZ_l2r : _FL2R<(outs GRRegs:$dst), (ins GRRegs:$src), 902 "clz $dst, $src", 903 [(set GRRegs:$dst, (ctlz GRRegs:$src))]>; 904 905def SETC_l2r : _FL2R<(outs), (ins GRRegs:$r, GRRegs:$val), 906 "setc res[$r], $val", 907 [(int_xcore_setc GRRegs:$r, GRRegs:$val)]>; 908 909def SETTW_l2r : _FL2R<(outs), (ins GRRegs:$r, GRRegs:$val), 910 "settw res[$r], $val", 911 [(int_xcore_settw GRRegs:$r, GRRegs:$val)]>; 912 913def GETPS_l2r : _FL2R<(outs GRRegs:$dst), (ins GRRegs:$src), 914 "get $dst, ps[$src]", 915 [(set GRRegs:$dst, (int_xcore_getps GRRegs:$src))]>; 916 917def SETPS_l2r : _FL2R<(outs), (ins GRRegs:$src1, GRRegs:$src2), 918 "set ps[$src1], $src2", 919 [(int_xcore_setps GRRegs:$src1, GRRegs:$src2)]>; 920 921def INITLR_l2r : _FL2R<(outs), (ins GRRegs:$t, GRRegs:$src), 922 "init t[$t]:lr, $src", 923 [(int_xcore_initlr GRRegs:$t, GRRegs:$src)]>; 924 925def SETCLK_l2r : _FL2R<(outs), (ins GRRegs:$src1, GRRegs:$src2), 926 "setclk res[$src1], $src2", 927 [(int_xcore_setclk GRRegs:$src1, GRRegs:$src2)]>; 928 929def SETRDY_l2r : _FL2R<(outs), (ins GRRegs:$src1, GRRegs:$src2), 930 "setrdy res[$src1], $src2", 931 [(int_xcore_setrdy GRRegs:$src1, GRRegs:$src2)]>; 932 933def SETPSC_l2r : _FL2R<(outs), (ins GRRegs:$src1, GRRegs:$src2), 934 "setpsc res[$src1], $src2", 935 [(int_xcore_setpsc GRRegs:$src1, GRRegs:$src2)]>; 936 937def PEEK_l2r : _FL2R<(outs GRRegs:$dst), (ins GRRegs:$src), 938 "peek $dst, res[$src]", 939 [(set GRRegs:$dst, (int_xcore_peek GRRegs:$src))]>; 940 941def ENDIN_l2r : _FL2R<(outs GRRegs:$dst), (ins GRRegs:$src), 942 "endin $dst, res[$src]", 943 [(set GRRegs:$dst, (int_xcore_endin GRRegs:$src))]>; 944 945// One operand short 946// TODO edu, eeu, waitet, waitef, tstart, clrtp 947// setdp, setcp, setev, kcall 948// dgetreg 949def MSYNC_1r : _F1R<(outs), (ins GRRegs:$i), 950 "msync res[$i]", 951 [(int_xcore_msync GRRegs:$i)]>; 952def MJOIN_1r : _F1R<(outs), (ins GRRegs:$i), 953 "mjoin res[$i]", 954 [(int_xcore_mjoin GRRegs:$i)]>; 955 956let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in 957def BAU_1r : _F1R<(outs), (ins GRRegs:$addr), 958 "bau $addr", 959 [(brind GRRegs:$addr)]>; 960 961let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in 962def BR_JT : PseudoInstXCore<(outs), (ins InlineJT:$t, GRRegs:$i), 963 "bru $i\n$t", 964 [(XCoreBR_JT tjumptable:$t, GRRegs:$i)]>; 965 966let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in 967def BR_JT32 : PseudoInstXCore<(outs), (ins InlineJT32:$t, GRRegs:$i), 968 "bru $i\n$t", 969 [(XCoreBR_JT32 tjumptable:$t, GRRegs:$i)]>; 970 971let Defs=[SP], neverHasSideEffects=1 in 972def SETSP_1r : _F1R<(outs), (ins GRRegs:$src), 973 "set sp, $src", 974 []>; 975 976let hasCtrlDep = 1 in 977def ECALLT_1r : _F1R<(outs), (ins GRRegs:$src), 978 "ecallt $src", 979 []>; 980 981let hasCtrlDep = 1 in 982def ECALLF_1r : _F1R<(outs), (ins GRRegs:$src), 983 "ecallf $src", 984 []>; 985 986let isCall=1, 987// All calls clobber the link register and the non-callee-saved registers: 988Defs = [R0, R1, R2, R3, R11, LR], Uses = [SP] in { 989def BLA_1r : _F1R<(outs), (ins GRRegs:$addr), 990 "bla $addr", 991 [(XCoreBranchLink GRRegs:$addr)]>; 992} 993 994def SYNCR_1r : _F1R<(outs), (ins GRRegs:$r), 995 "syncr res[$r]", 996 [(int_xcore_syncr GRRegs:$r)]>; 997 998def FREER_1r : _F1R<(outs), (ins GRRegs:$r), 999 "freer res[$r]", 1000 [(int_xcore_freer GRRegs:$r)]>; 1001 1002let Uses=[R11] in { 1003def SETV_1r : _F1R<(outs), (ins GRRegs:$r), 1004 "setv res[$r], r11", 1005 [(int_xcore_setv GRRegs:$r, R11)]>; 1006 1007def SETEV_1r : _F1R<(outs), (ins GRRegs:$r), 1008 "setev res[$r], r11", 1009 [(int_xcore_setev GRRegs:$r, R11)]>; 1010} 1011 1012def EEU_1r : _F1R<(outs), (ins GRRegs:$r), 1013 "eeu res[$r]", 1014 [(int_xcore_eeu GRRegs:$r)]>; 1015 1016// Zero operand short 1017// TODO freet, ldspc, stspc, ldssr, stssr, ldsed, stsed, 1018// stet, getkep, getksp, setkep, getid, kret, dcall, dret, 1019// dentsp, drestsp 1020 1021def CLRE_0R : _F0R<(outs), (ins), "clre", [(int_xcore_clre)]>; 1022 1023let Defs = [R11] in { 1024def GETID_0R : _F0R<(outs), (ins), 1025 "get r11, id", 1026 [(set R11, (int_xcore_getid))]>; 1027 1028def GETED_0R : _F0R<(outs), (ins), 1029 "get r11, ed", 1030 [(set R11, (int_xcore_geted))]>; 1031 1032def GETET_0R : _F0R<(outs), (ins), 1033 "get r11, et", 1034 [(set R11, (int_xcore_getet))]>; 1035} 1036 1037def SSYNC_0r : _F0R<(outs), (ins), 1038 "ssync", 1039 [(int_xcore_ssync)]>; 1040 1041let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1, 1042 hasSideEffects = 1 in 1043def WAITEU_0R : _F0R<(outs), (ins), 1044 "waiteu", 1045 [(brind (int_xcore_waitevent))]>; 1046 1047//===----------------------------------------------------------------------===// 1048// Non-Instruction Patterns 1049//===----------------------------------------------------------------------===// 1050 1051def : Pat<(XCoreBranchLink tglobaladdr:$addr), (BL_lu10 tglobaladdr:$addr)>; 1052def : Pat<(XCoreBranchLink texternalsym:$addr), (BL_lu10 texternalsym:$addr)>; 1053 1054/// sext_inreg 1055def : Pat<(sext_inreg GRRegs:$b, i1), (SEXT_rus GRRegs:$b, 1)>; 1056def : Pat<(sext_inreg GRRegs:$b, i8), (SEXT_rus GRRegs:$b, 8)>; 1057def : Pat<(sext_inreg GRRegs:$b, i16), (SEXT_rus GRRegs:$b, 16)>; 1058 1059/// loads 1060def : Pat<(zextloadi8 (add GRRegs:$addr, GRRegs:$offset)), 1061 (LD8U_3r GRRegs:$addr, GRRegs:$offset)>; 1062def : Pat<(zextloadi8 GRRegs:$addr), (LD8U_3r GRRegs:$addr, (LDC_ru6 0))>; 1063 1064def : Pat<(sextloadi16 (lda16f GRRegs:$addr, GRRegs:$offset)), 1065 (LD16S_3r GRRegs:$addr, GRRegs:$offset)>; 1066def : Pat<(sextloadi16 GRRegs:$addr), (LD16S_3r GRRegs:$addr, (LDC_ru6 0))>; 1067 1068def : Pat<(load (ldawf GRRegs:$addr, GRRegs:$offset)), 1069 (LDW_3r GRRegs:$addr, GRRegs:$offset)>; 1070def : Pat<(load (add GRRegs:$addr, immUs4:$offset)), 1071 (LDW_2rus GRRegs:$addr, (div4_xform immUs4:$offset))>; 1072def : Pat<(load GRRegs:$addr), (LDW_2rus GRRegs:$addr, 0)>; 1073 1074/// anyext 1075def : Pat<(extloadi8 (add GRRegs:$addr, GRRegs:$offset)), 1076 (LD8U_3r GRRegs:$addr, GRRegs:$offset)>; 1077def : Pat<(extloadi8 GRRegs:$addr), (LD8U_3r GRRegs:$addr, (LDC_ru6 0))>; 1078def : Pat<(extloadi16 (lda16f GRRegs:$addr, GRRegs:$offset)), 1079 (LD16S_3r GRRegs:$addr, GRRegs:$offset)>; 1080def : Pat<(extloadi16 GRRegs:$addr), (LD16S_3r GRRegs:$addr, (LDC_ru6 0))>; 1081 1082/// stores 1083def : Pat<(truncstorei8 GRRegs:$val, (add GRRegs:$addr, GRRegs:$offset)), 1084 (ST8_l3r GRRegs:$val, GRRegs:$addr, GRRegs:$offset)>; 1085def : Pat<(truncstorei8 GRRegs:$val, GRRegs:$addr), 1086 (ST8_l3r GRRegs:$val, GRRegs:$addr, (LDC_ru6 0))>; 1087 1088def : Pat<(truncstorei16 GRRegs:$val, (lda16f GRRegs:$addr, GRRegs:$offset)), 1089 (ST16_l3r GRRegs:$val, GRRegs:$addr, GRRegs:$offset)>; 1090def : Pat<(truncstorei16 GRRegs:$val, GRRegs:$addr), 1091 (ST16_l3r GRRegs:$val, GRRegs:$addr, (LDC_ru6 0))>; 1092 1093def : Pat<(store GRRegs:$val, (ldawf GRRegs:$addr, GRRegs:$offset)), 1094 (STW_3r GRRegs:$val, GRRegs:$addr, GRRegs:$offset)>; 1095def : Pat<(store GRRegs:$val, (add GRRegs:$addr, immUs4:$offset)), 1096 (STW_2rus GRRegs:$val, GRRegs:$addr, (div4_xform immUs4:$offset))>; 1097def : Pat<(store GRRegs:$val, GRRegs:$addr), 1098 (STW_2rus GRRegs:$val, GRRegs:$addr, 0)>; 1099 1100/// cttz 1101def : Pat<(cttz GRRegs:$src), (CLZ_l2r (BITREV_l2r GRRegs:$src))>; 1102 1103/// trap 1104def : Pat<(trap), (ECALLF_1r (LDC_ru6 0))>; 1105 1106/// 1107/// branch patterns 1108/// 1109 1110// unconditional branch 1111def : Pat<(br bb:$addr), (BRFU_lu6 bb:$addr)>; 1112 1113// direct match equal/notequal zero brcond 1114def : Pat<(brcond (setne GRRegs:$lhs, 0), bb:$dst), 1115 (BRFT_lru6 GRRegs:$lhs, bb:$dst)>; 1116def : Pat<(brcond (seteq GRRegs:$lhs, 0), bb:$dst), 1117 (BRFF_lru6 GRRegs:$lhs, bb:$dst)>; 1118 1119def : Pat<(brcond (setle GRRegs:$lhs, GRRegs:$rhs), bb:$dst), 1120 (BRFF_lru6 (LSS_3r GRRegs:$rhs, GRRegs:$lhs), bb:$dst)>; 1121def : Pat<(brcond (setule GRRegs:$lhs, GRRegs:$rhs), bb:$dst), 1122 (BRFF_lru6 (LSU_3r GRRegs:$rhs, GRRegs:$lhs), bb:$dst)>; 1123def : Pat<(brcond (setge GRRegs:$lhs, GRRegs:$rhs), bb:$dst), 1124 (BRFF_lru6 (LSS_3r GRRegs:$lhs, GRRegs:$rhs), bb:$dst)>; 1125def : Pat<(brcond (setuge GRRegs:$lhs, GRRegs:$rhs), bb:$dst), 1126 (BRFF_lru6 (LSU_3r GRRegs:$lhs, GRRegs:$rhs), bb:$dst)>; 1127def : Pat<(brcond (setne GRRegs:$lhs, GRRegs:$rhs), bb:$dst), 1128 (BRFF_lru6 (EQ_3r GRRegs:$lhs, GRRegs:$rhs), bb:$dst)>; 1129def : Pat<(brcond (setne GRRegs:$lhs, immUs:$rhs), bb:$dst), 1130 (BRFF_lru6 (EQ_2rus GRRegs:$lhs, immUs:$rhs), bb:$dst)>; 1131 1132// generic brcond pattern 1133def : Pat<(brcond GRRegs:$cond, bb:$addr), (BRFT_lru6 GRRegs:$cond, bb:$addr)>; 1134 1135 1136/// 1137/// Select patterns 1138/// 1139 1140// direct match equal/notequal zero select 1141def : Pat<(select (setne GRRegs:$lhs, 0), GRRegs:$T, GRRegs:$F), 1142 (SELECT_CC GRRegs:$lhs, GRRegs:$T, GRRegs:$F)>; 1143 1144def : Pat<(select (seteq GRRegs:$lhs, 0), GRRegs:$T, GRRegs:$F), 1145 (SELECT_CC GRRegs:$lhs, GRRegs:$F, GRRegs:$T)>; 1146 1147def : Pat<(select (setle GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F), 1148 (SELECT_CC (LSS_3r GRRegs:$rhs, GRRegs:$lhs), GRRegs:$F, GRRegs:$T)>; 1149def : Pat<(select (setule GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F), 1150 (SELECT_CC (LSU_3r GRRegs:$rhs, GRRegs:$lhs), GRRegs:$F, GRRegs:$T)>; 1151def : Pat<(select (setge GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F), 1152 (SELECT_CC (LSS_3r GRRegs:$lhs, GRRegs:$rhs), GRRegs:$F, GRRegs:$T)>; 1153def : Pat<(select (setuge GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F), 1154 (SELECT_CC (LSU_3r GRRegs:$lhs, GRRegs:$rhs), GRRegs:$F, GRRegs:$T)>; 1155def : Pat<(select (setne GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F), 1156 (SELECT_CC (EQ_3r GRRegs:$lhs, GRRegs:$rhs), GRRegs:$F, GRRegs:$T)>; 1157def : Pat<(select (setne GRRegs:$lhs, immUs:$rhs), GRRegs:$T, GRRegs:$F), 1158 (SELECT_CC (EQ_2rus GRRegs:$lhs, immUs:$rhs), GRRegs:$F, GRRegs:$T)>; 1159 1160/// 1161/// setcc patterns, only matched when none of the above brcond 1162/// patterns match 1163/// 1164 1165// setcc 2 register operands 1166def : Pat<(setle GRRegs:$lhs, GRRegs:$rhs), 1167 (EQ_2rus (LSS_3r GRRegs:$rhs, GRRegs:$lhs), 0)>; 1168def : Pat<(setule GRRegs:$lhs, GRRegs:$rhs), 1169 (EQ_2rus (LSU_3r GRRegs:$rhs, GRRegs:$lhs), 0)>; 1170 1171def : Pat<(setgt GRRegs:$lhs, GRRegs:$rhs), 1172 (LSS_3r GRRegs:$rhs, GRRegs:$lhs)>; 1173def : Pat<(setugt GRRegs:$lhs, GRRegs:$rhs), 1174 (LSU_3r GRRegs:$rhs, GRRegs:$lhs)>; 1175 1176def : Pat<(setge GRRegs:$lhs, GRRegs:$rhs), 1177 (EQ_2rus (LSS_3r GRRegs:$lhs, GRRegs:$rhs), 0)>; 1178def : Pat<(setuge GRRegs:$lhs, GRRegs:$rhs), 1179 (EQ_2rus (LSU_3r GRRegs:$lhs, GRRegs:$rhs), 0)>; 1180 1181def : Pat<(setlt GRRegs:$lhs, GRRegs:$rhs), 1182 (LSS_3r GRRegs:$lhs, GRRegs:$rhs)>; 1183def : Pat<(setult GRRegs:$lhs, GRRegs:$rhs), 1184 (LSU_3r GRRegs:$lhs, GRRegs:$rhs)>; 1185 1186def : Pat<(setne GRRegs:$lhs, GRRegs:$rhs), 1187 (EQ_2rus (EQ_3r GRRegs:$lhs, GRRegs:$rhs), 0)>; 1188 1189def : Pat<(seteq GRRegs:$lhs, GRRegs:$rhs), 1190 (EQ_3r GRRegs:$lhs, GRRegs:$rhs)>; 1191 1192// setcc reg/imm operands 1193def : Pat<(seteq GRRegs:$lhs, immUs:$rhs), 1194 (EQ_2rus GRRegs:$lhs, immUs:$rhs)>; 1195def : Pat<(setne GRRegs:$lhs, immUs:$rhs), 1196 (EQ_2rus (EQ_2rus GRRegs:$lhs, immUs:$rhs), 0)>; 1197 1198// misc 1199def : Pat<(add GRRegs:$addr, immUs4:$offset), 1200 (LDAWF_l2rus GRRegs:$addr, (div4_xform immUs4:$offset))>; 1201 1202def : Pat<(sub GRRegs:$addr, immUs4:$offset), 1203 (LDAWB_l2rus GRRegs:$addr, (div4_xform immUs4:$offset))>; 1204 1205def : Pat<(and GRRegs:$val, immMskBitp:$mask), 1206 (ZEXT_rus GRRegs:$val, (msksize_xform immMskBitp:$mask))>; 1207 1208// (sub X, imm) gets canonicalized to (add X, -imm). Match this form. 1209def : Pat<(add GRRegs:$src1, immUsNeg:$src2), 1210 (SUB_2rus GRRegs:$src1, (neg_xform immUsNeg:$src2))>; 1211 1212def : Pat<(add GRRegs:$src1, immUs4Neg:$src2), 1213 (LDAWB_l2rus GRRegs:$src1, (div4neg_xform immUs4Neg:$src2))>; 1214 1215/// 1216/// Some peepholes 1217/// 1218 1219def : Pat<(mul GRRegs:$src, 3), 1220 (LDA16F_l3r GRRegs:$src, GRRegs:$src)>; 1221 1222def : Pat<(mul GRRegs:$src, 5), 1223 (LDAWF_l3r GRRegs:$src, GRRegs:$src)>; 1224 1225def : Pat<(mul GRRegs:$src, -3), 1226 (LDAWB_l3r GRRegs:$src, GRRegs:$src)>; 1227 1228// ashr X, 32 is equivalent to ashr X, 31 on the XCore. 1229def : Pat<(sra GRRegs:$src, 31), 1230 (ASHR_l2rus GRRegs:$src, 32)>; 1231 1232def : Pat<(brcond (setlt GRRegs:$lhs, 0), bb:$dst), 1233 (BRFT_lru6 (ASHR_l2rus GRRegs:$lhs, 32), bb:$dst)>; 1234 1235// setge X, 0 is canonicalized to setgt X, -1 1236def : Pat<(brcond (setgt GRRegs:$lhs, -1), bb:$dst), 1237 (BRFF_lru6 (ASHR_l2rus GRRegs:$lhs, 32), bb:$dst)>; 1238 1239def : Pat<(select (setlt GRRegs:$lhs, 0), GRRegs:$T, GRRegs:$F), 1240 (SELECT_CC (ASHR_l2rus GRRegs:$lhs, 32), GRRegs:$T, GRRegs:$F)>; 1241 1242def : Pat<(select (setgt GRRegs:$lhs, -1), GRRegs:$T, GRRegs:$F), 1243 (SELECT_CC (ASHR_l2rus GRRegs:$lhs, 32), GRRegs:$F, GRRegs:$T)>; 1244 1245def : Pat<(setgt GRRegs:$lhs, -1), 1246 (EQ_2rus (ASHR_l2rus GRRegs:$lhs, 32), 0)>; 1247 1248def : Pat<(sra (shl GRRegs:$src, immBpwSubBitp:$imm), immBpwSubBitp:$imm), 1249 (SEXT_rus GRRegs:$src, (bpwsub_xform immBpwSubBitp:$imm))>; 1250