XCoreInstrInfo.td revision 226633
1193323Sed//===- XCoreInstrInfo.td - Target Description for XCore ----*- tablegen -*-===// 2193323Sed// 3193323Sed// The LLVM Compiler Infrastructure 4193323Sed// 5193323Sed// This file is distributed under the University of Illinois Open Source 6193323Sed// License. See LICENSE.TXT for details. 7193323Sed// 8193323Sed//===----------------------------------------------------------------------===// 9193323Sed// 10193323Sed// This file describes the XCore instructions in TableGen format. 11193323Sed// 12193323Sed//===----------------------------------------------------------------------===// 13193323Sed 14193323Sed// Uses of CP, DP are not currently reflected in the patterns, since 15193323Sed// having a physical register as an operand prevents loop hoisting and 16193323Sed// since the value of these registers never changes during the life of the 17193323Sed// function. 18193323Sed 19193323Sed//===----------------------------------------------------------------------===// 20193323Sed// Instruction format superclass. 21193323Sed//===----------------------------------------------------------------------===// 22193323Sed 23193323Sedinclude "XCoreInstrFormats.td" 24193323Sed 25193323Sed//===----------------------------------------------------------------------===// 26193323Sed// XCore specific DAG Nodes. 27193323Sed// 28193323Sed 29193323Sed// Call 30193323Seddef SDT_XCoreBranchLink : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>; 31193323Seddef XCoreBranchLink : SDNode<"XCoreISD::BL",SDT_XCoreBranchLink, 32218893Sdim [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 33205407Srdivacky SDNPVariadic]>; 34193323Sed 35206083Srdivackydef XCoreRetsp : SDNode<"XCoreISD::RETSP", SDTBrind, 36218893Sdim [SDNPHasChain, SDNPOptInGlue]>; 37193323Sed 38204642Srdivackydef SDT_XCoreBR_JT : SDTypeProfile<0, 2, 39204642Srdivacky [SDTCisVT<0, i32>, SDTCisVT<1, i32>]>; 40204642Srdivacky 41204642Srdivackydef XCoreBR_JT : SDNode<"XCoreISD::BR_JT", SDT_XCoreBR_JT, 42204642Srdivacky [SDNPHasChain]>; 43204642Srdivacky 44204642Srdivackydef XCoreBR_JT32 : SDNode<"XCoreISD::BR_JT32", SDT_XCoreBR_JT, 45204642Srdivacky [SDNPHasChain]>; 46204642Srdivacky 47193323Seddef SDT_XCoreAddress : SDTypeProfile<1, 1, 48193323Sed [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>; 49193323Sed 50193323Seddef pcrelwrapper : SDNode<"XCoreISD::PCRelativeWrapper", SDT_XCoreAddress, 51193323Sed []>; 52193323Sed 53193323Seddef dprelwrapper : SDNode<"XCoreISD::DPRelativeWrapper", SDT_XCoreAddress, 54193323Sed []>; 55193323Sed 56193323Seddef cprelwrapper : SDNode<"XCoreISD::CPRelativeWrapper", SDT_XCoreAddress, 57193323Sed []>; 58193323Sed 59193323Seddef SDT_XCoreStwsp : SDTypeProfile<0, 2, [SDTCisInt<1>]>; 60193323Seddef XCoreStwsp : SDNode<"XCoreISD::STWSP", SDT_XCoreStwsp, 61193323Sed [SDNPHasChain]>; 62193323Sed 63193323Sed// These are target-independent nodes, but have target-specific formats. 64193323Seddef SDT_XCoreCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>; 65193323Seddef SDT_XCoreCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, 66193323Sed SDTCisVT<1, i32> ]>; 67193323Sed 68193323Seddef callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_XCoreCallSeqStart, 69218893Sdim [SDNPHasChain, SDNPOutGlue]>; 70193323Seddef callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_XCoreCallSeqEnd, 71218893Sdim [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 72193323Sed 73193323Sed//===----------------------------------------------------------------------===// 74193323Sed// Instruction Pattern Stuff 75193323Sed//===----------------------------------------------------------------------===// 76193323Sed 77193323Seddef div4_xform : SDNodeXForm<imm, [{ 78193323Sed // Transformation function: imm/4 79193323Sed assert(N->getZExtValue() % 4 == 0); 80193323Sed return getI32Imm(N->getZExtValue()/4); 81193323Sed}]>; 82193323Sed 83193323Seddef msksize_xform : SDNodeXForm<imm, [{ 84193323Sed // Transformation function: get the size of a mask 85193323Sed assert(isMask_32(N->getZExtValue())); 86193323Sed // look for the first non-zero bit 87193323Sed return getI32Imm(32 - CountLeadingZeros_32(N->getZExtValue())); 88193323Sed}]>; 89193323Sed 90193323Seddef neg_xform : SDNodeXForm<imm, [{ 91193323Sed // Transformation function: -imm 92193323Sed uint32_t value = N->getZExtValue(); 93193323Sed return getI32Imm(-value); 94193323Sed}]>; 95193323Sed 96198090Srdivackydef bpwsub_xform : SDNodeXForm<imm, [{ 97198090Srdivacky // Transformation function: 32-imm 98198090Srdivacky uint32_t value = N->getZExtValue(); 99198090Srdivacky return getI32Imm(32-value); 100198090Srdivacky}]>; 101198090Srdivacky 102193323Seddef div4neg_xform : SDNodeXForm<imm, [{ 103193323Sed // Transformation function: -imm/4 104193323Sed uint32_t value = N->getZExtValue(); 105193323Sed assert(-value % 4 == 0); 106193323Sed return getI32Imm(-value/4); 107193323Sed}]>; 108193323Sed 109193323Seddef immUs4Neg : PatLeaf<(imm), [{ 110193323Sed uint32_t value = (uint32_t)N->getZExtValue(); 111193323Sed return (-value)%4 == 0 && (-value)/4 <= 11; 112193323Sed}]>; 113193323Sed 114193323Seddef immUs4 : PatLeaf<(imm), [{ 115193323Sed uint32_t value = (uint32_t)N->getZExtValue(); 116193323Sed return value%4 == 0 && value/4 <= 11; 117193323Sed}]>; 118193323Sed 119193323Seddef immUsNeg : PatLeaf<(imm), [{ 120193323Sed return -((uint32_t)N->getZExtValue()) <= 11; 121193323Sed}]>; 122193323Sed 123193323Seddef immUs : PatLeaf<(imm), [{ 124193323Sed return (uint32_t)N->getZExtValue() <= 11; 125193323Sed}]>; 126193323Sed 127193323Seddef immU6 : PatLeaf<(imm), [{ 128193323Sed return (uint32_t)N->getZExtValue() < (1 << 6); 129193323Sed}]>; 130193323Sed 131193323Seddef immU10 : PatLeaf<(imm), [{ 132193323Sed return (uint32_t)N->getZExtValue() < (1 << 10); 133193323Sed}]>; 134193323Sed 135193323Seddef immU16 : PatLeaf<(imm), [{ 136193323Sed return (uint32_t)N->getZExtValue() < (1 << 16); 137193323Sed}]>; 138193323Sed 139193323Seddef immU20 : PatLeaf<(imm), [{ 140193323Sed return (uint32_t)N->getZExtValue() < (1 << 20); 141193323Sed}]>; 142193323Sed 143212904Sdimdef immMskBitp : PatLeaf<(imm), [{ return immMskBitp(N); }]>; 144193323Sed 145193323Seddef immBitp : PatLeaf<(imm), [{ 146193323Sed uint32_t value = (uint32_t)N->getZExtValue(); 147193323Sed return (value >= 1 && value <= 8) 148193323Sed || value == 16 149193323Sed || value == 24 150193323Sed || value == 32; 151193323Sed}]>; 152193323Sed 153198090Srdivackydef immBpwSubBitp : PatLeaf<(imm), [{ 154198090Srdivacky uint32_t value = (uint32_t)N->getZExtValue(); 155198090Srdivacky return (value >= 24 && value <= 31) 156198090Srdivacky || value == 16 157198090Srdivacky || value == 8 158198090Srdivacky || value == 0; 159198090Srdivacky}]>; 160198090Srdivacky 161193323Seddef lda16f : PatFrag<(ops node:$addr, node:$offset), 162193323Sed (add node:$addr, (shl node:$offset, 1))>; 163193323Seddef lda16b : PatFrag<(ops node:$addr, node:$offset), 164193323Sed (sub node:$addr, (shl node:$offset, 1))>; 165193323Seddef ldawf : PatFrag<(ops node:$addr, node:$offset), 166193323Sed (add node:$addr, (shl node:$offset, 2))>; 167193323Seddef ldawb : PatFrag<(ops node:$addr, node:$offset), 168193323Sed (sub node:$addr, (shl node:$offset, 2))>; 169193323Sed 170193323Sed// Instruction operand types 171193323Seddef calltarget : Operand<i32>; 172193323Seddef brtarget : Operand<OtherVT>; 173193323Seddef pclabel : Operand<i32>; 174193323Sed 175193323Sed// Addressing modes 176193323Seddef ADDRspii : ComplexPattern<i32, 2, "SelectADDRspii", [add, frameindex], []>; 177193323Seddef ADDRdpii : ComplexPattern<i32, 2, "SelectADDRdpii", [add, dprelwrapper], 178193323Sed []>; 179193323Seddef ADDRcpii : ComplexPattern<i32, 2, "SelectADDRcpii", [add, cprelwrapper], 180193323Sed []>; 181193323Sed 182193323Sed// Address operands 183193323Seddef MEMii : Operand<i32> { 184193323Sed let PrintMethod = "printMemOperand"; 185193323Sed let MIOperandInfo = (ops i32imm, i32imm); 186193323Sed} 187193323Sed 188204642Srdivacky// Jump tables. 189204642Srdivackydef InlineJT : Operand<i32> { 190204642Srdivacky let PrintMethod = "printInlineJT"; 191204642Srdivacky} 192204642Srdivacky 193204642Srdivackydef InlineJT32 : Operand<i32> { 194204642Srdivacky let PrintMethod = "printInlineJT32"; 195204642Srdivacky} 196204642Srdivacky 197193323Sed//===----------------------------------------------------------------------===// 198193323Sed// Instruction Class Templates 199193323Sed//===----------------------------------------------------------------------===// 200193323Sed 201193323Sed// Three operand short 202193323Sed 203193323Sedmulticlass F3R_2RUS<string OpcStr, SDNode OpNode> { 204193323Sed def _3r: _F3R< 205193323Sed (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), 206193323Sed !strconcat(OpcStr, " $dst, $b, $c"), 207193323Sed [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>; 208193323Sed def _2rus : _F2RUS< 209193323Sed (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c), 210193323Sed !strconcat(OpcStr, " $dst, $b, $c"), 211193323Sed [(set GRRegs:$dst, (OpNode GRRegs:$b, immUs:$c))]>; 212193323Sed} 213193323Sed 214193323Sedmulticlass F3R_2RUS_np<string OpcStr> { 215193323Sed def _3r: _F3R< 216193323Sed (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), 217193323Sed !strconcat(OpcStr, " $dst, $b, $c"), 218193323Sed []>; 219193323Sed def _2rus : _F2RUS< 220193323Sed (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c), 221193323Sed !strconcat(OpcStr, " $dst, $b, $c"), 222193323Sed []>; 223193323Sed} 224193323Sed 225193323Sedmulticlass F3R_2RBITP<string OpcStr, SDNode OpNode> { 226193323Sed def _3r: _F3R< 227193323Sed (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), 228193323Sed !strconcat(OpcStr, " $dst, $b, $c"), 229193323Sed [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>; 230193323Sed def _2rus : _F2RUS< 231193323Sed (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c), 232193323Sed !strconcat(OpcStr, " $dst, $b, $c"), 233193323Sed [(set GRRegs:$dst, (OpNode GRRegs:$b, immBitp:$c))]>; 234193323Sed} 235193323Sed 236193323Sedclass F3R<string OpcStr, SDNode OpNode> : _F3R< 237193323Sed (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), 238193323Sed !strconcat(OpcStr, " $dst, $b, $c"), 239193323Sed [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>; 240193323Sed 241193323Sedclass F3R_np<string OpcStr> : _F3R< 242193323Sed (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), 243193323Sed !strconcat(OpcStr, " $dst, $b, $c"), 244193323Sed []>; 245193323Sed// Three operand long 246193323Sed 247193323Sed/// FL3R_L2RUS multiclass - Define a normal FL3R/FL2RUS pattern in one shot. 248193323Sedmulticlass FL3R_L2RUS<string OpcStr, SDNode OpNode> { 249193323Sed def _l3r: _FL3R< 250193323Sed (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), 251193323Sed !strconcat(OpcStr, " $dst, $b, $c"), 252193323Sed [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>; 253193323Sed def _l2rus : _FL2RUS< 254193323Sed (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c), 255193323Sed !strconcat(OpcStr, " $dst, $b, $c"), 256193323Sed [(set GRRegs:$dst, (OpNode GRRegs:$b, immUs:$c))]>; 257193323Sed} 258193323Sed 259193323Sed/// FL3R_L2RUS multiclass - Define a normal FL3R/FL2RUS pattern in one shot. 260193323Sedmulticlass FL3R_L2RBITP<string OpcStr, SDNode OpNode> { 261193323Sed def _l3r: _FL3R< 262193323Sed (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), 263193323Sed !strconcat(OpcStr, " $dst, $b, $c"), 264193323Sed [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>; 265193323Sed def _l2rus : _FL2RUS< 266193323Sed (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c), 267193323Sed !strconcat(OpcStr, " $dst, $b, $c"), 268193323Sed [(set GRRegs:$dst, (OpNode GRRegs:$b, immBitp:$c))]>; 269193323Sed} 270193323Sed 271193323Sedclass FL3R<string OpcStr, SDNode OpNode> : _FL3R< 272193323Sed (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), 273193323Sed !strconcat(OpcStr, " $dst, $b, $c"), 274193323Sed [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>; 275193323Sed 276193323Sed// Register - U6 277193323Sed// Operand register - U6 278193323Sedmulticlass FRU6_LRU6_branch<string OpcStr> { 279193323Sed def _ru6: _FRU6< 280193323Sed (outs), (ins GRRegs:$cond, brtarget:$dest), 281193323Sed !strconcat(OpcStr, " $cond, $dest"), 282193323Sed []>; 283193323Sed def _lru6: _FLRU6< 284193323Sed (outs), (ins GRRegs:$cond, brtarget:$dest), 285193323Sed !strconcat(OpcStr, " $cond, $dest"), 286193323Sed []>; 287193323Sed} 288193323Sed 289193323Sedmulticlass FRU6_LRU6_cp<string OpcStr> { 290193323Sed def _ru6: _FRU6< 291193323Sed (outs GRRegs:$dst), (ins i32imm:$a), 292193323Sed !strconcat(OpcStr, " $dst, cp[$a]"), 293193323Sed []>; 294193323Sed def _lru6: _FLRU6< 295193323Sed (outs GRRegs:$dst), (ins i32imm:$a), 296193323Sed !strconcat(OpcStr, " $dst, cp[$a]"), 297193323Sed []>; 298193323Sed} 299193323Sed 300193323Sed// U6 301193323Sedmulticlass FU6_LU6<string OpcStr, SDNode OpNode> { 302193323Sed def _u6: _FU6< 303193323Sed (outs), (ins i32imm:$b), 304193323Sed !strconcat(OpcStr, " $b"), 305193323Sed [(OpNode immU6:$b)]>; 306193323Sed def _lu6: _FLU6< 307193323Sed (outs), (ins i32imm:$b), 308193323Sed !strconcat(OpcStr, " $b"), 309193323Sed [(OpNode immU16:$b)]>; 310193323Sed} 311221345Sdimmulticlass FU6_LU6_int<string OpcStr, Intrinsic Int> { 312221345Sdim def _u6: _FU6< 313221345Sdim (outs), (ins i32imm:$b), 314221345Sdim !strconcat(OpcStr, " $b"), 315221345Sdim [(Int immU6:$b)]>; 316221345Sdim def _lu6: _FLU6< 317221345Sdim (outs), (ins i32imm:$b), 318221345Sdim !strconcat(OpcStr, " $b"), 319221345Sdim [(Int immU16:$b)]>; 320221345Sdim} 321193323Sed 322193323Sedmulticlass FU6_LU6_np<string OpcStr> { 323193323Sed def _u6: _FU6< 324193323Sed (outs), (ins i32imm:$b), 325193323Sed !strconcat(OpcStr, " $b"), 326193323Sed []>; 327193323Sed def _lu6: _FLU6< 328193323Sed (outs), (ins i32imm:$b), 329193323Sed !strconcat(OpcStr, " $b"), 330193323Sed []>; 331193323Sed} 332193323Sed 333193323Sed// U10 334193323Sedmulticlass FU10_LU10_np<string OpcStr> { 335193323Sed def _u10: _FU10< 336193323Sed (outs), (ins i32imm:$b), 337193323Sed !strconcat(OpcStr, " $b"), 338193323Sed []>; 339193323Sed def _lu10: _FLU10< 340193323Sed (outs), (ins i32imm:$b), 341193323Sed !strconcat(OpcStr, " $b"), 342193323Sed []>; 343193323Sed} 344193323Sed 345193323Sed// Two operand short 346193323Sed 347193323Sedclass F2R_np<string OpcStr> : _F2R< 348193323Sed (outs GRRegs:$dst), (ins GRRegs:$b), 349193323Sed !strconcat(OpcStr, " $dst, $b"), 350193323Sed []>; 351193323Sed 352193323Sed// Two operand long 353193323Sed 354193323Sed//===----------------------------------------------------------------------===// 355193323Sed// Pseudo Instructions 356193323Sed//===----------------------------------------------------------------------===// 357193323Sed 358193323Sedlet Defs = [SP], Uses = [SP] in { 359193323Seddef ADJCALLSTACKDOWN : PseudoInstXCore<(outs), (ins i32imm:$amt), 360193323Sed "${:comment} ADJCALLSTACKDOWN $amt", 361193323Sed [(callseq_start timm:$amt)]>; 362193323Seddef ADJCALLSTACKUP : PseudoInstXCore<(outs), (ins i32imm:$amt1, i32imm:$amt2), 363193323Sed "${:comment} ADJCALLSTACKUP $amt1", 364193323Sed [(callseq_end timm:$amt1, timm:$amt2)]>; 365193323Sed} 366193323Sed 367193323Seddef LDWFI : PseudoInstXCore<(outs GRRegs:$dst), (ins MEMii:$addr), 368193323Sed "${:comment} LDWFI $dst, $addr", 369193323Sed [(set GRRegs:$dst, (load ADDRspii:$addr))]>; 370193323Sed 371193323Seddef LDAWFI : PseudoInstXCore<(outs GRRegs:$dst), (ins MEMii:$addr), 372193323Sed "${:comment} LDAWFI $dst, $addr", 373193323Sed [(set GRRegs:$dst, ADDRspii:$addr)]>; 374193323Sed 375193323Seddef STWFI : PseudoInstXCore<(outs), (ins GRRegs:$src, MEMii:$addr), 376193323Sed "${:comment} STWFI $src, $addr", 377193323Sed [(store GRRegs:$src, ADDRspii:$addr)]>; 378193323Sed 379198892Srdivacky// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after 380198892Srdivacky// instruction selection into a branch sequence. 381198892Srdivackylet usesCustomInserter = 1 in { 382193323Sed def SELECT_CC : PseudoInstXCore<(outs GRRegs:$dst), 383193323Sed (ins GRRegs:$cond, GRRegs:$T, GRRegs:$F), 384193323Sed "${:comment} SELECT_CC PSEUDO!", 385193323Sed [(set GRRegs:$dst, 386193323Sed (select GRRegs:$cond, GRRegs:$T, GRRegs:$F))]>; 387193323Sed} 388193323Sed 389193323Sed//===----------------------------------------------------------------------===// 390193323Sed// Instructions 391193323Sed//===----------------------------------------------------------------------===// 392193323Sed 393193323Sed// Three operand short 394193323Seddefm ADD : F3R_2RUS<"add", add>; 395193323Seddefm SUB : F3R_2RUS<"sub", sub>; 396193323Sedlet neverHasSideEffects = 1 in { 397193323Seddefm EQ : F3R_2RUS_np<"eq">; 398193323Seddef LSS_3r : F3R_np<"lss">; 399193323Seddef LSU_3r : F3R_np<"lsu">; 400193323Sed} 401193323Seddef AND_3r : F3R<"and", and>; 402193323Seddef OR_3r : F3R<"or", or>; 403193323Sed 404193323Sedlet mayLoad=1 in { 405193323Seddef LDW_3r : _F3R<(outs GRRegs:$dst), (ins GRRegs:$addr, GRRegs:$offset), 406193323Sed "ldw $dst, $addr[$offset]", 407193323Sed []>; 408193323Sed 409193323Seddef LDW_2rus : _F2RUS<(outs GRRegs:$dst), (ins GRRegs:$addr, i32imm:$offset), 410193323Sed "ldw $dst, $addr[$offset]", 411193323Sed []>; 412193323Sed 413193323Seddef LD16S_3r : _F3R<(outs GRRegs:$dst), (ins GRRegs:$addr, GRRegs:$offset), 414193323Sed "ld16s $dst, $addr[$offset]", 415193323Sed []>; 416193323Sed 417193323Seddef LD8U_3r : _F3R<(outs GRRegs:$dst), (ins GRRegs:$addr, GRRegs:$offset), 418193323Sed "ld8u $dst, $addr[$offset]", 419193323Sed []>; 420193323Sed} 421193323Sed 422193323Sedlet mayStore=1 in { 423193323Seddef STW_3r : _F3R<(outs), (ins GRRegs:$val, GRRegs:$addr, GRRegs:$offset), 424193323Sed "stw $val, $addr[$offset]", 425193323Sed []>; 426193323Sed 427193323Seddef STW_2rus : _F2RUS<(outs), (ins GRRegs:$val, GRRegs:$addr, i32imm:$offset), 428193323Sed "stw $val, $addr[$offset]", 429193323Sed []>; 430193323Sed} 431193323Sed 432193323Seddefm SHL : F3R_2RBITP<"shl", shl>; 433193323Seddefm SHR : F3R_2RBITP<"shr", srl>; 434193323Sed// TODO tsetr 435193323Sed 436193323Sed// Three operand long 437193323Seddef LDAWF_l3r : _FL3R<(outs GRRegs:$dst), (ins GRRegs:$addr, GRRegs:$offset), 438193323Sed "ldaw $dst, $addr[$offset]", 439193323Sed [(set GRRegs:$dst, (ldawf GRRegs:$addr, GRRegs:$offset))]>; 440193323Sed 441193323Sedlet neverHasSideEffects = 1 in 442193323Seddef LDAWF_l2rus : _FL2RUS<(outs GRRegs:$dst), 443193323Sed (ins GRRegs:$addr, i32imm:$offset), 444193323Sed "ldaw $dst, $addr[$offset]", 445193323Sed []>; 446193323Sed 447193323Seddef LDAWB_l3r : _FL3R<(outs GRRegs:$dst), (ins GRRegs:$addr, GRRegs:$offset), 448193323Sed "ldaw $dst, $addr[-$offset]", 449193323Sed [(set GRRegs:$dst, (ldawb GRRegs:$addr, GRRegs:$offset))]>; 450193323Sed 451193323Sedlet neverHasSideEffects = 1 in 452193323Seddef LDAWB_l2rus : _FL2RUS<(outs GRRegs:$dst), 453193323Sed (ins GRRegs:$addr, i32imm:$offset), 454193323Sed "ldaw $dst, $addr[-$offset]", 455193323Sed []>; 456193323Sed 457193323Seddef LDA16F_l3r : _FL3R<(outs GRRegs:$dst), (ins GRRegs:$addr, GRRegs:$offset), 458193323Sed "lda16 $dst, $addr[$offset]", 459193323Sed [(set GRRegs:$dst, (lda16f GRRegs:$addr, GRRegs:$offset))]>; 460193323Sed 461193323Seddef LDA16B_l3r : _FL3R<(outs GRRegs:$dst), (ins GRRegs:$addr, GRRegs:$offset), 462193323Sed "lda16 $dst, $addr[-$offset]", 463193323Sed [(set GRRegs:$dst, (lda16b GRRegs:$addr, GRRegs:$offset))]>; 464193323Sed 465193323Seddef MUL_l3r : FL3R<"mul", mul>; 466193323Sed// Instructions which may trap are marked as side effecting. 467193323Sedlet hasSideEffects = 1 in { 468193323Seddef DIVS_l3r : FL3R<"divs", sdiv>; 469193323Seddef DIVU_l3r : FL3R<"divu", udiv>; 470193323Seddef REMS_l3r : FL3R<"rems", srem>; 471193323Seddef REMU_l3r : FL3R<"remu", urem>; 472193323Sed} 473193323Seddef XOR_l3r : FL3R<"xor", xor>; 474193323Seddefm ASHR : FL3R_L2RBITP<"ashr", sra>; 475223017Sdim 476223017Sdimlet Constraints = "$src1 = $dst" in 477223017Sdimdef CRC_l3r : _FL3R<(outs GRRegs:$dst), 478223017Sdim (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3), 479223017Sdim "crc32 $dst, $src2, $src3", 480223017Sdim [(set GRRegs:$dst, 481223017Sdim (int_xcore_crc32 GRRegs:$src1, GRRegs:$src2, 482223017Sdim GRRegs:$src3))]>; 483223017Sdim 484223017Sdim// TODO inpw, outpw 485193323Sedlet mayStore=1 in { 486193323Seddef ST16_l3r : _FL3R<(outs), (ins GRRegs:$val, GRRegs:$addr, GRRegs:$offset), 487193323Sed "st16 $val, $addr[$offset]", 488193323Sed []>; 489193323Sed 490193323Seddef ST8_l3r : _FL3R<(outs), (ins GRRegs:$val, GRRegs:$addr, GRRegs:$offset), 491193323Sed "st8 $val, $addr[$offset]", 492193323Sed []>; 493193323Sed} 494193323Sed 495193323Sed// Four operand long 496198090Srdivackylet Constraints = "$src1 = $dst1,$src2 = $dst2" in { 497193323Seddef MACCU_l4r : _L4R<(outs GRRegs:$dst1, GRRegs:$dst2), 498193323Sed (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3, 499193323Sed GRRegs:$src4), 500193323Sed "maccu $dst1, $dst2, $src3, $src4", 501193323Sed []>; 502193323Sed 503193323Seddef MACCS_l4r : _L4R<(outs GRRegs:$dst1, GRRegs:$dst2), 504193323Sed (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3, 505193323Sed GRRegs:$src4), 506193323Sed "maccs $dst1, $dst2, $src3, $src4", 507193323Sed []>; 508193323Sed} 509193323Sed 510223017Sdimlet Constraints = "$src1 = $dst1" in 511223017Sdimdef CRC8_l4r : _L4R<(outs GRRegs:$dst1, GRRegs:$dst2), 512223017Sdim (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3), 513223017Sdim "crc8 $dst1, $dst2, $src2, $src3", 514223017Sdim []>; 515223017Sdim 516193323Sed// Five operand long 517193323Sed 518193323Seddef LADD_l5r : _L5R<(outs GRRegs:$dst1, GRRegs:$dst2), 519193323Sed (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3), 520193323Sed "ladd $dst1, $dst2, $src1, $src2, $src3", 521193323Sed []>; 522193323Sed 523193323Seddef LSUB_l5r : _L5R<(outs GRRegs:$dst1, GRRegs:$dst2), 524193323Sed (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3), 525193323Sed "lsub $dst1, $dst2, $src1, $src2, $src3", 526193323Sed []>; 527193323Sed 528193323Seddef LDIV_l5r : _L5R<(outs GRRegs:$dst1, GRRegs:$dst2), 529193323Sed (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3), 530193323Sed "ldiv $dst1, $dst2, $src1, $src2, $src3", 531193323Sed []>; 532193323Sed 533193323Sed// Six operand long 534193323Sed 535193323Seddef LMUL_l6r : _L6R<(outs GRRegs:$dst1, GRRegs:$dst2), 536193323Sed (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3, 537193323Sed GRRegs:$src4), 538193323Sed "lmul $dst1, $dst2, $src1, $src2, $src3, $src4", 539193323Sed []>; 540193323Sed 541193323Sed// Register - U6 542193323Sed 543193323Sed//let Uses = [DP] in ... 544193323Sedlet neverHasSideEffects = 1, isReMaterializable = 1 in 545193323Seddef LDAWDP_ru6: _FRU6<(outs GRRegs:$dst), (ins MEMii:$a), 546193323Sed "ldaw $dst, dp[$a]", 547193323Sed []>; 548193323Sed 549193323Sedlet isReMaterializable = 1 in 550193323Seddef LDAWDP_lru6: _FLRU6< 551193323Sed (outs GRRegs:$dst), (ins MEMii:$a), 552193323Sed "ldaw $dst, dp[$a]", 553193323Sed [(set GRRegs:$dst, ADDRdpii:$a)]>; 554193323Sed 555193323Sedlet mayLoad=1 in 556193323Seddef LDWDP_ru6: _FRU6<(outs GRRegs:$dst), (ins MEMii:$a), 557193323Sed "ldw $dst, dp[$a]", 558193323Sed []>; 559193323Sed 560193323Seddef LDWDP_lru6: _FLRU6< 561193323Sed (outs GRRegs:$dst), (ins MEMii:$a), 562193323Sed "ldw $dst, dp[$a]", 563193323Sed [(set GRRegs:$dst, (load ADDRdpii:$a))]>; 564193323Sed 565193323Sedlet mayStore=1 in 566193323Seddef STWDP_ru6 : _FRU6<(outs), (ins GRRegs:$val, MEMii:$addr), 567193323Sed "stw $val, dp[$addr]", 568193323Sed []>; 569193323Sed 570193323Seddef STWDP_lru6 : _FLRU6<(outs), (ins GRRegs:$val, MEMii:$addr), 571193323Sed "stw $val, dp[$addr]", 572193323Sed [(store GRRegs:$val, ADDRdpii:$addr)]>; 573193323Sed 574193323Sed//let Uses = [CP] in .. 575226633Sdimlet mayLoad = 1, isReMaterializable = 1, neverHasSideEffects = 1 in 576193323Seddefm LDWCP : FRU6_LRU6_cp<"ldw">; 577193323Sed 578193323Sedlet Uses = [SP] in { 579193323Sedlet mayStore=1 in { 580193323Seddef STWSP_ru6 : _FRU6< 581193323Sed (outs), (ins GRRegs:$val, i32imm:$index), 582193323Sed "stw $val, sp[$index]", 583193323Sed [(XCoreStwsp GRRegs:$val, immU6:$index)]>; 584193323Sed 585193323Seddef STWSP_lru6 : _FLRU6< 586193323Sed (outs), (ins GRRegs:$val, i32imm:$index), 587193323Sed "stw $val, sp[$index]", 588193323Sed [(XCoreStwsp GRRegs:$val, immU16:$index)]>; 589193323Sed} 590193323Sed 591193323Sedlet mayLoad=1 in { 592193323Seddef LDWSP_ru6 : _FRU6< 593193323Sed (outs GRRegs:$dst), (ins i32imm:$b), 594193323Sed "ldw $dst, sp[$b]", 595193323Sed []>; 596193323Sed 597193323Seddef LDWSP_lru6 : _FLRU6< 598193323Sed (outs GRRegs:$dst), (ins i32imm:$b), 599193323Sed "ldw $dst, sp[$b]", 600193323Sed []>; 601193323Sed} 602193323Sed 603193323Sedlet neverHasSideEffects = 1 in { 604193323Seddef LDAWSP_ru6 : _FRU6< 605193323Sed (outs GRRegs:$dst), (ins i32imm:$b), 606193323Sed "ldaw $dst, sp[$b]", 607193323Sed []>; 608193323Sed 609193323Seddef LDAWSP_lru6 : _FLRU6< 610193323Sed (outs GRRegs:$dst), (ins i32imm:$b), 611193323Sed "ldaw $dst, sp[$b]", 612193323Sed []>; 613193323Sed 614193323Seddef LDAWSP_ru6_RRegs : _FRU6< 615193323Sed (outs RRegs:$dst), (ins i32imm:$b), 616193323Sed "ldaw $dst, sp[$b]", 617193323Sed []>; 618193323Sed 619193323Seddef LDAWSP_lru6_RRegs : _FLRU6< 620193323Sed (outs RRegs:$dst), (ins i32imm:$b), 621193323Sed "ldaw $dst, sp[$b]", 622193323Sed []>; 623193323Sed} 624193323Sed} 625193323Sed 626193323Sedlet isReMaterializable = 1 in { 627193323Seddef LDC_ru6 : _FRU6< 628193323Sed (outs GRRegs:$dst), (ins i32imm:$b), 629193323Sed "ldc $dst, $b", 630193323Sed [(set GRRegs:$dst, immU6:$b)]>; 631193323Sed 632193323Seddef LDC_lru6 : _FLRU6< 633193323Sed (outs GRRegs:$dst), (ins i32imm:$b), 634193323Sed "ldc $dst, $b", 635193323Sed [(set GRRegs:$dst, immU16:$b)]>; 636193323Sed} 637193323Sed 638218893Sdimdef SETC_ru6 : _FRU6<(outs), (ins GRRegs:$r, i32imm:$val), 639218893Sdim "setc res[$r], $val", 640218893Sdim [(int_xcore_setc GRRegs:$r, immU6:$val)]>; 641218893Sdim 642218893Sdimdef SETC_lru6 : _FLRU6<(outs), (ins GRRegs:$r, i32imm:$val), 643218893Sdim "setc res[$r], $val", 644218893Sdim [(int_xcore_setc GRRegs:$r, immU16:$val)]>; 645218893Sdim 646193323Sed// Operand register - U6 647193323Sedlet isBranch = 1, isTerminator = 1 in { 648193323Seddefm BRFT: FRU6_LRU6_branch<"bt">; 649193323Seddefm BRBT: FRU6_LRU6_branch<"bt">; 650193323Seddefm BRFF: FRU6_LRU6_branch<"bf">; 651193323Seddefm BRBF: FRU6_LRU6_branch<"bf">; 652193323Sed} 653193323Sed 654193323Sed// U6 655193323Sedlet Defs = [SP], Uses = [SP] in { 656193323Sedlet neverHasSideEffects = 1 in 657193323Seddefm EXTSP : FU6_LU6_np<"extsp">; 658193323Sedlet mayStore = 1 in 659193323Seddefm ENTSP : FU6_LU6_np<"entsp">; 660193323Sed 661199481Srdivackylet isReturn = 1, isTerminator = 1, mayLoad = 1, isBarrier = 1 in { 662193323Seddefm RETSP : FU6_LU6<"retsp", XCoreRetsp>; 663193323Sed} 664193323Sed} 665193323Sed 666221345Sdim// TODO extdp, kentsp, krestsp, blat 667221345Sdim// getsr, kalli 668204642Srdivackylet isBranch = 1, isTerminator = 1, isBarrier = 1 in { 669193323Seddef BRBU_u6 : _FU6< 670193323Sed (outs), 671193323Sed (ins brtarget:$target), 672193323Sed "bu $target", 673193323Sed []>; 674193323Sed 675193323Seddef BRBU_lu6 : _FLU6< 676193323Sed (outs), 677193323Sed (ins brtarget:$target), 678193323Sed "bu $target", 679193323Sed []>; 680193323Sed 681193323Seddef BRFU_u6 : _FU6< 682193323Sed (outs), 683193323Sed (ins brtarget:$target), 684193323Sed "bu $target", 685193323Sed []>; 686193323Sed 687193323Seddef BRFU_lu6 : _FLU6< 688193323Sed (outs), 689193323Sed (ins brtarget:$target), 690193323Sed "bu $target", 691193323Sed []>; 692193323Sed} 693193323Sed 694193323Sed//let Uses = [CP] in ... 695198090Srdivackylet Defs = [R11], neverHasSideEffects = 1, isReMaterializable = 1 in 696193323Seddef LDAWCP_u6: _FRU6<(outs), (ins MEMii:$a), 697193323Sed "ldaw r11, cp[$a]", 698193323Sed []>; 699193323Sed 700198090Srdivackylet Defs = [R11], isReMaterializable = 1 in 701193323Seddef LDAWCP_lu6: _FLRU6< 702193323Sed (outs), (ins MEMii:$a), 703193323Sed "ldaw r11, cp[$a]", 704193323Sed [(set R11, ADDRcpii:$a)]>; 705193323Sed 706221345Sdimdefm SETSR : FU6_LU6_int<"setsr", int_xcore_setsr>; 707221345Sdim 708221345Sdimdefm CLRSR : FU6_LU6_int<"clrsr", int_xcore_clrsr>; 709221345Sdim 710221345Sdim// setsr may cause a branch if it is used to enable events. clrsr may 711221345Sdim// branch if it is executed while events are enabled. 712221345Sdimlet isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in { 713221345Sdimdefm SETSR_branch : FU6_LU6_np<"setsr">; 714221345Sdimdefm CLRSR_branch : FU6_LU6_np<"clrsr">; 715221345Sdim} 716221345Sdim 717193323Sed// U10 718193323Sed// TODO ldwcpl, blacp 719193323Sed 720193323Sedlet Defs = [R11], isReMaterializable = 1, neverHasSideEffects = 1 in 721193323Seddef LDAP_u10 : _FU10< 722193323Sed (outs), 723193323Sed (ins i32imm:$addr), 724193323Sed "ldap r11, $addr", 725193323Sed []>; 726193323Sed 727193323Sedlet Defs = [R11], isReMaterializable = 1 in 728193323Seddef LDAP_lu10 : _FLU10< 729193323Sed (outs), 730193323Sed (ins i32imm:$addr), 731193323Sed "ldap r11, $addr", 732193323Sed [(set R11, (pcrelwrapper tglobaladdr:$addr))]>; 733193323Sed 734199511Srdivackylet Defs = [R11], isReMaterializable = 1 in 735199511Srdivackydef LDAP_lu10_ba : _FLU10<(outs), 736199511Srdivacky (ins i32imm:$addr), 737199511Srdivacky "ldap r11, $addr", 738199511Srdivacky [(set R11, (pcrelwrapper tblockaddress:$addr))]>; 739199511Srdivacky 740193323Sedlet isCall=1, 741203954Srdivacky// All calls clobber the link register and the non-callee-saved registers: 742226633SdimDefs = [R0, R1, R2, R3, R11, LR], Uses = [SP] in { 743193323Seddef BL_u10 : _FU10< 744193323Sed (outs), 745193323Sed (ins calltarget:$target, variable_ops), 746193323Sed "bl $target", 747193323Sed [(XCoreBranchLink immU10:$target)]>; 748193323Sed 749193323Seddef BL_lu10 : _FLU10< 750193323Sed (outs), 751193323Sed (ins calltarget:$target, variable_ops), 752193323Sed "bl $target", 753193323Sed [(XCoreBranchLink immU20:$target)]>; 754193323Sed} 755193323Sed 756193323Sed// Two operand short 757226633Sdim// TODO eet, eef, tsetmr 758193323Seddef NOT : _F2R<(outs GRRegs:$dst), (ins GRRegs:$b), 759193323Sed "not $dst, $b", 760193323Sed [(set GRRegs:$dst, (not GRRegs:$b))]>; 761193323Sed 762193323Seddef NEG : _F2R<(outs GRRegs:$dst), (ins GRRegs:$b), 763193323Sed "neg $dst, $b", 764193323Sed [(set GRRegs:$dst, (ineg GRRegs:$b))]>; 765193323Sed 766210299Sedlet Constraints = "$src1 = $dst" in { 767193323Seddef SEXT_rus : _FRUS<(outs GRRegs:$dst), (ins GRRegs:$src1, i32imm:$src2), 768226633Sdim "sext $dst, $src2", 769226633Sdim [(set GRRegs:$dst, (int_xcore_sext GRRegs:$src1, 770226633Sdim immBitp:$src2))]>; 771193323Sed 772226633Sdimdef SEXT_2r : _FRUS<(outs GRRegs:$dst), (ins GRRegs:$src1, GRRegs:$src2), 773226633Sdim "sext $dst, $src2", 774226633Sdim [(set GRRegs:$dst, (int_xcore_sext GRRegs:$src1, 775226633Sdim GRRegs:$src2))]>; 776226633Sdim 777193323Seddef ZEXT_rus : _FRUS<(outs GRRegs:$dst), (ins GRRegs:$src1, i32imm:$src2), 778226633Sdim "zext $dst, $src2", 779226633Sdim [(set GRRegs:$dst, (int_xcore_zext GRRegs:$src1, 780226633Sdim immBitp:$src2))]>; 781193323Sed 782226633Sdimdef ZEXT_2r : _FRUS<(outs GRRegs:$dst), (ins GRRegs:$src1, GRRegs:$src2), 783226633Sdim "zext $dst, $src2", 784226633Sdim [(set GRRegs:$dst, (int_xcore_zext GRRegs:$src1, 785226633Sdim GRRegs:$src2))]>; 786226633Sdim 787193323Seddef ANDNOT_2r : _F2R<(outs GRRegs:$dst), (ins GRRegs:$src1, GRRegs:$src2), 788193323Sed "andnot $dst, $src2", 789193323Sed [(set GRRegs:$dst, (and GRRegs:$src1, (not GRRegs:$src2)))]>; 790193323Sed} 791193323Sed 792193323Sedlet isReMaterializable = 1, neverHasSideEffects = 1 in 793193323Seddef MKMSK_rus : _FRUS<(outs GRRegs:$dst), (ins i32imm:$size), 794193323Sed "mkmsk $dst, $size", 795193323Sed []>; 796193323Sed 797193323Seddef MKMSK_2r : _FRUS<(outs GRRegs:$dst), (ins GRRegs:$size), 798193323Sed "mkmsk $dst, $size", 799193323Sed [(set GRRegs:$dst, (add (shl 1, GRRegs:$size), 0xffffffff))]>; 800193323Sed 801218893Sdimdef GETR_rus : _FRUS<(outs GRRegs:$dst), (ins i32imm:$type), 802218893Sdim "getr $dst, $type", 803218893Sdim [(set GRRegs:$dst, (int_xcore_getr immUs:$type))]>; 804218893Sdim 805219077Sdimdef GETTS_2r : _F2R<(outs GRRegs:$dst), (ins GRRegs:$r), 806219077Sdim "getts $dst, res[$r]", 807219077Sdim [(set GRRegs:$dst, (int_xcore_getts GRRegs:$r))]>; 808219077Sdim 809219077Sdimdef SETPT_2r : _F2R<(outs), (ins GRRegs:$r, GRRegs:$val), 810219077Sdim "setpt res[$r], $val", 811219077Sdim [(int_xcore_setpt GRRegs:$r, GRRegs:$val)]>; 812219077Sdim 813218893Sdimdef OUTCT_2r : _F2R<(outs), (ins GRRegs:$r, GRRegs:$val), 814218893Sdim "outct res[$r], $val", 815218893Sdim [(int_xcore_outct GRRegs:$r, GRRegs:$val)]>; 816218893Sdim 817218893Sdimdef OUTCT_rus : _F2R<(outs), (ins GRRegs:$r, i32imm:$val), 818218893Sdim "outct res[$r], $val", 819218893Sdim [(int_xcore_outct GRRegs:$r, immUs:$val)]>; 820218893Sdim 821218893Sdimdef OUTT_2r : _F2R<(outs), (ins GRRegs:$r, GRRegs:$val), 822218893Sdim "outt res[$r], $val", 823218893Sdim [(int_xcore_outt GRRegs:$r, GRRegs:$val)]>; 824218893Sdim 825218893Sdimdef OUT_2r : _F2R<(outs), (ins GRRegs:$r, GRRegs:$val), 826218893Sdim "out res[$r], $val", 827218893Sdim [(int_xcore_out GRRegs:$r, GRRegs:$val)]>; 828218893Sdim 829219077Sdimlet Constraints = "$src = $dst" in 830219077Sdimdef OUTSHR_2r : _F2R<(outs GRRegs:$dst), (ins GRRegs:$r, GRRegs:$src), 831219077Sdim "outshr res[$r], $src", 832226633Sdim [(set GRRegs:$dst, (int_xcore_outshr GRRegs:$r, 833226633Sdim GRRegs:$src))]>; 834219077Sdim 835218893Sdimdef INCT_2r : _F2R<(outs GRRegs:$dst), (ins GRRegs:$r), 836218893Sdim "inct $dst, res[$r]", 837218893Sdim [(set GRRegs:$dst, (int_xcore_inct GRRegs:$r))]>; 838218893Sdim 839218893Sdimdef INT_2r : _F2R<(outs GRRegs:$dst), (ins GRRegs:$r), 840218893Sdim "int $dst, res[$r]", 841218893Sdim [(set GRRegs:$dst, (int_xcore_int GRRegs:$r))]>; 842218893Sdim 843218893Sdimdef IN_2r : _F2R<(outs GRRegs:$dst), (ins GRRegs:$r), 844218893Sdim "in $dst, res[$r]", 845218893Sdim [(set GRRegs:$dst, (int_xcore_in GRRegs:$r))]>; 846218893Sdim 847219077Sdimlet Constraints = "$src = $dst" in 848219077Sdimdef INSHR_2r : _F2R<(outs GRRegs:$dst), (ins GRRegs:$r, GRRegs:$src), 849219077Sdim "inshr $dst, res[$r]", 850226633Sdim [(set GRRegs:$dst, (int_xcore_inshr GRRegs:$r, 851226633Sdim GRRegs:$src))]>; 852219077Sdim 853218893Sdimdef CHKCT_2r : _F2R<(outs), (ins GRRegs:$r, GRRegs:$val), 854218893Sdim "chkct res[$r], $val", 855218893Sdim [(int_xcore_chkct GRRegs:$r, GRRegs:$val)]>; 856218893Sdim 857218893Sdimdef CHKCT_rus : _F2R<(outs), (ins GRRegs:$r, i32imm:$val), 858218893Sdim "chkct res[$r], $val", 859218893Sdim [(int_xcore_chkct GRRegs:$r, immUs:$val)]>; 860218893Sdim 861226633Sdimdef TESTCT_2r : _F2R<(outs GRRegs:$dst), (ins GRRegs:$src), 862226633Sdim "testct $dst, res[$src]", 863226633Sdim [(set GRRegs:$dst, (int_xcore_testct GRRegs:$src))]>; 864226633Sdim 865226633Sdimdef TESTWCT_2r : _F2R<(outs GRRegs:$dst), (ins GRRegs:$src), 866226633Sdim "testwct $dst, res[$src]", 867226633Sdim [(set GRRegs:$dst, (int_xcore_testwct GRRegs:$src))]>; 868226633Sdim 869218893Sdimdef SETD_2r : _F2R<(outs), (ins GRRegs:$r, GRRegs:$val), 870218893Sdim "setd res[$r], $val", 871218893Sdim [(int_xcore_setd GRRegs:$r, GRRegs:$val)]>; 872218893Sdim 873221345Sdimdef GETST_2r : _F2R<(outs GRRegs:$dst), (ins GRRegs:$r), 874221345Sdim "getst $dst, res[$r]", 875221345Sdim [(set GRRegs:$dst, (int_xcore_getst GRRegs:$r))]>; 876221345Sdim 877221345Sdimdef INITSP_2r : _F2R<(outs), (ins GRRegs:$t, GRRegs:$src), 878221345Sdim "init t[$t]:sp, $src", 879221345Sdim [(int_xcore_initsp GRRegs:$t, GRRegs:$src)]>; 880221345Sdim 881221345Sdimdef INITPC_2r : _F2R<(outs), (ins GRRegs:$t, GRRegs:$src), 882221345Sdim "init t[$t]:pc, $src", 883221345Sdim [(int_xcore_initpc GRRegs:$t, GRRegs:$src)]>; 884221345Sdim 885221345Sdimdef INITCP_2r : _F2R<(outs), (ins GRRegs:$t, GRRegs:$src), 886221345Sdim "init t[$t]:cp, $src", 887221345Sdim [(int_xcore_initcp GRRegs:$t, GRRegs:$src)]>; 888221345Sdim 889221345Sdimdef INITDP_2r : _F2R<(outs), (ins GRRegs:$t, GRRegs:$src), 890221345Sdim "init t[$t]:dp, $src", 891221345Sdim [(int_xcore_initdp GRRegs:$t, GRRegs:$src)]>; 892221345Sdim 893193323Sed// Two operand long 894221345Sdim// getd, testlcl 895193323Seddef BITREV_l2r : _FL2R<(outs GRRegs:$dst), (ins GRRegs:$src), 896193323Sed "bitrev $dst, $src", 897193323Sed [(set GRRegs:$dst, (int_xcore_bitrev GRRegs:$src))]>; 898193323Sed 899193323Seddef BYTEREV_l2r : _FL2R<(outs GRRegs:$dst), (ins GRRegs:$src), 900193323Sed "byterev $dst, $src", 901193323Sed [(set GRRegs:$dst, (bswap GRRegs:$src))]>; 902193323Sed 903193323Seddef CLZ_l2r : _FL2R<(outs GRRegs:$dst), (ins GRRegs:$src), 904193323Sed "clz $dst, $src", 905193323Sed [(set GRRegs:$dst, (ctlz GRRegs:$src))]>; 906193323Sed 907219077Sdimdef SETC_l2r : _FL2R<(outs), (ins GRRegs:$r, GRRegs:$val), 908218893Sdim "setc res[$r], $val", 909218893Sdim [(int_xcore_setc GRRegs:$r, GRRegs:$val)]>; 910218893Sdim 911219077Sdimdef SETTW_l2r : _FL2R<(outs), (ins GRRegs:$r, GRRegs:$val), 912219077Sdim "settw res[$r], $val", 913219077Sdim [(int_xcore_settw GRRegs:$r, GRRegs:$val)]>; 914219077Sdim 915221345Sdimdef GETPS_l2r : _FL2R<(outs GRRegs:$dst), (ins GRRegs:$src), 916221345Sdim "get $dst, ps[$src]", 917221345Sdim [(set GRRegs:$dst, (int_xcore_getps GRRegs:$src))]>; 918221345Sdim 919221345Sdimdef SETPS_l2r : _FL2R<(outs), (ins GRRegs:$src1, GRRegs:$src2), 920221345Sdim "set ps[$src1], $src2", 921221345Sdim [(int_xcore_setps GRRegs:$src1, GRRegs:$src2)]>; 922221345Sdim 923221345Sdimdef INITLR_l2r : _FL2R<(outs), (ins GRRegs:$t, GRRegs:$src), 924221345Sdim "init t[$t]:lr, $src", 925221345Sdim [(int_xcore_initlr GRRegs:$t, GRRegs:$src)]>; 926221345Sdim 927221345Sdimdef SETCLK_l2r : _FL2R<(outs), (ins GRRegs:$src1, GRRegs:$src2), 928221345Sdim "setclk res[$src1], $src2", 929221345Sdim [(int_xcore_setclk GRRegs:$src1, GRRegs:$src2)]>; 930221345Sdim 931221345Sdimdef SETRDY_l2r : _FL2R<(outs), (ins GRRegs:$src1, GRRegs:$src2), 932221345Sdim "setrdy res[$src1], $src2", 933221345Sdim [(int_xcore_setrdy GRRegs:$src1, GRRegs:$src2)]>; 934221345Sdim 935221345Sdimdef SETPSC_l2r : _FL2R<(outs), (ins GRRegs:$src1, GRRegs:$src2), 936221345Sdim "setpsc res[$src1], $src2", 937221345Sdim [(int_xcore_setpsc GRRegs:$src1, GRRegs:$src2)]>; 938221345Sdim 939226633Sdimdef PEEK_l2r : _FL2R<(outs GRRegs:$dst), (ins GRRegs:$src), 940226633Sdim "peek $dst, res[$src]", 941226633Sdim [(set GRRegs:$dst, (int_xcore_peek GRRegs:$src))]>; 942226633Sdim 943226633Sdimdef ENDIN_l2r : _FL2R<(outs GRRegs:$dst), (ins GRRegs:$src), 944226633Sdim "endin $dst, res[$src]", 945226633Sdim [(set GRRegs:$dst, (int_xcore_endin GRRegs:$src))]>; 946226633Sdim 947193323Sed// One operand short 948221345Sdim// TODO edu, eeu, waitet, waitef, tstart, clrtp 949219077Sdim// setdp, setcp, setev, kcall 950193323Sed// dgetreg 951221345Sdimdef MSYNC_1r : _F1R<(outs), (ins GRRegs:$i), 952221345Sdim "msync res[$i]", 953221345Sdim [(int_xcore_msync GRRegs:$i)]>; 954221345Sdimdef MJOIN_1r : _F1R<(outs), (ins GRRegs:$i), 955221345Sdim "mjoin res[$i]", 956221345Sdim [(int_xcore_mjoin GRRegs:$i)]>; 957221345Sdim 958204642Srdivackylet isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in 959193323Seddef BAU_1r : _F1R<(outs), (ins GRRegs:$addr), 960193323Sed "bau $addr", 961193323Sed [(brind GRRegs:$addr)]>; 962193323Sed 963204642Srdivackylet isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in 964204642Srdivackydef BR_JT : PseudoInstXCore<(outs), (ins InlineJT:$t, GRRegs:$i), 965204642Srdivacky "bru $i\n$t", 966204642Srdivacky [(XCoreBR_JT tjumptable:$t, GRRegs:$i)]>; 967204642Srdivacky 968204642Srdivackylet isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in 969204642Srdivackydef BR_JT32 : PseudoInstXCore<(outs), (ins InlineJT32:$t, GRRegs:$i), 970204642Srdivacky "bru $i\n$t", 971204642Srdivacky [(XCoreBR_JT32 tjumptable:$t, GRRegs:$i)]>; 972204642Srdivacky 973193323Sedlet Defs=[SP], neverHasSideEffects=1 in 974193323Seddef SETSP_1r : _F1R<(outs), (ins GRRegs:$src), 975193323Sed "set sp, $src", 976193323Sed []>; 977193323Sed 978204642Srdivackylet hasCtrlDep = 1 in 979193323Seddef ECALLT_1r : _F1R<(outs), (ins GRRegs:$src), 980193323Sed "ecallt $src", 981193323Sed []>; 982193323Sed 983204642Srdivackylet hasCtrlDep = 1 in 984193323Seddef ECALLF_1r : _F1R<(outs), (ins GRRegs:$src), 985193323Sed "ecallf $src", 986193323Sed []>; 987193323Sed 988193323Sedlet isCall=1, 989203954Srdivacky// All calls clobber the link register and the non-callee-saved registers: 990226633SdimDefs = [R0, R1, R2, R3, R11, LR], Uses = [SP] in { 991193323Seddef BLA_1r : _F1R<(outs), (ins GRRegs:$addr, variable_ops), 992193323Sed "bla $addr", 993193323Sed [(XCoreBranchLink GRRegs:$addr)]>; 994193323Sed} 995193323Sed 996219077Sdimdef SYNCR_1r : _F1R<(outs), (ins GRRegs:$r), 997219077Sdim "syncr res[$r]", 998219077Sdim [(int_xcore_syncr GRRegs:$r)]>; 999219077Sdim 1000218893Sdimdef FREER_1r : _F1R<(outs), (ins GRRegs:$r), 1001218893Sdim "freer res[$r]", 1002218893Sdim [(int_xcore_freer GRRegs:$r)]>; 1003218893Sdim 1004226633Sdimlet Uses=[R11] in { 1005219077Sdimdef SETV_1r : _F1R<(outs), (ins GRRegs:$r), 1006226633Sdim "setv res[$r], r11", 1007226633Sdim [(int_xcore_setv GRRegs:$r, R11)]>; 1008219077Sdim 1009226633Sdimdef SETEV_1r : _F1R<(outs), (ins GRRegs:$r), 1010226633Sdim "setev res[$r], r11", 1011226633Sdim [(int_xcore_setev GRRegs:$r, R11)]>; 1012226633Sdim} 1013226633Sdim 1014219077Sdimdef EEU_1r : _F1R<(outs), (ins GRRegs:$r), 1015219077Sdim "eeu res[$r]", 1016219077Sdim [(int_xcore_eeu GRRegs:$r)]>; 1017219077Sdim 1018193323Sed// Zero operand short 1019221345Sdim// TODO freet, ldspc, stspc, ldssr, stssr, ldsed, stsed, 1020226633Sdim// stet, getkep, getksp, setkep, getid, kret, dcall, dret, 1021193323Sed// dentsp, drestsp 1022193323Sed 1023219077Sdimdef CLRE_0R : _F0R<(outs), (ins), "clre", [(int_xcore_clre)]>; 1024219077Sdim 1025226633Sdimlet Defs = [R11] in { 1026193323Seddef GETID_0R : _F0R<(outs), (ins), 1027226633Sdim "get r11, id", 1028226633Sdim [(set R11, (int_xcore_getid))]>; 1029193323Sed 1030226633Sdimdef GETED_0R : _F0R<(outs), (ins), 1031226633Sdim "get r11, ed", 1032226633Sdim [(set R11, (int_xcore_geted))]>; 1033226633Sdim 1034226633Sdimdef GETET_0R : _F0R<(outs), (ins), 1035226633Sdim "get r11, et", 1036226633Sdim [(set R11, (int_xcore_getet))]>; 1037226633Sdim} 1038226633Sdim 1039221345Sdimdef SSYNC_0r : _F0R<(outs), (ins), 1040221345Sdim "ssync", 1041221345Sdim [(int_xcore_ssync)]>; 1042221345Sdim 1043219077Sdimlet isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1, 1044219077Sdim hasSideEffects = 1 in 1045219077Sdimdef WAITEU_0R : _F0R<(outs), (ins), 1046219077Sdim "waiteu", 1047219077Sdim [(brind (int_xcore_waitevent))]>; 1048219077Sdim 1049193323Sed//===----------------------------------------------------------------------===// 1050193323Sed// Non-Instruction Patterns 1051193323Sed//===----------------------------------------------------------------------===// 1052193323Sed 1053193323Seddef : Pat<(XCoreBranchLink tglobaladdr:$addr), (BL_lu10 tglobaladdr:$addr)>; 1054193323Seddef : Pat<(XCoreBranchLink texternalsym:$addr), (BL_lu10 texternalsym:$addr)>; 1055193323Sed 1056193323Sed/// sext_inreg 1057193323Seddef : Pat<(sext_inreg GRRegs:$b, i1), (SEXT_rus GRRegs:$b, 1)>; 1058193323Seddef : Pat<(sext_inreg GRRegs:$b, i8), (SEXT_rus GRRegs:$b, 8)>; 1059193323Seddef : Pat<(sext_inreg GRRegs:$b, i16), (SEXT_rus GRRegs:$b, 16)>; 1060193323Sed 1061193323Sed/// loads 1062193323Seddef : Pat<(zextloadi8 (add GRRegs:$addr, GRRegs:$offset)), 1063193323Sed (LD8U_3r GRRegs:$addr, GRRegs:$offset)>; 1064193323Seddef : Pat<(zextloadi8 GRRegs:$addr), (LD8U_3r GRRegs:$addr, (LDC_ru6 0))>; 1065193323Sed 1066198090Srdivackydef : Pat<(sextloadi16 (lda16f GRRegs:$addr, GRRegs:$offset)), 1067193323Sed (LD16S_3r GRRegs:$addr, GRRegs:$offset)>; 1068193323Seddef : Pat<(sextloadi16 GRRegs:$addr), (LD16S_3r GRRegs:$addr, (LDC_ru6 0))>; 1069193323Sed 1070193323Seddef : Pat<(load (ldawf GRRegs:$addr, GRRegs:$offset)), 1071193323Sed (LDW_3r GRRegs:$addr, GRRegs:$offset)>; 1072193323Seddef : Pat<(load (add GRRegs:$addr, immUs4:$offset)), 1073193323Sed (LDW_2rus GRRegs:$addr, (div4_xform immUs4:$offset))>; 1074193323Seddef : Pat<(load GRRegs:$addr), (LDW_2rus GRRegs:$addr, 0)>; 1075193323Sed 1076193323Sed/// anyext 1077193323Seddef : Pat<(extloadi8 (add GRRegs:$addr, GRRegs:$offset)), 1078193323Sed (LD8U_3r GRRegs:$addr, GRRegs:$offset)>; 1079193323Seddef : Pat<(extloadi8 GRRegs:$addr), (LD8U_3r GRRegs:$addr, (LDC_ru6 0))>; 1080193323Seddef : Pat<(extloadi16 (lda16f GRRegs:$addr, GRRegs:$offset)), 1081193323Sed (LD16S_3r GRRegs:$addr, GRRegs:$offset)>; 1082193323Seddef : Pat<(extloadi16 GRRegs:$addr), (LD16S_3r GRRegs:$addr, (LDC_ru6 0))>; 1083193323Sed 1084193323Sed/// stores 1085193323Seddef : Pat<(truncstorei8 GRRegs:$val, (add GRRegs:$addr, GRRegs:$offset)), 1086193323Sed (ST8_l3r GRRegs:$val, GRRegs:$addr, GRRegs:$offset)>; 1087193323Seddef : Pat<(truncstorei8 GRRegs:$val, GRRegs:$addr), 1088193323Sed (ST8_l3r GRRegs:$val, GRRegs:$addr, (LDC_ru6 0))>; 1089193323Sed 1090193323Seddef : Pat<(truncstorei16 GRRegs:$val, (lda16f GRRegs:$addr, GRRegs:$offset)), 1091193323Sed (ST16_l3r GRRegs:$val, GRRegs:$addr, GRRegs:$offset)>; 1092193323Seddef : Pat<(truncstorei16 GRRegs:$val, GRRegs:$addr), 1093193323Sed (ST16_l3r GRRegs:$val, GRRegs:$addr, (LDC_ru6 0))>; 1094193323Sed 1095193323Seddef : Pat<(store GRRegs:$val, (ldawf GRRegs:$addr, GRRegs:$offset)), 1096193323Sed (STW_3r GRRegs:$val, GRRegs:$addr, GRRegs:$offset)>; 1097193323Seddef : Pat<(store GRRegs:$val, (add GRRegs:$addr, immUs4:$offset)), 1098193323Sed (STW_2rus GRRegs:$val, GRRegs:$addr, (div4_xform immUs4:$offset))>; 1099193323Seddef : Pat<(store GRRegs:$val, GRRegs:$addr), 1100193323Sed (STW_2rus GRRegs:$val, GRRegs:$addr, 0)>; 1101193323Sed 1102193323Sed/// cttz 1103193323Seddef : Pat<(cttz GRRegs:$src), (CLZ_l2r (BITREV_l2r GRRegs:$src))>; 1104193323Sed 1105193323Sed/// trap 1106193323Seddef : Pat<(trap), (ECALLF_1r (LDC_ru6 0))>; 1107193323Sed 1108193323Sed/// 1109193323Sed/// branch patterns 1110193323Sed/// 1111193323Sed 1112193323Sed// unconditional branch 1113193323Seddef : Pat<(br bb:$addr), (BRFU_lu6 bb:$addr)>; 1114193323Sed 1115193323Sed// direct match equal/notequal zero brcond 1116193323Seddef : Pat<(brcond (setne GRRegs:$lhs, 0), bb:$dst), 1117193323Sed (BRFT_lru6 GRRegs:$lhs, bb:$dst)>; 1118193323Seddef : Pat<(brcond (seteq GRRegs:$lhs, 0), bb:$dst), 1119193323Sed (BRFF_lru6 GRRegs:$lhs, bb:$dst)>; 1120193323Sed 1121193323Seddef : Pat<(brcond (setle GRRegs:$lhs, GRRegs:$rhs), bb:$dst), 1122193323Sed (BRFF_lru6 (LSS_3r GRRegs:$rhs, GRRegs:$lhs), bb:$dst)>; 1123193323Seddef : Pat<(brcond (setule GRRegs:$lhs, GRRegs:$rhs), bb:$dst), 1124193323Sed (BRFF_lru6 (LSU_3r GRRegs:$rhs, GRRegs:$lhs), bb:$dst)>; 1125193323Seddef : Pat<(brcond (setge GRRegs:$lhs, GRRegs:$rhs), bb:$dst), 1126193323Sed (BRFF_lru6 (LSS_3r GRRegs:$lhs, GRRegs:$rhs), bb:$dst)>; 1127193323Seddef : Pat<(brcond (setuge GRRegs:$lhs, GRRegs:$rhs), bb:$dst), 1128193323Sed (BRFF_lru6 (LSU_3r GRRegs:$lhs, GRRegs:$rhs), bb:$dst)>; 1129193323Seddef : Pat<(brcond (setne GRRegs:$lhs, GRRegs:$rhs), bb:$dst), 1130193323Sed (BRFF_lru6 (EQ_3r GRRegs:$lhs, GRRegs:$rhs), bb:$dst)>; 1131193323Seddef : Pat<(brcond (setne GRRegs:$lhs, immUs:$rhs), bb:$dst), 1132193323Sed (BRFF_lru6 (EQ_2rus GRRegs:$lhs, immUs:$rhs), bb:$dst)>; 1133193323Sed 1134193323Sed// generic brcond pattern 1135193323Seddef : Pat<(brcond GRRegs:$cond, bb:$addr), (BRFT_lru6 GRRegs:$cond, bb:$addr)>; 1136193323Sed 1137193323Sed 1138193323Sed/// 1139193323Sed/// Select patterns 1140193323Sed/// 1141193323Sed 1142193323Sed// direct match equal/notequal zero select 1143193323Seddef : Pat<(select (setne GRRegs:$lhs, 0), GRRegs:$T, GRRegs:$F), 1144193323Sed (SELECT_CC GRRegs:$lhs, GRRegs:$T, GRRegs:$F)>; 1145193323Sed 1146193323Seddef : Pat<(select (seteq GRRegs:$lhs, 0), GRRegs:$T, GRRegs:$F), 1147193323Sed (SELECT_CC GRRegs:$lhs, GRRegs:$F, GRRegs:$T)>; 1148193323Sed 1149193323Seddef : Pat<(select (setle GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F), 1150193323Sed (SELECT_CC (LSS_3r GRRegs:$rhs, GRRegs:$lhs), GRRegs:$F, GRRegs:$T)>; 1151193323Seddef : Pat<(select (setule GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F), 1152193323Sed (SELECT_CC (LSU_3r GRRegs:$rhs, GRRegs:$lhs), GRRegs:$F, GRRegs:$T)>; 1153193323Seddef : Pat<(select (setge GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F), 1154193323Sed (SELECT_CC (LSS_3r GRRegs:$lhs, GRRegs:$rhs), GRRegs:$F, GRRegs:$T)>; 1155193323Seddef : Pat<(select (setuge GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F), 1156193323Sed (SELECT_CC (LSU_3r GRRegs:$lhs, GRRegs:$rhs), GRRegs:$F, GRRegs:$T)>; 1157193323Seddef : Pat<(select (setne GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F), 1158193323Sed (SELECT_CC (EQ_3r GRRegs:$lhs, GRRegs:$rhs), GRRegs:$F, GRRegs:$T)>; 1159193323Seddef : Pat<(select (setne GRRegs:$lhs, immUs:$rhs), GRRegs:$T, GRRegs:$F), 1160193323Sed (SELECT_CC (EQ_2rus GRRegs:$lhs, immUs:$rhs), GRRegs:$F, GRRegs:$T)>; 1161193323Sed 1162193323Sed/// 1163193323Sed/// setcc patterns, only matched when none of the above brcond 1164193323Sed/// patterns match 1165193323Sed/// 1166193323Sed 1167193323Sed// setcc 2 register operands 1168193323Seddef : Pat<(setle GRRegs:$lhs, GRRegs:$rhs), 1169193323Sed (EQ_2rus (LSS_3r GRRegs:$rhs, GRRegs:$lhs), 0)>; 1170193323Seddef : Pat<(setule GRRegs:$lhs, GRRegs:$rhs), 1171193323Sed (EQ_2rus (LSU_3r GRRegs:$rhs, GRRegs:$lhs), 0)>; 1172193323Sed 1173193323Seddef : Pat<(setgt GRRegs:$lhs, GRRegs:$rhs), 1174193323Sed (LSS_3r GRRegs:$rhs, GRRegs:$lhs)>; 1175193323Seddef : Pat<(setugt GRRegs:$lhs, GRRegs:$rhs), 1176193323Sed (LSU_3r GRRegs:$rhs, GRRegs:$lhs)>; 1177193323Sed 1178193323Seddef : Pat<(setge GRRegs:$lhs, GRRegs:$rhs), 1179193323Sed (EQ_2rus (LSS_3r GRRegs:$lhs, GRRegs:$rhs), 0)>; 1180193323Seddef : Pat<(setuge GRRegs:$lhs, GRRegs:$rhs), 1181193323Sed (EQ_2rus (LSU_3r GRRegs:$lhs, GRRegs:$rhs), 0)>; 1182193323Sed 1183193323Seddef : Pat<(setlt GRRegs:$lhs, GRRegs:$rhs), 1184193323Sed (LSS_3r GRRegs:$lhs, GRRegs:$rhs)>; 1185193323Seddef : Pat<(setult GRRegs:$lhs, GRRegs:$rhs), 1186193323Sed (LSU_3r GRRegs:$lhs, GRRegs:$rhs)>; 1187193323Sed 1188193323Seddef : Pat<(setne GRRegs:$lhs, GRRegs:$rhs), 1189193323Sed (EQ_2rus (EQ_3r GRRegs:$lhs, GRRegs:$rhs), 0)>; 1190193323Sed 1191193323Seddef : Pat<(seteq GRRegs:$lhs, GRRegs:$rhs), 1192193323Sed (EQ_3r GRRegs:$lhs, GRRegs:$rhs)>; 1193193323Sed 1194193323Sed// setcc reg/imm operands 1195193323Seddef : Pat<(seteq GRRegs:$lhs, immUs:$rhs), 1196193323Sed (EQ_2rus GRRegs:$lhs, immUs:$rhs)>; 1197193323Seddef : Pat<(setne GRRegs:$lhs, immUs:$rhs), 1198193323Sed (EQ_2rus (EQ_2rus GRRegs:$lhs, immUs:$rhs), 0)>; 1199193323Sed 1200193323Sed// misc 1201193323Seddef : Pat<(add GRRegs:$addr, immUs4:$offset), 1202193323Sed (LDAWF_l2rus GRRegs:$addr, (div4_xform immUs4:$offset))>; 1203193323Sed 1204193323Seddef : Pat<(sub GRRegs:$addr, immUs4:$offset), 1205193323Sed (LDAWB_l2rus GRRegs:$addr, (div4_xform immUs4:$offset))>; 1206193323Sed 1207193323Seddef : Pat<(and GRRegs:$val, immMskBitp:$mask), 1208193323Sed (ZEXT_rus GRRegs:$val, (msksize_xform immMskBitp:$mask))>; 1209193323Sed 1210193323Sed// (sub X, imm) gets canonicalized to (add X, -imm). Match this form. 1211193323Seddef : Pat<(add GRRegs:$src1, immUsNeg:$src2), 1212193323Sed (SUB_2rus GRRegs:$src1, (neg_xform immUsNeg:$src2))>; 1213193323Sed 1214193323Seddef : Pat<(add GRRegs:$src1, immUs4Neg:$src2), 1215193323Sed (LDAWB_l2rus GRRegs:$src1, (div4neg_xform immUs4Neg:$src2))>; 1216193323Sed 1217193323Sed/// 1218193323Sed/// Some peepholes 1219193323Sed/// 1220193323Sed 1221193323Seddef : Pat<(mul GRRegs:$src, 3), 1222193323Sed (LDA16F_l3r GRRegs:$src, GRRegs:$src)>; 1223193323Sed 1224193323Seddef : Pat<(mul GRRegs:$src, 5), 1225193323Sed (LDAWF_l3r GRRegs:$src, GRRegs:$src)>; 1226193323Sed 1227193323Seddef : Pat<(mul GRRegs:$src, -3), 1228193323Sed (LDAWB_l3r GRRegs:$src, GRRegs:$src)>; 1229193323Sed 1230193323Sed// ashr X, 32 is equivalent to ashr X, 31 on the XCore. 1231193323Seddef : Pat<(sra GRRegs:$src, 31), 1232193323Sed (ASHR_l2rus GRRegs:$src, 32)>; 1233193323Sed 1234198090Srdivackydef : Pat<(brcond (setlt GRRegs:$lhs, 0), bb:$dst), 1235198090Srdivacky (BRFT_lru6 (ASHR_l2rus GRRegs:$lhs, 32), bb:$dst)>; 1236198090Srdivacky 1237198090Srdivacky// setge X, 0 is canonicalized to setgt X, -1 1238198090Srdivackydef : Pat<(brcond (setgt GRRegs:$lhs, -1), bb:$dst), 1239198090Srdivacky (BRFF_lru6 (ASHR_l2rus GRRegs:$lhs, 32), bb:$dst)>; 1240198090Srdivacky 1241198090Srdivackydef : Pat<(select (setlt GRRegs:$lhs, 0), GRRegs:$T, GRRegs:$F), 1242198090Srdivacky (SELECT_CC (ASHR_l2rus GRRegs:$lhs, 32), GRRegs:$T, GRRegs:$F)>; 1243198090Srdivacky 1244198090Srdivackydef : Pat<(select (setgt GRRegs:$lhs, -1), GRRegs:$T, GRRegs:$F), 1245198090Srdivacky (SELECT_CC (ASHR_l2rus GRRegs:$lhs, 32), GRRegs:$F, GRRegs:$T)>; 1246198090Srdivacky 1247198090Srdivackydef : Pat<(setgt GRRegs:$lhs, -1), 1248198090Srdivacky (EQ_2rus (ASHR_l2rus GRRegs:$lhs, 32), 0)>; 1249198090Srdivacky 1250198090Srdivackydef : Pat<(sra (shl GRRegs:$src, immBpwSubBitp:$imm), immBpwSubBitp:$imm), 1251198090Srdivacky (SEXT_rus GRRegs:$src, (bpwsub_xform immBpwSubBitp:$imm))>; 1252