XCoreInstrInfo.td revision 221345
1193323Sed//===- XCoreInstrInfo.td - Target Description for XCore ----*- tablegen -*-===// 2193323Sed// 3193323Sed// The LLVM Compiler Infrastructure 4193323Sed// 5193323Sed// This file is distributed under the University of Illinois Open Source 6193323Sed// License. See LICENSE.TXT for details. 7193323Sed// 8193323Sed//===----------------------------------------------------------------------===// 9193323Sed// 10193323Sed// This file describes the XCore instructions in TableGen format. 11193323Sed// 12193323Sed//===----------------------------------------------------------------------===// 13193323Sed 14193323Sed// Uses of CP, DP are not currently reflected in the patterns, since 15193323Sed// having a physical register as an operand prevents loop hoisting and 16193323Sed// since the value of these registers never changes during the life of the 17193323Sed// function. 18193323Sed 19193323Sed//===----------------------------------------------------------------------===// 20193323Sed// Instruction format superclass. 21193323Sed//===----------------------------------------------------------------------===// 22193323Sed 23193323Sedinclude "XCoreInstrFormats.td" 24193323Sed 25193323Sed//===----------------------------------------------------------------------===// 26193323Sed// XCore specific DAG Nodes. 27193323Sed// 28193323Sed 29193323Sed// Call 30193323Seddef SDT_XCoreBranchLink : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>; 31193323Seddef XCoreBranchLink : SDNode<"XCoreISD::BL",SDT_XCoreBranchLink, 32218893Sdim [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 33205407Srdivacky SDNPVariadic]>; 34193323Sed 35206083Srdivackydef XCoreRetsp : SDNode<"XCoreISD::RETSP", SDTBrind, 36218893Sdim [SDNPHasChain, SDNPOptInGlue]>; 37193323Sed 38204642Srdivackydef SDT_XCoreBR_JT : SDTypeProfile<0, 2, 39204642Srdivacky [SDTCisVT<0, i32>, SDTCisVT<1, i32>]>; 40204642Srdivacky 41204642Srdivackydef XCoreBR_JT : SDNode<"XCoreISD::BR_JT", SDT_XCoreBR_JT, 42204642Srdivacky [SDNPHasChain]>; 43204642Srdivacky 44204642Srdivackydef XCoreBR_JT32 : SDNode<"XCoreISD::BR_JT32", SDT_XCoreBR_JT, 45204642Srdivacky [SDNPHasChain]>; 46204642Srdivacky 47193323Seddef SDT_XCoreAddress : SDTypeProfile<1, 1, 48193323Sed [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>; 49193323Sed 50193323Seddef pcrelwrapper : SDNode<"XCoreISD::PCRelativeWrapper", SDT_XCoreAddress, 51193323Sed []>; 52193323Sed 53193323Seddef dprelwrapper : SDNode<"XCoreISD::DPRelativeWrapper", SDT_XCoreAddress, 54193323Sed []>; 55193323Sed 56193323Seddef cprelwrapper : SDNode<"XCoreISD::CPRelativeWrapper", SDT_XCoreAddress, 57193323Sed []>; 58193323Sed 59193323Seddef SDT_XCoreStwsp : SDTypeProfile<0, 2, [SDTCisInt<1>]>; 60193323Seddef XCoreStwsp : SDNode<"XCoreISD::STWSP", SDT_XCoreStwsp, 61193323Sed [SDNPHasChain]>; 62193323Sed 63193323Sed// These are target-independent nodes, but have target-specific formats. 64193323Seddef SDT_XCoreCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>; 65193323Seddef SDT_XCoreCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, 66193323Sed SDTCisVT<1, i32> ]>; 67193323Sed 68193323Seddef callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_XCoreCallSeqStart, 69218893Sdim [SDNPHasChain, SDNPOutGlue]>; 70193323Seddef callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_XCoreCallSeqEnd, 71218893Sdim [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 72193323Sed 73193323Sed//===----------------------------------------------------------------------===// 74193323Sed// Instruction Pattern Stuff 75193323Sed//===----------------------------------------------------------------------===// 76193323Sed 77193323Seddef div4_xform : SDNodeXForm<imm, [{ 78193323Sed // Transformation function: imm/4 79193323Sed assert(N->getZExtValue() % 4 == 0); 80193323Sed return getI32Imm(N->getZExtValue()/4); 81193323Sed}]>; 82193323Sed 83193323Seddef msksize_xform : SDNodeXForm<imm, [{ 84193323Sed // Transformation function: get the size of a mask 85193323Sed assert(isMask_32(N->getZExtValue())); 86193323Sed // look for the first non-zero bit 87193323Sed return getI32Imm(32 - CountLeadingZeros_32(N->getZExtValue())); 88193323Sed}]>; 89193323Sed 90193323Seddef neg_xform : SDNodeXForm<imm, [{ 91193323Sed // Transformation function: -imm 92193323Sed uint32_t value = N->getZExtValue(); 93193323Sed return getI32Imm(-value); 94193323Sed}]>; 95193323Sed 96198090Srdivackydef bpwsub_xform : SDNodeXForm<imm, [{ 97198090Srdivacky // Transformation function: 32-imm 98198090Srdivacky uint32_t value = N->getZExtValue(); 99198090Srdivacky return getI32Imm(32-value); 100198090Srdivacky}]>; 101198090Srdivacky 102193323Seddef div4neg_xform : SDNodeXForm<imm, [{ 103193323Sed // Transformation function: -imm/4 104193323Sed uint32_t value = N->getZExtValue(); 105193323Sed assert(-value % 4 == 0); 106193323Sed return getI32Imm(-value/4); 107193323Sed}]>; 108193323Sed 109193323Seddef immUs4Neg : PatLeaf<(imm), [{ 110193323Sed uint32_t value = (uint32_t)N->getZExtValue(); 111193323Sed return (-value)%4 == 0 && (-value)/4 <= 11; 112193323Sed}]>; 113193323Sed 114193323Seddef immUs4 : PatLeaf<(imm), [{ 115193323Sed uint32_t value = (uint32_t)N->getZExtValue(); 116193323Sed return value%4 == 0 && value/4 <= 11; 117193323Sed}]>; 118193323Sed 119193323Seddef immUsNeg : PatLeaf<(imm), [{ 120193323Sed return -((uint32_t)N->getZExtValue()) <= 11; 121193323Sed}]>; 122193323Sed 123193323Seddef immUs : PatLeaf<(imm), [{ 124193323Sed return (uint32_t)N->getZExtValue() <= 11; 125193323Sed}]>; 126193323Sed 127193323Seddef immU6 : PatLeaf<(imm), [{ 128193323Sed return (uint32_t)N->getZExtValue() < (1 << 6); 129193323Sed}]>; 130193323Sed 131193323Seddef immU10 : PatLeaf<(imm), [{ 132193323Sed return (uint32_t)N->getZExtValue() < (1 << 10); 133193323Sed}]>; 134193323Sed 135193323Seddef immU16 : PatLeaf<(imm), [{ 136193323Sed return (uint32_t)N->getZExtValue() < (1 << 16); 137193323Sed}]>; 138193323Sed 139193323Seddef immU20 : PatLeaf<(imm), [{ 140193323Sed return (uint32_t)N->getZExtValue() < (1 << 20); 141193323Sed}]>; 142193323Sed 143212904Sdimdef immMskBitp : PatLeaf<(imm), [{ return immMskBitp(N); }]>; 144193323Sed 145193323Seddef immBitp : PatLeaf<(imm), [{ 146193323Sed uint32_t value = (uint32_t)N->getZExtValue(); 147193323Sed return (value >= 1 && value <= 8) 148193323Sed || value == 16 149193323Sed || value == 24 150193323Sed || value == 32; 151193323Sed}]>; 152193323Sed 153198090Srdivackydef immBpwSubBitp : PatLeaf<(imm), [{ 154198090Srdivacky uint32_t value = (uint32_t)N->getZExtValue(); 155198090Srdivacky return (value >= 24 && value <= 31) 156198090Srdivacky || value == 16 157198090Srdivacky || value == 8 158198090Srdivacky || value == 0; 159198090Srdivacky}]>; 160198090Srdivacky 161193323Seddef lda16f : PatFrag<(ops node:$addr, node:$offset), 162193323Sed (add node:$addr, (shl node:$offset, 1))>; 163193323Seddef lda16b : PatFrag<(ops node:$addr, node:$offset), 164193323Sed (sub node:$addr, (shl node:$offset, 1))>; 165193323Seddef ldawf : PatFrag<(ops node:$addr, node:$offset), 166193323Sed (add node:$addr, (shl node:$offset, 2))>; 167193323Seddef ldawb : PatFrag<(ops node:$addr, node:$offset), 168193323Sed (sub node:$addr, (shl node:$offset, 2))>; 169193323Sed 170193323Sed// Instruction operand types 171193323Seddef calltarget : Operand<i32>; 172193323Seddef brtarget : Operand<OtherVT>; 173193323Seddef pclabel : Operand<i32>; 174193323Sed 175193323Sed// Addressing modes 176193323Seddef ADDRspii : ComplexPattern<i32, 2, "SelectADDRspii", [add, frameindex], []>; 177193323Seddef ADDRdpii : ComplexPattern<i32, 2, "SelectADDRdpii", [add, dprelwrapper], 178193323Sed []>; 179193323Seddef ADDRcpii : ComplexPattern<i32, 2, "SelectADDRcpii", [add, cprelwrapper], 180193323Sed []>; 181193323Sed 182193323Sed// Address operands 183193323Seddef MEMii : Operand<i32> { 184193323Sed let PrintMethod = "printMemOperand"; 185193323Sed let MIOperandInfo = (ops i32imm, i32imm); 186193323Sed} 187193323Sed 188204642Srdivacky// Jump tables. 189204642Srdivackydef InlineJT : Operand<i32> { 190204642Srdivacky let PrintMethod = "printInlineJT"; 191204642Srdivacky} 192204642Srdivacky 193204642Srdivackydef InlineJT32 : Operand<i32> { 194204642Srdivacky let PrintMethod = "printInlineJT32"; 195204642Srdivacky} 196204642Srdivacky 197193323Sed//===----------------------------------------------------------------------===// 198193323Sed// Instruction Class Templates 199193323Sed//===----------------------------------------------------------------------===// 200193323Sed 201193323Sed// Three operand short 202193323Sed 203193323Sedmulticlass F3R_2RUS<string OpcStr, SDNode OpNode> { 204193323Sed def _3r: _F3R< 205193323Sed (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), 206193323Sed !strconcat(OpcStr, " $dst, $b, $c"), 207193323Sed [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>; 208193323Sed def _2rus : _F2RUS< 209193323Sed (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c), 210193323Sed !strconcat(OpcStr, " $dst, $b, $c"), 211193323Sed [(set GRRegs:$dst, (OpNode GRRegs:$b, immUs:$c))]>; 212193323Sed} 213193323Sed 214193323Sedmulticlass F3R_2RUS_np<string OpcStr> { 215193323Sed def _3r: _F3R< 216193323Sed (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), 217193323Sed !strconcat(OpcStr, " $dst, $b, $c"), 218193323Sed []>; 219193323Sed def _2rus : _F2RUS< 220193323Sed (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c), 221193323Sed !strconcat(OpcStr, " $dst, $b, $c"), 222193323Sed []>; 223193323Sed} 224193323Sed 225193323Sedmulticlass F3R_2RBITP<string OpcStr, SDNode OpNode> { 226193323Sed def _3r: _F3R< 227193323Sed (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), 228193323Sed !strconcat(OpcStr, " $dst, $b, $c"), 229193323Sed [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>; 230193323Sed def _2rus : _F2RUS< 231193323Sed (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c), 232193323Sed !strconcat(OpcStr, " $dst, $b, $c"), 233193323Sed [(set GRRegs:$dst, (OpNode GRRegs:$b, immBitp:$c))]>; 234193323Sed} 235193323Sed 236193323Sedclass F3R<string OpcStr, SDNode OpNode> : _F3R< 237193323Sed (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), 238193323Sed !strconcat(OpcStr, " $dst, $b, $c"), 239193323Sed [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>; 240193323Sed 241193323Sedclass F3R_np<string OpcStr> : _F3R< 242193323Sed (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), 243193323Sed !strconcat(OpcStr, " $dst, $b, $c"), 244193323Sed []>; 245193323Sed// Three operand long 246193323Sed 247193323Sed/// FL3R_L2RUS multiclass - Define a normal FL3R/FL2RUS pattern in one shot. 248193323Sedmulticlass FL3R_L2RUS<string OpcStr, SDNode OpNode> { 249193323Sed def _l3r: _FL3R< 250193323Sed (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), 251193323Sed !strconcat(OpcStr, " $dst, $b, $c"), 252193323Sed [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>; 253193323Sed def _l2rus : _FL2RUS< 254193323Sed (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c), 255193323Sed !strconcat(OpcStr, " $dst, $b, $c"), 256193323Sed [(set GRRegs:$dst, (OpNode GRRegs:$b, immUs:$c))]>; 257193323Sed} 258193323Sed 259193323Sed/// FL3R_L2RUS multiclass - Define a normal FL3R/FL2RUS pattern in one shot. 260193323Sedmulticlass FL3R_L2RBITP<string OpcStr, SDNode OpNode> { 261193323Sed def _l3r: _FL3R< 262193323Sed (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), 263193323Sed !strconcat(OpcStr, " $dst, $b, $c"), 264193323Sed [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>; 265193323Sed def _l2rus : _FL2RUS< 266193323Sed (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c), 267193323Sed !strconcat(OpcStr, " $dst, $b, $c"), 268193323Sed [(set GRRegs:$dst, (OpNode GRRegs:$b, immBitp:$c))]>; 269193323Sed} 270193323Sed 271193323Sedclass FL3R<string OpcStr, SDNode OpNode> : _FL3R< 272193323Sed (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), 273193323Sed !strconcat(OpcStr, " $dst, $b, $c"), 274193323Sed [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>; 275193323Sed 276193323Sed// Register - U6 277193323Sed// Operand register - U6 278193323Sedmulticlass FRU6_LRU6_branch<string OpcStr> { 279193323Sed def _ru6: _FRU6< 280193323Sed (outs), (ins GRRegs:$cond, brtarget:$dest), 281193323Sed !strconcat(OpcStr, " $cond, $dest"), 282193323Sed []>; 283193323Sed def _lru6: _FLRU6< 284193323Sed (outs), (ins GRRegs:$cond, brtarget:$dest), 285193323Sed !strconcat(OpcStr, " $cond, $dest"), 286193323Sed []>; 287193323Sed} 288193323Sed 289193323Sedmulticlass FRU6_LRU6_cp<string OpcStr> { 290193323Sed def _ru6: _FRU6< 291193323Sed (outs GRRegs:$dst), (ins i32imm:$a), 292193323Sed !strconcat(OpcStr, " $dst, cp[$a]"), 293193323Sed []>; 294193323Sed def _lru6: _FLRU6< 295193323Sed (outs GRRegs:$dst), (ins i32imm:$a), 296193323Sed !strconcat(OpcStr, " $dst, cp[$a]"), 297193323Sed []>; 298193323Sed} 299193323Sed 300193323Sed// U6 301193323Sedmulticlass FU6_LU6<string OpcStr, SDNode OpNode> { 302193323Sed def _u6: _FU6< 303193323Sed (outs), (ins i32imm:$b), 304193323Sed !strconcat(OpcStr, " $b"), 305193323Sed [(OpNode immU6:$b)]>; 306193323Sed def _lu6: _FLU6< 307193323Sed (outs), (ins i32imm:$b), 308193323Sed !strconcat(OpcStr, " $b"), 309193323Sed [(OpNode immU16:$b)]>; 310193323Sed} 311221345Sdimmulticlass FU6_LU6_int<string OpcStr, Intrinsic Int> { 312221345Sdim def _u6: _FU6< 313221345Sdim (outs), (ins i32imm:$b), 314221345Sdim !strconcat(OpcStr, " $b"), 315221345Sdim [(Int immU6:$b)]>; 316221345Sdim def _lu6: _FLU6< 317221345Sdim (outs), (ins i32imm:$b), 318221345Sdim !strconcat(OpcStr, " $b"), 319221345Sdim [(Int immU16:$b)]>; 320221345Sdim} 321193323Sed 322193323Sedmulticlass FU6_LU6_np<string OpcStr> { 323193323Sed def _u6: _FU6< 324193323Sed (outs), (ins i32imm:$b), 325193323Sed !strconcat(OpcStr, " $b"), 326193323Sed []>; 327193323Sed def _lu6: _FLU6< 328193323Sed (outs), (ins i32imm:$b), 329193323Sed !strconcat(OpcStr, " $b"), 330193323Sed []>; 331193323Sed} 332193323Sed 333193323Sed// U10 334193323Sedmulticlass FU10_LU10_np<string OpcStr> { 335193323Sed def _u10: _FU10< 336193323Sed (outs), (ins i32imm:$b), 337193323Sed !strconcat(OpcStr, " $b"), 338193323Sed []>; 339193323Sed def _lu10: _FLU10< 340193323Sed (outs), (ins i32imm:$b), 341193323Sed !strconcat(OpcStr, " $b"), 342193323Sed []>; 343193323Sed} 344193323Sed 345193323Sed// Two operand short 346193323Sed 347193323Sedclass F2R_np<string OpcStr> : _F2R< 348193323Sed (outs GRRegs:$dst), (ins GRRegs:$b), 349193323Sed !strconcat(OpcStr, " $dst, $b"), 350193323Sed []>; 351193323Sed 352193323Sed// Two operand long 353193323Sed 354193323Sed//===----------------------------------------------------------------------===// 355193323Sed// Pseudo Instructions 356193323Sed//===----------------------------------------------------------------------===// 357193323Sed 358193323Sedlet Defs = [SP], Uses = [SP] in { 359193323Seddef ADJCALLSTACKDOWN : PseudoInstXCore<(outs), (ins i32imm:$amt), 360193323Sed "${:comment} ADJCALLSTACKDOWN $amt", 361193323Sed [(callseq_start timm:$amt)]>; 362193323Seddef ADJCALLSTACKUP : PseudoInstXCore<(outs), (ins i32imm:$amt1, i32imm:$amt2), 363193323Sed "${:comment} ADJCALLSTACKUP $amt1", 364193323Sed [(callseq_end timm:$amt1, timm:$amt2)]>; 365193323Sed} 366193323Sed 367193323Seddef LDWFI : PseudoInstXCore<(outs GRRegs:$dst), (ins MEMii:$addr), 368193323Sed "${:comment} LDWFI $dst, $addr", 369193323Sed [(set GRRegs:$dst, (load ADDRspii:$addr))]>; 370193323Sed 371193323Seddef LDAWFI : PseudoInstXCore<(outs GRRegs:$dst), (ins MEMii:$addr), 372193323Sed "${:comment} LDAWFI $dst, $addr", 373193323Sed [(set GRRegs:$dst, ADDRspii:$addr)]>; 374193323Sed 375193323Seddef STWFI : PseudoInstXCore<(outs), (ins GRRegs:$src, MEMii:$addr), 376193323Sed "${:comment} STWFI $src, $addr", 377193323Sed [(store GRRegs:$src, ADDRspii:$addr)]>; 378193323Sed 379198892Srdivacky// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after 380198892Srdivacky// instruction selection into a branch sequence. 381198892Srdivackylet usesCustomInserter = 1 in { 382193323Sed def SELECT_CC : PseudoInstXCore<(outs GRRegs:$dst), 383193323Sed (ins GRRegs:$cond, GRRegs:$T, GRRegs:$F), 384193323Sed "${:comment} SELECT_CC PSEUDO!", 385193323Sed [(set GRRegs:$dst, 386193323Sed (select GRRegs:$cond, GRRegs:$T, GRRegs:$F))]>; 387193323Sed} 388193323Sed 389193323Sed//===----------------------------------------------------------------------===// 390193323Sed// Instructions 391193323Sed//===----------------------------------------------------------------------===// 392193323Sed 393193323Sed// Three operand short 394193323Seddefm ADD : F3R_2RUS<"add", add>; 395193323Seddefm SUB : F3R_2RUS<"sub", sub>; 396193323Sedlet neverHasSideEffects = 1 in { 397193323Seddefm EQ : F3R_2RUS_np<"eq">; 398193323Seddef LSS_3r : F3R_np<"lss">; 399193323Seddef LSU_3r : F3R_np<"lsu">; 400193323Sed} 401193323Seddef AND_3r : F3R<"and", and>; 402193323Seddef OR_3r : F3R<"or", or>; 403193323Sed 404193323Sedlet mayLoad=1 in { 405193323Seddef LDW_3r : _F3R<(outs GRRegs:$dst), (ins GRRegs:$addr, GRRegs:$offset), 406193323Sed "ldw $dst, $addr[$offset]", 407193323Sed []>; 408193323Sed 409193323Seddef LDW_2rus : _F2RUS<(outs GRRegs:$dst), (ins GRRegs:$addr, i32imm:$offset), 410193323Sed "ldw $dst, $addr[$offset]", 411193323Sed []>; 412193323Sed 413193323Seddef LD16S_3r : _F3R<(outs GRRegs:$dst), (ins GRRegs:$addr, GRRegs:$offset), 414193323Sed "ld16s $dst, $addr[$offset]", 415193323Sed []>; 416193323Sed 417193323Seddef LD8U_3r : _F3R<(outs GRRegs:$dst), (ins GRRegs:$addr, GRRegs:$offset), 418193323Sed "ld8u $dst, $addr[$offset]", 419193323Sed []>; 420193323Sed} 421193323Sed 422193323Sedlet mayStore=1 in { 423193323Seddef STW_3r : _F3R<(outs), (ins GRRegs:$val, GRRegs:$addr, GRRegs:$offset), 424193323Sed "stw $val, $addr[$offset]", 425193323Sed []>; 426193323Sed 427193323Seddef STW_2rus : _F2RUS<(outs), (ins GRRegs:$val, GRRegs:$addr, i32imm:$offset), 428193323Sed "stw $val, $addr[$offset]", 429193323Sed []>; 430193323Sed} 431193323Sed 432193323Seddefm SHL : F3R_2RBITP<"shl", shl>; 433193323Seddefm SHR : F3R_2RBITP<"shr", srl>; 434193323Sed// TODO tsetr 435193323Sed 436193323Sed// Three operand long 437193323Seddef LDAWF_l3r : _FL3R<(outs GRRegs:$dst), (ins GRRegs:$addr, GRRegs:$offset), 438193323Sed "ldaw $dst, $addr[$offset]", 439193323Sed [(set GRRegs:$dst, (ldawf GRRegs:$addr, GRRegs:$offset))]>; 440193323Sed 441193323Sedlet neverHasSideEffects = 1 in 442193323Seddef LDAWF_l2rus : _FL2RUS<(outs GRRegs:$dst), 443193323Sed (ins GRRegs:$addr, i32imm:$offset), 444193323Sed "ldaw $dst, $addr[$offset]", 445193323Sed []>; 446193323Sed 447193323Seddef LDAWB_l3r : _FL3R<(outs GRRegs:$dst), (ins GRRegs:$addr, GRRegs:$offset), 448193323Sed "ldaw $dst, $addr[-$offset]", 449193323Sed [(set GRRegs:$dst, (ldawb GRRegs:$addr, GRRegs:$offset))]>; 450193323Sed 451193323Sedlet neverHasSideEffects = 1 in 452193323Seddef LDAWB_l2rus : _FL2RUS<(outs GRRegs:$dst), 453193323Sed (ins GRRegs:$addr, i32imm:$offset), 454193323Sed "ldaw $dst, $addr[-$offset]", 455193323Sed []>; 456193323Sed 457193323Seddef LDA16F_l3r : _FL3R<(outs GRRegs:$dst), (ins GRRegs:$addr, GRRegs:$offset), 458193323Sed "lda16 $dst, $addr[$offset]", 459193323Sed [(set GRRegs:$dst, (lda16f GRRegs:$addr, GRRegs:$offset))]>; 460193323Sed 461193323Seddef LDA16B_l3r : _FL3R<(outs GRRegs:$dst), (ins GRRegs:$addr, GRRegs:$offset), 462193323Sed "lda16 $dst, $addr[-$offset]", 463193323Sed [(set GRRegs:$dst, (lda16b GRRegs:$addr, GRRegs:$offset))]>; 464193323Sed 465193323Seddef MUL_l3r : FL3R<"mul", mul>; 466193323Sed// Instructions which may trap are marked as side effecting. 467193323Sedlet hasSideEffects = 1 in { 468193323Seddef DIVS_l3r : FL3R<"divs", sdiv>; 469193323Seddef DIVU_l3r : FL3R<"divu", udiv>; 470193323Seddef REMS_l3r : FL3R<"rems", srem>; 471193323Seddef REMU_l3r : FL3R<"remu", urem>; 472193323Sed} 473193323Seddef XOR_l3r : FL3R<"xor", xor>; 474193323Seddefm ASHR : FL3R_L2RBITP<"ashr", sra>; 475193323Sed// TODO crc32, crc8, inpw, outpw 476193323Sedlet mayStore=1 in { 477193323Seddef ST16_l3r : _FL3R<(outs), (ins GRRegs:$val, GRRegs:$addr, GRRegs:$offset), 478193323Sed "st16 $val, $addr[$offset]", 479193323Sed []>; 480193323Sed 481193323Seddef ST8_l3r : _FL3R<(outs), (ins GRRegs:$val, GRRegs:$addr, GRRegs:$offset), 482193323Sed "st8 $val, $addr[$offset]", 483193323Sed []>; 484193323Sed} 485193323Sed 486193323Sed// Four operand long 487198090Srdivackylet Constraints = "$src1 = $dst1,$src2 = $dst2" in { 488193323Seddef MACCU_l4r : _L4R<(outs GRRegs:$dst1, GRRegs:$dst2), 489193323Sed (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3, 490193323Sed GRRegs:$src4), 491193323Sed "maccu $dst1, $dst2, $src3, $src4", 492193323Sed []>; 493193323Sed 494193323Seddef MACCS_l4r : _L4R<(outs GRRegs:$dst1, GRRegs:$dst2), 495193323Sed (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3, 496193323Sed GRRegs:$src4), 497193323Sed "maccs $dst1, $dst2, $src3, $src4", 498193323Sed []>; 499193323Sed} 500193323Sed 501193323Sed// Five operand long 502193323Sed 503193323Seddef LADD_l5r : _L5R<(outs GRRegs:$dst1, GRRegs:$dst2), 504193323Sed (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3), 505193323Sed "ladd $dst1, $dst2, $src1, $src2, $src3", 506193323Sed []>; 507193323Sed 508193323Seddef LSUB_l5r : _L5R<(outs GRRegs:$dst1, GRRegs:$dst2), 509193323Sed (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3), 510193323Sed "lsub $dst1, $dst2, $src1, $src2, $src3", 511193323Sed []>; 512193323Sed 513193323Seddef LDIV_l5r : _L5R<(outs GRRegs:$dst1, GRRegs:$dst2), 514193323Sed (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3), 515193323Sed "ldiv $dst1, $dst2, $src1, $src2, $src3", 516193323Sed []>; 517193323Sed 518193323Sed// Six operand long 519193323Sed 520193323Seddef LMUL_l6r : _L6R<(outs GRRegs:$dst1, GRRegs:$dst2), 521193323Sed (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3, 522193323Sed GRRegs:$src4), 523193323Sed "lmul $dst1, $dst2, $src1, $src2, $src3, $src4", 524193323Sed []>; 525193323Sed 526193323Sed// Register - U6 527193323Sed 528193323Sed//let Uses = [DP] in ... 529193323Sedlet neverHasSideEffects = 1, isReMaterializable = 1 in 530193323Seddef LDAWDP_ru6: _FRU6<(outs GRRegs:$dst), (ins MEMii:$a), 531193323Sed "ldaw $dst, dp[$a]", 532193323Sed []>; 533193323Sed 534193323Sedlet isReMaterializable = 1 in 535193323Seddef LDAWDP_lru6: _FLRU6< 536193323Sed (outs GRRegs:$dst), (ins MEMii:$a), 537193323Sed "ldaw $dst, dp[$a]", 538193323Sed [(set GRRegs:$dst, ADDRdpii:$a)]>; 539193323Sed 540193323Sedlet mayLoad=1 in 541193323Seddef LDWDP_ru6: _FRU6<(outs GRRegs:$dst), (ins MEMii:$a), 542193323Sed "ldw $dst, dp[$a]", 543193323Sed []>; 544193323Sed 545193323Seddef LDWDP_lru6: _FLRU6< 546193323Sed (outs GRRegs:$dst), (ins MEMii:$a), 547193323Sed "ldw $dst, dp[$a]", 548193323Sed [(set GRRegs:$dst, (load ADDRdpii:$a))]>; 549193323Sed 550193323Sedlet mayStore=1 in 551193323Seddef STWDP_ru6 : _FRU6<(outs), (ins GRRegs:$val, MEMii:$addr), 552193323Sed "stw $val, dp[$addr]", 553193323Sed []>; 554193323Sed 555193323Seddef STWDP_lru6 : _FLRU6<(outs), (ins GRRegs:$val, MEMii:$addr), 556193323Sed "stw $val, dp[$addr]", 557193323Sed [(store GRRegs:$val, ADDRdpii:$addr)]>; 558193323Sed 559193323Sed//let Uses = [CP] in .. 560193323Sedlet mayLoad = 1, isReMaterializable = 1 in 561193323Seddefm LDWCP : FRU6_LRU6_cp<"ldw">; 562193323Sed 563193323Sedlet Uses = [SP] in { 564193323Sedlet mayStore=1 in { 565193323Seddef STWSP_ru6 : _FRU6< 566193323Sed (outs), (ins GRRegs:$val, i32imm:$index), 567193323Sed "stw $val, sp[$index]", 568193323Sed [(XCoreStwsp GRRegs:$val, immU6:$index)]>; 569193323Sed 570193323Seddef STWSP_lru6 : _FLRU6< 571193323Sed (outs), (ins GRRegs:$val, i32imm:$index), 572193323Sed "stw $val, sp[$index]", 573193323Sed [(XCoreStwsp GRRegs:$val, immU16:$index)]>; 574193323Sed} 575193323Sed 576193323Sedlet mayLoad=1 in { 577193323Seddef LDWSP_ru6 : _FRU6< 578193323Sed (outs GRRegs:$dst), (ins i32imm:$b), 579193323Sed "ldw $dst, sp[$b]", 580193323Sed []>; 581193323Sed 582193323Seddef LDWSP_lru6 : _FLRU6< 583193323Sed (outs GRRegs:$dst), (ins i32imm:$b), 584193323Sed "ldw $dst, sp[$b]", 585193323Sed []>; 586193323Sed} 587193323Sed 588193323Sedlet neverHasSideEffects = 1 in { 589193323Seddef LDAWSP_ru6 : _FRU6< 590193323Sed (outs GRRegs:$dst), (ins i32imm:$b), 591193323Sed "ldaw $dst, sp[$b]", 592193323Sed []>; 593193323Sed 594193323Seddef LDAWSP_lru6 : _FLRU6< 595193323Sed (outs GRRegs:$dst), (ins i32imm:$b), 596193323Sed "ldaw $dst, sp[$b]", 597193323Sed []>; 598193323Sed 599193323Seddef LDAWSP_ru6_RRegs : _FRU6< 600193323Sed (outs RRegs:$dst), (ins i32imm:$b), 601193323Sed "ldaw $dst, sp[$b]", 602193323Sed []>; 603193323Sed 604193323Seddef LDAWSP_lru6_RRegs : _FLRU6< 605193323Sed (outs RRegs:$dst), (ins i32imm:$b), 606193323Sed "ldaw $dst, sp[$b]", 607193323Sed []>; 608193323Sed} 609193323Sed} 610193323Sed 611193323Sedlet isReMaterializable = 1 in { 612193323Seddef LDC_ru6 : _FRU6< 613193323Sed (outs GRRegs:$dst), (ins i32imm:$b), 614193323Sed "ldc $dst, $b", 615193323Sed [(set GRRegs:$dst, immU6:$b)]>; 616193323Sed 617193323Seddef LDC_lru6 : _FLRU6< 618193323Sed (outs GRRegs:$dst), (ins i32imm:$b), 619193323Sed "ldc $dst, $b", 620193323Sed [(set GRRegs:$dst, immU16:$b)]>; 621193323Sed} 622193323Sed 623218893Sdimdef SETC_ru6 : _FRU6<(outs), (ins GRRegs:$r, i32imm:$val), 624218893Sdim "setc res[$r], $val", 625218893Sdim [(int_xcore_setc GRRegs:$r, immU6:$val)]>; 626218893Sdim 627218893Sdimdef SETC_lru6 : _FLRU6<(outs), (ins GRRegs:$r, i32imm:$val), 628218893Sdim "setc res[$r], $val", 629218893Sdim [(int_xcore_setc GRRegs:$r, immU16:$val)]>; 630218893Sdim 631193323Sed// Operand register - U6 632193323Sedlet isBranch = 1, isTerminator = 1 in { 633193323Seddefm BRFT: FRU6_LRU6_branch<"bt">; 634193323Seddefm BRBT: FRU6_LRU6_branch<"bt">; 635193323Seddefm BRFF: FRU6_LRU6_branch<"bf">; 636193323Seddefm BRBF: FRU6_LRU6_branch<"bf">; 637193323Sed} 638193323Sed 639193323Sed// U6 640193323Sedlet Defs = [SP], Uses = [SP] in { 641193323Sedlet neverHasSideEffects = 1 in 642193323Seddefm EXTSP : FU6_LU6_np<"extsp">; 643193323Sedlet mayStore = 1 in 644193323Seddefm ENTSP : FU6_LU6_np<"entsp">; 645193323Sed 646199481Srdivackylet isReturn = 1, isTerminator = 1, mayLoad = 1, isBarrier = 1 in { 647193323Seddefm RETSP : FU6_LU6<"retsp", XCoreRetsp>; 648193323Sed} 649193323Sed} 650193323Sed 651221345Sdim// TODO extdp, kentsp, krestsp, blat 652221345Sdim// getsr, kalli 653204642Srdivackylet isBranch = 1, isTerminator = 1, isBarrier = 1 in { 654193323Seddef BRBU_u6 : _FU6< 655193323Sed (outs), 656193323Sed (ins brtarget:$target), 657193323Sed "bu $target", 658193323Sed []>; 659193323Sed 660193323Seddef BRBU_lu6 : _FLU6< 661193323Sed (outs), 662193323Sed (ins brtarget:$target), 663193323Sed "bu $target", 664193323Sed []>; 665193323Sed 666193323Seddef BRFU_u6 : _FU6< 667193323Sed (outs), 668193323Sed (ins brtarget:$target), 669193323Sed "bu $target", 670193323Sed []>; 671193323Sed 672193323Seddef BRFU_lu6 : _FLU6< 673193323Sed (outs), 674193323Sed (ins brtarget:$target), 675193323Sed "bu $target", 676193323Sed []>; 677193323Sed} 678193323Sed 679193323Sed//let Uses = [CP] in ... 680198090Srdivackylet Defs = [R11], neverHasSideEffects = 1, isReMaterializable = 1 in 681193323Seddef LDAWCP_u6: _FRU6<(outs), (ins MEMii:$a), 682193323Sed "ldaw r11, cp[$a]", 683193323Sed []>; 684193323Sed 685198090Srdivackylet Defs = [R11], isReMaterializable = 1 in 686193323Seddef LDAWCP_lu6: _FLRU6< 687193323Sed (outs), (ins MEMii:$a), 688193323Sed "ldaw r11, cp[$a]", 689193323Sed [(set R11, ADDRcpii:$a)]>; 690193323Sed 691221345Sdimdefm SETSR : FU6_LU6_int<"setsr", int_xcore_setsr>; 692221345Sdim 693221345Sdimdefm CLRSR : FU6_LU6_int<"clrsr", int_xcore_clrsr>; 694221345Sdim 695221345Sdim// setsr may cause a branch if it is used to enable events. clrsr may 696221345Sdim// branch if it is executed while events are enabled. 697221345Sdimlet isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in { 698221345Sdimdefm SETSR_branch : FU6_LU6_np<"setsr">; 699221345Sdimdefm CLRSR_branch : FU6_LU6_np<"clrsr">; 700221345Sdim} 701221345Sdim 702193323Sed// U10 703193323Sed// TODO ldwcpl, blacp 704193323Sed 705193323Sedlet Defs = [R11], isReMaterializable = 1, neverHasSideEffects = 1 in 706193323Seddef LDAP_u10 : _FU10< 707193323Sed (outs), 708193323Sed (ins i32imm:$addr), 709193323Sed "ldap r11, $addr", 710193323Sed []>; 711193323Sed 712193323Sedlet Defs = [R11], isReMaterializable = 1 in 713193323Seddef LDAP_lu10 : _FLU10< 714193323Sed (outs), 715193323Sed (ins i32imm:$addr), 716193323Sed "ldap r11, $addr", 717193323Sed [(set R11, (pcrelwrapper tglobaladdr:$addr))]>; 718193323Sed 719199511Srdivackylet Defs = [R11], isReMaterializable = 1 in 720199511Srdivackydef LDAP_lu10_ba : _FLU10<(outs), 721199511Srdivacky (ins i32imm:$addr), 722199511Srdivacky "ldap r11, $addr", 723199511Srdivacky [(set R11, (pcrelwrapper tblockaddress:$addr))]>; 724199511Srdivacky 725193323Sedlet isCall=1, 726203954Srdivacky// All calls clobber the link register and the non-callee-saved registers: 727193323SedDefs = [R0, R1, R2, R3, R11, LR] in { 728193323Seddef BL_u10 : _FU10< 729193323Sed (outs), 730193323Sed (ins calltarget:$target, variable_ops), 731193323Sed "bl $target", 732193323Sed [(XCoreBranchLink immU10:$target)]>; 733193323Sed 734193323Seddef BL_lu10 : _FLU10< 735193323Sed (outs), 736193323Sed (ins calltarget:$target, variable_ops), 737193323Sed "bl $target", 738193323Sed [(XCoreBranchLink immU20:$target)]>; 739193323Sed} 740193323Sed 741193323Sed// Two operand short 742221345Sdim// TODO eet, eef, testwct, tsetmr, sext (reg), zext (reg) 743193323Seddef NOT : _F2R<(outs GRRegs:$dst), (ins GRRegs:$b), 744193323Sed "not $dst, $b", 745193323Sed [(set GRRegs:$dst, (not GRRegs:$b))]>; 746193323Sed 747193323Seddef NEG : _F2R<(outs GRRegs:$dst), (ins GRRegs:$b), 748193323Sed "neg $dst, $b", 749193323Sed [(set GRRegs:$dst, (ineg GRRegs:$b))]>; 750193323Sed 751210299Sedlet Constraints = "$src1 = $dst" in { 752193323Sedlet neverHasSideEffects = 1 in 753193323Seddef SEXT_rus : _FRUS<(outs GRRegs:$dst), (ins GRRegs:$src1, i32imm:$src2), 754193323Sed "sext $dst, $src2", 755193323Sed []>; 756193323Sed 757193323Sedlet neverHasSideEffects = 1 in 758193323Seddef ZEXT_rus : _FRUS<(outs GRRegs:$dst), (ins GRRegs:$src1, i32imm:$src2), 759193323Sed "zext $dst, $src2", 760193323Sed []>; 761193323Sed 762193323Seddef ANDNOT_2r : _F2R<(outs GRRegs:$dst), (ins GRRegs:$src1, GRRegs:$src2), 763193323Sed "andnot $dst, $src2", 764193323Sed [(set GRRegs:$dst, (and GRRegs:$src1, (not GRRegs:$src2)))]>; 765193323Sed} 766193323Sed 767193323Sedlet isReMaterializable = 1, neverHasSideEffects = 1 in 768193323Seddef MKMSK_rus : _FRUS<(outs GRRegs:$dst), (ins i32imm:$size), 769193323Sed "mkmsk $dst, $size", 770193323Sed []>; 771193323Sed 772193323Seddef MKMSK_2r : _FRUS<(outs GRRegs:$dst), (ins GRRegs:$size), 773193323Sed "mkmsk $dst, $size", 774193323Sed [(set GRRegs:$dst, (add (shl 1, GRRegs:$size), 0xffffffff))]>; 775193323Sed 776218893Sdimdef GETR_rus : _FRUS<(outs GRRegs:$dst), (ins i32imm:$type), 777218893Sdim "getr $dst, $type", 778218893Sdim [(set GRRegs:$dst, (int_xcore_getr immUs:$type))]>; 779218893Sdim 780219077Sdimdef GETTS_2r : _F2R<(outs GRRegs:$dst), (ins GRRegs:$r), 781219077Sdim "getts $dst, res[$r]", 782219077Sdim [(set GRRegs:$dst, (int_xcore_getts GRRegs:$r))]>; 783219077Sdim 784219077Sdimdef SETPT_2r : _F2R<(outs), (ins GRRegs:$r, GRRegs:$val), 785219077Sdim "setpt res[$r], $val", 786219077Sdim [(int_xcore_setpt GRRegs:$r, GRRegs:$val)]>; 787219077Sdim 788218893Sdimdef OUTCT_2r : _F2R<(outs), (ins GRRegs:$r, GRRegs:$val), 789218893Sdim "outct res[$r], $val", 790218893Sdim [(int_xcore_outct GRRegs:$r, GRRegs:$val)]>; 791218893Sdim 792218893Sdimdef OUTCT_rus : _F2R<(outs), (ins GRRegs:$r, i32imm:$val), 793218893Sdim "outct res[$r], $val", 794218893Sdim [(int_xcore_outct GRRegs:$r, immUs:$val)]>; 795218893Sdim 796218893Sdimdef OUTT_2r : _F2R<(outs), (ins GRRegs:$r, GRRegs:$val), 797218893Sdim "outt res[$r], $val", 798218893Sdim [(int_xcore_outt GRRegs:$r, GRRegs:$val)]>; 799218893Sdim 800218893Sdimdef OUT_2r : _F2R<(outs), (ins GRRegs:$r, GRRegs:$val), 801218893Sdim "out res[$r], $val", 802218893Sdim [(int_xcore_out GRRegs:$r, GRRegs:$val)]>; 803218893Sdim 804219077Sdimlet Constraints = "$src = $dst" in 805219077Sdimdef OUTSHR_2r : _F2R<(outs GRRegs:$dst), (ins GRRegs:$r, GRRegs:$src), 806219077Sdim "outshr res[$r], $src", 807219077Sdim [(set GRRegs:$dst, (int_xcore_outshr GRRegs:$r, GRRegs:$src))]>; 808219077Sdim 809218893Sdimdef INCT_2r : _F2R<(outs GRRegs:$dst), (ins GRRegs:$r), 810218893Sdim "inct $dst, res[$r]", 811218893Sdim [(set GRRegs:$dst, (int_xcore_inct GRRegs:$r))]>; 812218893Sdim 813218893Sdimdef INT_2r : _F2R<(outs GRRegs:$dst), (ins GRRegs:$r), 814218893Sdim "int $dst, res[$r]", 815218893Sdim [(set GRRegs:$dst, (int_xcore_int GRRegs:$r))]>; 816218893Sdim 817218893Sdimdef IN_2r : _F2R<(outs GRRegs:$dst), (ins GRRegs:$r), 818218893Sdim "in $dst, res[$r]", 819218893Sdim [(set GRRegs:$dst, (int_xcore_in GRRegs:$r))]>; 820218893Sdim 821219077Sdimlet Constraints = "$src = $dst" in 822219077Sdimdef INSHR_2r : _F2R<(outs GRRegs:$dst), (ins GRRegs:$r, GRRegs:$src), 823219077Sdim "inshr $dst, res[$r]", 824219077Sdim [(set GRRegs:$dst, (int_xcore_inshr GRRegs:$r, GRRegs:$src))]>; 825219077Sdim 826218893Sdimdef CHKCT_2r : _F2R<(outs), (ins GRRegs:$r, GRRegs:$val), 827218893Sdim "chkct res[$r], $val", 828218893Sdim [(int_xcore_chkct GRRegs:$r, GRRegs:$val)]>; 829218893Sdim 830218893Sdimdef CHKCT_rus : _F2R<(outs), (ins GRRegs:$r, i32imm:$val), 831218893Sdim "chkct res[$r], $val", 832218893Sdim [(int_xcore_chkct GRRegs:$r, immUs:$val)]>; 833218893Sdim 834218893Sdimdef SETD_2r : _F2R<(outs), (ins GRRegs:$r, GRRegs:$val), 835218893Sdim "setd res[$r], $val", 836218893Sdim [(int_xcore_setd GRRegs:$r, GRRegs:$val)]>; 837218893Sdim 838221345Sdimdef GETST_2r : _F2R<(outs GRRegs:$dst), (ins GRRegs:$r), 839221345Sdim "getst $dst, res[$r]", 840221345Sdim [(set GRRegs:$dst, (int_xcore_getst GRRegs:$r))]>; 841221345Sdim 842221345Sdimdef INITSP_2r : _F2R<(outs), (ins GRRegs:$t, GRRegs:$src), 843221345Sdim "init t[$t]:sp, $src", 844221345Sdim [(int_xcore_initsp GRRegs:$t, GRRegs:$src)]>; 845221345Sdim 846221345Sdimdef INITPC_2r : _F2R<(outs), (ins GRRegs:$t, GRRegs:$src), 847221345Sdim "init t[$t]:pc, $src", 848221345Sdim [(int_xcore_initpc GRRegs:$t, GRRegs:$src)]>; 849221345Sdim 850221345Sdimdef INITCP_2r : _F2R<(outs), (ins GRRegs:$t, GRRegs:$src), 851221345Sdim "init t[$t]:cp, $src", 852221345Sdim [(int_xcore_initcp GRRegs:$t, GRRegs:$src)]>; 853221345Sdim 854221345Sdimdef INITDP_2r : _F2R<(outs), (ins GRRegs:$t, GRRegs:$src), 855221345Sdim "init t[$t]:dp, $src", 856221345Sdim [(int_xcore_initdp GRRegs:$t, GRRegs:$src)]>; 857221345Sdim 858193323Sed// Two operand long 859221345Sdim// TODO endin, peek, 860221345Sdim// getd, testlcl 861193323Seddef BITREV_l2r : _FL2R<(outs GRRegs:$dst), (ins GRRegs:$src), 862193323Sed "bitrev $dst, $src", 863193323Sed [(set GRRegs:$dst, (int_xcore_bitrev GRRegs:$src))]>; 864193323Sed 865193323Seddef BYTEREV_l2r : _FL2R<(outs GRRegs:$dst), (ins GRRegs:$src), 866193323Sed "byterev $dst, $src", 867193323Sed [(set GRRegs:$dst, (bswap GRRegs:$src))]>; 868193323Sed 869193323Seddef CLZ_l2r : _FL2R<(outs GRRegs:$dst), (ins GRRegs:$src), 870193323Sed "clz $dst, $src", 871193323Sed [(set GRRegs:$dst, (ctlz GRRegs:$src))]>; 872193323Sed 873219077Sdimdef SETC_l2r : _FL2R<(outs), (ins GRRegs:$r, GRRegs:$val), 874218893Sdim "setc res[$r], $val", 875218893Sdim [(int_xcore_setc GRRegs:$r, GRRegs:$val)]>; 876218893Sdim 877219077Sdimdef SETTW_l2r : _FL2R<(outs), (ins GRRegs:$r, GRRegs:$val), 878219077Sdim "settw res[$r], $val", 879219077Sdim [(int_xcore_settw GRRegs:$r, GRRegs:$val)]>; 880219077Sdim 881221345Sdimdef GETPS_l2r : _FL2R<(outs GRRegs:$dst), (ins GRRegs:$src), 882221345Sdim "get $dst, ps[$src]", 883221345Sdim [(set GRRegs:$dst, (int_xcore_getps GRRegs:$src))]>; 884221345Sdim 885221345Sdimdef SETPS_l2r : _FL2R<(outs), (ins GRRegs:$src1, GRRegs:$src2), 886221345Sdim "set ps[$src1], $src2", 887221345Sdim [(int_xcore_setps GRRegs:$src1, GRRegs:$src2)]>; 888221345Sdim 889221345Sdimdef INITLR_l2r : _FL2R<(outs), (ins GRRegs:$t, GRRegs:$src), 890221345Sdim "init t[$t]:lr, $src", 891221345Sdim [(int_xcore_initlr GRRegs:$t, GRRegs:$src)]>; 892221345Sdim 893221345Sdimdef SETCLK_l2r : _FL2R<(outs), (ins GRRegs:$src1, GRRegs:$src2), 894221345Sdim "setclk res[$src1], $src2", 895221345Sdim [(int_xcore_setclk GRRegs:$src1, GRRegs:$src2)]>; 896221345Sdim 897221345Sdimdef SETRDY_l2r : _FL2R<(outs), (ins GRRegs:$src1, GRRegs:$src2), 898221345Sdim "setrdy res[$src1], $src2", 899221345Sdim [(int_xcore_setrdy GRRegs:$src1, GRRegs:$src2)]>; 900221345Sdim 901221345Sdimdef SETPSC_l2r : _FL2R<(outs), (ins GRRegs:$src1, GRRegs:$src2), 902221345Sdim "setpsc res[$src1], $src2", 903221345Sdim [(int_xcore_setpsc GRRegs:$src1, GRRegs:$src2)]>; 904221345Sdim 905193323Sed// One operand short 906221345Sdim// TODO edu, eeu, waitet, waitef, tstart, clrtp 907219077Sdim// setdp, setcp, setev, kcall 908193323Sed// dgetreg 909221345Sdimdef MSYNC_1r : _F1R<(outs), (ins GRRegs:$i), 910221345Sdim "msync res[$i]", 911221345Sdim [(int_xcore_msync GRRegs:$i)]>; 912221345Sdimdef MJOIN_1r : _F1R<(outs), (ins GRRegs:$i), 913221345Sdim "mjoin res[$i]", 914221345Sdim [(int_xcore_mjoin GRRegs:$i)]>; 915221345Sdim 916204642Srdivackylet isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in 917193323Seddef BAU_1r : _F1R<(outs), (ins GRRegs:$addr), 918193323Sed "bau $addr", 919193323Sed [(brind GRRegs:$addr)]>; 920193323Sed 921204642Srdivackylet isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in 922204642Srdivackydef BR_JT : PseudoInstXCore<(outs), (ins InlineJT:$t, GRRegs:$i), 923204642Srdivacky "bru $i\n$t", 924204642Srdivacky [(XCoreBR_JT tjumptable:$t, GRRegs:$i)]>; 925204642Srdivacky 926204642Srdivackylet isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in 927204642Srdivackydef BR_JT32 : PseudoInstXCore<(outs), (ins InlineJT32:$t, GRRegs:$i), 928204642Srdivacky "bru $i\n$t", 929204642Srdivacky [(XCoreBR_JT32 tjumptable:$t, GRRegs:$i)]>; 930204642Srdivacky 931193323Sedlet Defs=[SP], neverHasSideEffects=1 in 932193323Seddef SETSP_1r : _F1R<(outs), (ins GRRegs:$src), 933193323Sed "set sp, $src", 934193323Sed []>; 935193323Sed 936204642Srdivackylet hasCtrlDep = 1 in 937193323Seddef ECALLT_1r : _F1R<(outs), (ins GRRegs:$src), 938193323Sed "ecallt $src", 939193323Sed []>; 940193323Sed 941204642Srdivackylet hasCtrlDep = 1 in 942193323Seddef ECALLF_1r : _F1R<(outs), (ins GRRegs:$src), 943193323Sed "ecallf $src", 944193323Sed []>; 945193323Sed 946193323Sedlet isCall=1, 947203954Srdivacky// All calls clobber the link register and the non-callee-saved registers: 948193323SedDefs = [R0, R1, R2, R3, R11, LR] in { 949193323Seddef BLA_1r : _F1R<(outs), (ins GRRegs:$addr, variable_ops), 950193323Sed "bla $addr", 951193323Sed [(XCoreBranchLink GRRegs:$addr)]>; 952193323Sed} 953193323Sed 954219077Sdimdef SYNCR_1r : _F1R<(outs), (ins GRRegs:$r), 955219077Sdim "syncr res[$r]", 956219077Sdim [(int_xcore_syncr GRRegs:$r)]>; 957219077Sdim 958218893Sdimdef FREER_1r : _F1R<(outs), (ins GRRegs:$r), 959218893Sdim "freer res[$r]", 960218893Sdim [(int_xcore_freer GRRegs:$r)]>; 961218893Sdim 962219077Sdimlet Uses=[R11] in 963219077Sdimdef SETV_1r : _F1R<(outs), (ins GRRegs:$r), 964219077Sdim "setv res[$r], r11", 965219077Sdim [(int_xcore_setv GRRegs:$r, R11)]>; 966219077Sdim 967219077Sdimdef EEU_1r : _F1R<(outs), (ins GRRegs:$r), 968219077Sdim "eeu res[$r]", 969219077Sdim [(int_xcore_eeu GRRegs:$r)]>; 970219077Sdim 971193323Sed// Zero operand short 972221345Sdim// TODO freet, ldspc, stspc, ldssr, stssr, ldsed, stsed, 973193323Sed// stet, geted, getet, getkep, getksp, setkep, getid, kret, dcall, dret, 974193323Sed// dentsp, drestsp 975193323Sed 976219077Sdimdef CLRE_0R : _F0R<(outs), (ins), "clre", [(int_xcore_clre)]>; 977219077Sdim 978193323Sedlet Defs = [R11] in 979193323Seddef GETID_0R : _F0R<(outs), (ins), 980193323Sed "get r11, id", 981193323Sed [(set R11, (int_xcore_getid))]>; 982193323Sed 983221345Sdimdef SSYNC_0r : _F0R<(outs), (ins), 984221345Sdim "ssync", 985221345Sdim [(int_xcore_ssync)]>; 986221345Sdim 987219077Sdimlet isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1, 988219077Sdim hasSideEffects = 1 in 989219077Sdimdef WAITEU_0R : _F0R<(outs), (ins), 990219077Sdim "waiteu", 991219077Sdim [(brind (int_xcore_waitevent))]>; 992219077Sdim 993193323Sed//===----------------------------------------------------------------------===// 994193323Sed// Non-Instruction Patterns 995193323Sed//===----------------------------------------------------------------------===// 996193323Sed 997193323Seddef : Pat<(XCoreBranchLink tglobaladdr:$addr), (BL_lu10 tglobaladdr:$addr)>; 998193323Seddef : Pat<(XCoreBranchLink texternalsym:$addr), (BL_lu10 texternalsym:$addr)>; 999193323Sed 1000193323Sed/// sext_inreg 1001193323Seddef : Pat<(sext_inreg GRRegs:$b, i1), (SEXT_rus GRRegs:$b, 1)>; 1002193323Seddef : Pat<(sext_inreg GRRegs:$b, i8), (SEXT_rus GRRegs:$b, 8)>; 1003193323Seddef : Pat<(sext_inreg GRRegs:$b, i16), (SEXT_rus GRRegs:$b, 16)>; 1004193323Sed 1005193323Sed/// loads 1006193323Seddef : Pat<(zextloadi8 (add GRRegs:$addr, GRRegs:$offset)), 1007193323Sed (LD8U_3r GRRegs:$addr, GRRegs:$offset)>; 1008193323Seddef : Pat<(zextloadi8 GRRegs:$addr), (LD8U_3r GRRegs:$addr, (LDC_ru6 0))>; 1009193323Sed 1010198090Srdivackydef : Pat<(sextloadi16 (lda16f GRRegs:$addr, GRRegs:$offset)), 1011193323Sed (LD16S_3r GRRegs:$addr, GRRegs:$offset)>; 1012193323Seddef : Pat<(sextloadi16 GRRegs:$addr), (LD16S_3r GRRegs:$addr, (LDC_ru6 0))>; 1013193323Sed 1014193323Seddef : Pat<(load (ldawf GRRegs:$addr, GRRegs:$offset)), 1015193323Sed (LDW_3r GRRegs:$addr, GRRegs:$offset)>; 1016193323Seddef : Pat<(load (add GRRegs:$addr, immUs4:$offset)), 1017193323Sed (LDW_2rus GRRegs:$addr, (div4_xform immUs4:$offset))>; 1018193323Seddef : Pat<(load GRRegs:$addr), (LDW_2rus GRRegs:$addr, 0)>; 1019193323Sed 1020193323Sed/// anyext 1021193323Seddef : Pat<(extloadi8 (add GRRegs:$addr, GRRegs:$offset)), 1022193323Sed (LD8U_3r GRRegs:$addr, GRRegs:$offset)>; 1023193323Seddef : Pat<(extloadi8 GRRegs:$addr), (LD8U_3r GRRegs:$addr, (LDC_ru6 0))>; 1024193323Seddef : Pat<(extloadi16 (lda16f GRRegs:$addr, GRRegs:$offset)), 1025193323Sed (LD16S_3r GRRegs:$addr, GRRegs:$offset)>; 1026193323Seddef : Pat<(extloadi16 GRRegs:$addr), (LD16S_3r GRRegs:$addr, (LDC_ru6 0))>; 1027193323Sed 1028193323Sed/// stores 1029193323Seddef : Pat<(truncstorei8 GRRegs:$val, (add GRRegs:$addr, GRRegs:$offset)), 1030193323Sed (ST8_l3r GRRegs:$val, GRRegs:$addr, GRRegs:$offset)>; 1031193323Seddef : Pat<(truncstorei8 GRRegs:$val, GRRegs:$addr), 1032193323Sed (ST8_l3r GRRegs:$val, GRRegs:$addr, (LDC_ru6 0))>; 1033193323Sed 1034193323Seddef : Pat<(truncstorei16 GRRegs:$val, (lda16f GRRegs:$addr, GRRegs:$offset)), 1035193323Sed (ST16_l3r GRRegs:$val, GRRegs:$addr, GRRegs:$offset)>; 1036193323Seddef : Pat<(truncstorei16 GRRegs:$val, GRRegs:$addr), 1037193323Sed (ST16_l3r GRRegs:$val, GRRegs:$addr, (LDC_ru6 0))>; 1038193323Sed 1039193323Seddef : Pat<(store GRRegs:$val, (ldawf GRRegs:$addr, GRRegs:$offset)), 1040193323Sed (STW_3r GRRegs:$val, GRRegs:$addr, GRRegs:$offset)>; 1041193323Seddef : Pat<(store GRRegs:$val, (add GRRegs:$addr, immUs4:$offset)), 1042193323Sed (STW_2rus GRRegs:$val, GRRegs:$addr, (div4_xform immUs4:$offset))>; 1043193323Seddef : Pat<(store GRRegs:$val, GRRegs:$addr), 1044193323Sed (STW_2rus GRRegs:$val, GRRegs:$addr, 0)>; 1045193323Sed 1046193323Sed/// cttz 1047193323Seddef : Pat<(cttz GRRegs:$src), (CLZ_l2r (BITREV_l2r GRRegs:$src))>; 1048193323Sed 1049193323Sed/// trap 1050193323Seddef : Pat<(trap), (ECALLF_1r (LDC_ru6 0))>; 1051193323Sed 1052193323Sed/// 1053193323Sed/// branch patterns 1054193323Sed/// 1055193323Sed 1056193323Sed// unconditional branch 1057193323Seddef : Pat<(br bb:$addr), (BRFU_lu6 bb:$addr)>; 1058193323Sed 1059193323Sed// direct match equal/notequal zero brcond 1060193323Seddef : Pat<(brcond (setne GRRegs:$lhs, 0), bb:$dst), 1061193323Sed (BRFT_lru6 GRRegs:$lhs, bb:$dst)>; 1062193323Seddef : Pat<(brcond (seteq GRRegs:$lhs, 0), bb:$dst), 1063193323Sed (BRFF_lru6 GRRegs:$lhs, bb:$dst)>; 1064193323Sed 1065193323Seddef : Pat<(brcond (setle GRRegs:$lhs, GRRegs:$rhs), bb:$dst), 1066193323Sed (BRFF_lru6 (LSS_3r GRRegs:$rhs, GRRegs:$lhs), bb:$dst)>; 1067193323Seddef : Pat<(brcond (setule GRRegs:$lhs, GRRegs:$rhs), bb:$dst), 1068193323Sed (BRFF_lru6 (LSU_3r GRRegs:$rhs, GRRegs:$lhs), bb:$dst)>; 1069193323Seddef : Pat<(brcond (setge GRRegs:$lhs, GRRegs:$rhs), bb:$dst), 1070193323Sed (BRFF_lru6 (LSS_3r GRRegs:$lhs, GRRegs:$rhs), bb:$dst)>; 1071193323Seddef : Pat<(brcond (setuge GRRegs:$lhs, GRRegs:$rhs), bb:$dst), 1072193323Sed (BRFF_lru6 (LSU_3r GRRegs:$lhs, GRRegs:$rhs), bb:$dst)>; 1073193323Seddef : Pat<(brcond (setne GRRegs:$lhs, GRRegs:$rhs), bb:$dst), 1074193323Sed (BRFF_lru6 (EQ_3r GRRegs:$lhs, GRRegs:$rhs), bb:$dst)>; 1075193323Seddef : Pat<(brcond (setne GRRegs:$lhs, immUs:$rhs), bb:$dst), 1076193323Sed (BRFF_lru6 (EQ_2rus GRRegs:$lhs, immUs:$rhs), bb:$dst)>; 1077193323Sed 1078193323Sed// generic brcond pattern 1079193323Seddef : Pat<(brcond GRRegs:$cond, bb:$addr), (BRFT_lru6 GRRegs:$cond, bb:$addr)>; 1080193323Sed 1081193323Sed 1082193323Sed/// 1083193323Sed/// Select patterns 1084193323Sed/// 1085193323Sed 1086193323Sed// direct match equal/notequal zero select 1087193323Seddef : Pat<(select (setne GRRegs:$lhs, 0), GRRegs:$T, GRRegs:$F), 1088193323Sed (SELECT_CC GRRegs:$lhs, GRRegs:$T, GRRegs:$F)>; 1089193323Sed 1090193323Seddef : Pat<(select (seteq GRRegs:$lhs, 0), GRRegs:$T, GRRegs:$F), 1091193323Sed (SELECT_CC GRRegs:$lhs, GRRegs:$F, GRRegs:$T)>; 1092193323Sed 1093193323Seddef : Pat<(select (setle GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F), 1094193323Sed (SELECT_CC (LSS_3r GRRegs:$rhs, GRRegs:$lhs), GRRegs:$F, GRRegs:$T)>; 1095193323Seddef : Pat<(select (setule GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F), 1096193323Sed (SELECT_CC (LSU_3r GRRegs:$rhs, GRRegs:$lhs), GRRegs:$F, GRRegs:$T)>; 1097193323Seddef : Pat<(select (setge GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F), 1098193323Sed (SELECT_CC (LSS_3r GRRegs:$lhs, GRRegs:$rhs), GRRegs:$F, GRRegs:$T)>; 1099193323Seddef : Pat<(select (setuge GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F), 1100193323Sed (SELECT_CC (LSU_3r GRRegs:$lhs, GRRegs:$rhs), GRRegs:$F, GRRegs:$T)>; 1101193323Seddef : Pat<(select (setne GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F), 1102193323Sed (SELECT_CC (EQ_3r GRRegs:$lhs, GRRegs:$rhs), GRRegs:$F, GRRegs:$T)>; 1103193323Seddef : Pat<(select (setne GRRegs:$lhs, immUs:$rhs), GRRegs:$T, GRRegs:$F), 1104193323Sed (SELECT_CC (EQ_2rus GRRegs:$lhs, immUs:$rhs), GRRegs:$F, GRRegs:$T)>; 1105193323Sed 1106193323Sed/// 1107193323Sed/// setcc patterns, only matched when none of the above brcond 1108193323Sed/// patterns match 1109193323Sed/// 1110193323Sed 1111193323Sed// setcc 2 register operands 1112193323Seddef : Pat<(setle GRRegs:$lhs, GRRegs:$rhs), 1113193323Sed (EQ_2rus (LSS_3r GRRegs:$rhs, GRRegs:$lhs), 0)>; 1114193323Seddef : Pat<(setule GRRegs:$lhs, GRRegs:$rhs), 1115193323Sed (EQ_2rus (LSU_3r GRRegs:$rhs, GRRegs:$lhs), 0)>; 1116193323Sed 1117193323Seddef : Pat<(setgt GRRegs:$lhs, GRRegs:$rhs), 1118193323Sed (LSS_3r GRRegs:$rhs, GRRegs:$lhs)>; 1119193323Seddef : Pat<(setugt GRRegs:$lhs, GRRegs:$rhs), 1120193323Sed (LSU_3r GRRegs:$rhs, GRRegs:$lhs)>; 1121193323Sed 1122193323Seddef : Pat<(setge GRRegs:$lhs, GRRegs:$rhs), 1123193323Sed (EQ_2rus (LSS_3r GRRegs:$lhs, GRRegs:$rhs), 0)>; 1124193323Seddef : Pat<(setuge GRRegs:$lhs, GRRegs:$rhs), 1125193323Sed (EQ_2rus (LSU_3r GRRegs:$lhs, GRRegs:$rhs), 0)>; 1126193323Sed 1127193323Seddef : Pat<(setlt GRRegs:$lhs, GRRegs:$rhs), 1128193323Sed (LSS_3r GRRegs:$lhs, GRRegs:$rhs)>; 1129193323Seddef : Pat<(setult GRRegs:$lhs, GRRegs:$rhs), 1130193323Sed (LSU_3r GRRegs:$lhs, GRRegs:$rhs)>; 1131193323Sed 1132193323Seddef : Pat<(setne GRRegs:$lhs, GRRegs:$rhs), 1133193323Sed (EQ_2rus (EQ_3r GRRegs:$lhs, GRRegs:$rhs), 0)>; 1134193323Sed 1135193323Seddef : Pat<(seteq GRRegs:$lhs, GRRegs:$rhs), 1136193323Sed (EQ_3r GRRegs:$lhs, GRRegs:$rhs)>; 1137193323Sed 1138193323Sed// setcc reg/imm operands 1139193323Seddef : Pat<(seteq GRRegs:$lhs, immUs:$rhs), 1140193323Sed (EQ_2rus GRRegs:$lhs, immUs:$rhs)>; 1141193323Seddef : Pat<(setne GRRegs:$lhs, immUs:$rhs), 1142193323Sed (EQ_2rus (EQ_2rus GRRegs:$lhs, immUs:$rhs), 0)>; 1143193323Sed 1144193323Sed// misc 1145193323Seddef : Pat<(add GRRegs:$addr, immUs4:$offset), 1146193323Sed (LDAWF_l2rus GRRegs:$addr, (div4_xform immUs4:$offset))>; 1147193323Sed 1148193323Seddef : Pat<(sub GRRegs:$addr, immUs4:$offset), 1149193323Sed (LDAWB_l2rus GRRegs:$addr, (div4_xform immUs4:$offset))>; 1150193323Sed 1151193323Seddef : Pat<(and GRRegs:$val, immMskBitp:$mask), 1152193323Sed (ZEXT_rus GRRegs:$val, (msksize_xform immMskBitp:$mask))>; 1153193323Sed 1154193323Sed// (sub X, imm) gets canonicalized to (add X, -imm). Match this form. 1155193323Seddef : Pat<(add GRRegs:$src1, immUsNeg:$src2), 1156193323Sed (SUB_2rus GRRegs:$src1, (neg_xform immUsNeg:$src2))>; 1157193323Sed 1158193323Seddef : Pat<(add GRRegs:$src1, immUs4Neg:$src2), 1159193323Sed (LDAWB_l2rus GRRegs:$src1, (div4neg_xform immUs4Neg:$src2))>; 1160193323Sed 1161193323Sed/// 1162193323Sed/// Some peepholes 1163193323Sed/// 1164193323Sed 1165193323Seddef : Pat<(mul GRRegs:$src, 3), 1166193323Sed (LDA16F_l3r GRRegs:$src, GRRegs:$src)>; 1167193323Sed 1168193323Seddef : Pat<(mul GRRegs:$src, 5), 1169193323Sed (LDAWF_l3r GRRegs:$src, GRRegs:$src)>; 1170193323Sed 1171193323Seddef : Pat<(mul GRRegs:$src, -3), 1172193323Sed (LDAWB_l3r GRRegs:$src, GRRegs:$src)>; 1173193323Sed 1174193323Sed// ashr X, 32 is equivalent to ashr X, 31 on the XCore. 1175193323Seddef : Pat<(sra GRRegs:$src, 31), 1176193323Sed (ASHR_l2rus GRRegs:$src, 32)>; 1177193323Sed 1178198090Srdivackydef : Pat<(brcond (setlt GRRegs:$lhs, 0), bb:$dst), 1179198090Srdivacky (BRFT_lru6 (ASHR_l2rus GRRegs:$lhs, 32), bb:$dst)>; 1180198090Srdivacky 1181198090Srdivacky// setge X, 0 is canonicalized to setgt X, -1 1182198090Srdivackydef : Pat<(brcond (setgt GRRegs:$lhs, -1), bb:$dst), 1183198090Srdivacky (BRFF_lru6 (ASHR_l2rus GRRegs:$lhs, 32), bb:$dst)>; 1184198090Srdivacky 1185198090Srdivackydef : Pat<(select (setlt GRRegs:$lhs, 0), GRRegs:$T, GRRegs:$F), 1186198090Srdivacky (SELECT_CC (ASHR_l2rus GRRegs:$lhs, 32), GRRegs:$T, GRRegs:$F)>; 1187198090Srdivacky 1188198090Srdivackydef : Pat<(select (setgt GRRegs:$lhs, -1), GRRegs:$T, GRRegs:$F), 1189198090Srdivacky (SELECT_CC (ASHR_l2rus GRRegs:$lhs, 32), GRRegs:$F, GRRegs:$T)>; 1190198090Srdivacky 1191198090Srdivackydef : Pat<(setgt GRRegs:$lhs, -1), 1192198090Srdivacky (EQ_2rus (ASHR_l2rus GRRegs:$lhs, 32), 0)>; 1193198090Srdivacky 1194198090Srdivackydef : Pat<(sra (shl GRRegs:$src, immBpwSubBitp:$imm), immBpwSubBitp:$imm), 1195198090Srdivacky (SEXT_rus GRRegs:$src, (bpwsub_xform immBpwSubBitp:$imm))>; 1196