XCoreInstrInfo.td revision 210299
1193323Sed//===- XCoreInstrInfo.td - Target Description for XCore ----*- tablegen -*-===// 2193323Sed// 3193323Sed// The LLVM Compiler Infrastructure 4193323Sed// 5193323Sed// This file is distributed under the University of Illinois Open Source 6193323Sed// License. See LICENSE.TXT for details. 7193323Sed// 8193323Sed//===----------------------------------------------------------------------===// 9193323Sed// 10193323Sed// This file describes the XCore instructions in TableGen format. 11193323Sed// 12193323Sed//===----------------------------------------------------------------------===// 13193323Sed 14193323Sed// Uses of CP, DP are not currently reflected in the patterns, since 15193323Sed// having a physical register as an operand prevents loop hoisting and 16193323Sed// since the value of these registers never changes during the life of the 17193323Sed// function. 18193323Sed 19193323Sed//===----------------------------------------------------------------------===// 20193323Sed// Instruction format superclass. 21193323Sed//===----------------------------------------------------------------------===// 22193323Sed 23193323Sedinclude "XCoreInstrFormats.td" 24193323Sed 25193323Sed//===----------------------------------------------------------------------===// 26193323Sed// XCore specific DAG Nodes. 27193323Sed// 28193323Sed 29193323Sed// Call 30193323Seddef SDT_XCoreBranchLink : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>; 31193323Seddef XCoreBranchLink : SDNode<"XCoreISD::BL",SDT_XCoreBranchLink, 32205407Srdivacky [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag, 33205407Srdivacky SDNPVariadic]>; 34193323Sed 35206083Srdivackydef XCoreRetsp : SDNode<"XCoreISD::RETSP", SDTBrind, 36193323Sed [SDNPHasChain, SDNPOptInFlag]>; 37193323Sed 38204642Srdivackydef SDT_XCoreBR_JT : SDTypeProfile<0, 2, 39204642Srdivacky [SDTCisVT<0, i32>, SDTCisVT<1, i32>]>; 40204642Srdivacky 41204642Srdivackydef XCoreBR_JT : SDNode<"XCoreISD::BR_JT", SDT_XCoreBR_JT, 42204642Srdivacky [SDNPHasChain]>; 43204642Srdivacky 44204642Srdivackydef XCoreBR_JT32 : SDNode<"XCoreISD::BR_JT32", SDT_XCoreBR_JT, 45204642Srdivacky [SDNPHasChain]>; 46204642Srdivacky 47193323Seddef SDT_XCoreAddress : SDTypeProfile<1, 1, 48193323Sed [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>; 49193323Sed 50193323Seddef pcrelwrapper : SDNode<"XCoreISD::PCRelativeWrapper", SDT_XCoreAddress, 51193323Sed []>; 52193323Sed 53193323Seddef dprelwrapper : SDNode<"XCoreISD::DPRelativeWrapper", SDT_XCoreAddress, 54193323Sed []>; 55193323Sed 56193323Seddef cprelwrapper : SDNode<"XCoreISD::CPRelativeWrapper", SDT_XCoreAddress, 57193323Sed []>; 58193323Sed 59193323Seddef SDT_XCoreStwsp : SDTypeProfile<0, 2, [SDTCisInt<1>]>; 60193323Seddef XCoreStwsp : SDNode<"XCoreISD::STWSP", SDT_XCoreStwsp, 61193323Sed [SDNPHasChain]>; 62193323Sed 63193323Sed// These are target-independent nodes, but have target-specific formats. 64193323Seddef SDT_XCoreCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>; 65193323Seddef SDT_XCoreCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, 66193323Sed SDTCisVT<1, i32> ]>; 67193323Sed 68193323Seddef callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_XCoreCallSeqStart, 69193323Sed [SDNPHasChain, SDNPOutFlag]>; 70193323Seddef callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_XCoreCallSeqEnd, 71193323Sed [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>; 72193323Sed 73193323Sed//===----------------------------------------------------------------------===// 74193323Sed// Instruction Pattern Stuff 75193323Sed//===----------------------------------------------------------------------===// 76193323Sed 77193323Seddef div4_xform : SDNodeXForm<imm, [{ 78193323Sed // Transformation function: imm/4 79193323Sed assert(N->getZExtValue() % 4 == 0); 80193323Sed return getI32Imm(N->getZExtValue()/4); 81193323Sed}]>; 82193323Sed 83193323Seddef msksize_xform : SDNodeXForm<imm, [{ 84193323Sed // Transformation function: get the size of a mask 85193323Sed assert(isMask_32(N->getZExtValue())); 86193323Sed // look for the first non-zero bit 87193323Sed return getI32Imm(32 - CountLeadingZeros_32(N->getZExtValue())); 88193323Sed}]>; 89193323Sed 90193323Seddef neg_xform : SDNodeXForm<imm, [{ 91193323Sed // Transformation function: -imm 92193323Sed uint32_t value = N->getZExtValue(); 93193323Sed return getI32Imm(-value); 94193323Sed}]>; 95193323Sed 96198090Srdivackydef bpwsub_xform : SDNodeXForm<imm, [{ 97198090Srdivacky // Transformation function: 32-imm 98198090Srdivacky uint32_t value = N->getZExtValue(); 99198090Srdivacky return getI32Imm(32-value); 100198090Srdivacky}]>; 101198090Srdivacky 102193323Seddef div4neg_xform : SDNodeXForm<imm, [{ 103193323Sed // Transformation function: -imm/4 104193323Sed uint32_t value = N->getZExtValue(); 105193323Sed assert(-value % 4 == 0); 106193323Sed return getI32Imm(-value/4); 107193323Sed}]>; 108193323Sed 109193323Seddef immUs4Neg : PatLeaf<(imm), [{ 110193323Sed uint32_t value = (uint32_t)N->getZExtValue(); 111193323Sed return (-value)%4 == 0 && (-value)/4 <= 11; 112193323Sed}]>; 113193323Sed 114193323Seddef immUs4 : PatLeaf<(imm), [{ 115193323Sed uint32_t value = (uint32_t)N->getZExtValue(); 116193323Sed return value%4 == 0 && value/4 <= 11; 117193323Sed}]>; 118193323Sed 119193323Seddef immUsNeg : PatLeaf<(imm), [{ 120193323Sed return -((uint32_t)N->getZExtValue()) <= 11; 121193323Sed}]>; 122193323Sed 123193323Seddef immUs : PatLeaf<(imm), [{ 124193323Sed return (uint32_t)N->getZExtValue() <= 11; 125193323Sed}]>; 126193323Sed 127193323Seddef immU6 : PatLeaf<(imm), [{ 128193323Sed return (uint32_t)N->getZExtValue() < (1 << 6); 129193323Sed}]>; 130193323Sed 131193323Seddef immU10 : PatLeaf<(imm), [{ 132193323Sed return (uint32_t)N->getZExtValue() < (1 << 10); 133193323Sed}]>; 134193323Sed 135193323Seddef immU16 : PatLeaf<(imm), [{ 136193323Sed return (uint32_t)N->getZExtValue() < (1 << 16); 137193323Sed}]>; 138193323Sed 139193323Seddef immU20 : PatLeaf<(imm), [{ 140193323Sed return (uint32_t)N->getZExtValue() < (1 << 20); 141193323Sed}]>; 142193323Sed 143193323Seddef immMskBitp : PatLeaf<(imm), [{ 144193323Sed uint32_t value = (uint32_t)N->getZExtValue(); 145193323Sed if (!isMask_32(value)) { 146193323Sed return false; 147193323Sed } 148193323Sed int msksize = 32 - CountLeadingZeros_32(value); 149193323Sed return (msksize >= 1 && msksize <= 8) 150193323Sed || msksize == 16 151193323Sed || msksize == 24 152193323Sed || msksize == 32; 153193323Sed}]>; 154193323Sed 155193323Seddef immBitp : PatLeaf<(imm), [{ 156193323Sed uint32_t value = (uint32_t)N->getZExtValue(); 157193323Sed return (value >= 1 && value <= 8) 158193323Sed || value == 16 159193323Sed || value == 24 160193323Sed || value == 32; 161193323Sed}]>; 162193323Sed 163198090Srdivackydef immBpwSubBitp : PatLeaf<(imm), [{ 164198090Srdivacky uint32_t value = (uint32_t)N->getZExtValue(); 165198090Srdivacky return (value >= 24 && value <= 31) 166198090Srdivacky || value == 16 167198090Srdivacky || value == 8 168198090Srdivacky || value == 0; 169198090Srdivacky}]>; 170198090Srdivacky 171193323Seddef lda16f : PatFrag<(ops node:$addr, node:$offset), 172193323Sed (add node:$addr, (shl node:$offset, 1))>; 173193323Seddef lda16b : PatFrag<(ops node:$addr, node:$offset), 174193323Sed (sub node:$addr, (shl node:$offset, 1))>; 175193323Seddef ldawf : PatFrag<(ops node:$addr, node:$offset), 176193323Sed (add node:$addr, (shl node:$offset, 2))>; 177193323Seddef ldawb : PatFrag<(ops node:$addr, node:$offset), 178193323Sed (sub node:$addr, (shl node:$offset, 2))>; 179193323Sed 180193323Sed// Instruction operand types 181193323Seddef calltarget : Operand<i32>; 182193323Seddef brtarget : Operand<OtherVT>; 183193323Seddef pclabel : Operand<i32>; 184193323Sed 185193323Sed// Addressing modes 186193323Seddef ADDRspii : ComplexPattern<i32, 2, "SelectADDRspii", [add, frameindex], []>; 187193323Seddef ADDRdpii : ComplexPattern<i32, 2, "SelectADDRdpii", [add, dprelwrapper], 188193323Sed []>; 189193323Seddef ADDRcpii : ComplexPattern<i32, 2, "SelectADDRcpii", [add, cprelwrapper], 190193323Sed []>; 191193323Sed 192193323Sed// Address operands 193193323Seddef MEMii : Operand<i32> { 194193323Sed let PrintMethod = "printMemOperand"; 195193323Sed let MIOperandInfo = (ops i32imm, i32imm); 196193323Sed} 197193323Sed 198204642Srdivacky// Jump tables. 199204642Srdivackydef InlineJT : Operand<i32> { 200204642Srdivacky let PrintMethod = "printInlineJT"; 201204642Srdivacky} 202204642Srdivacky 203204642Srdivackydef InlineJT32 : Operand<i32> { 204204642Srdivacky let PrintMethod = "printInlineJT32"; 205204642Srdivacky} 206204642Srdivacky 207193323Sed//===----------------------------------------------------------------------===// 208193323Sed// Instruction Class Templates 209193323Sed//===----------------------------------------------------------------------===// 210193323Sed 211193323Sed// Three operand short 212193323Sed 213193323Sedmulticlass F3R_2RUS<string OpcStr, SDNode OpNode> { 214193323Sed def _3r: _F3R< 215193323Sed (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), 216193323Sed !strconcat(OpcStr, " $dst, $b, $c"), 217193323Sed [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>; 218193323Sed def _2rus : _F2RUS< 219193323Sed (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c), 220193323Sed !strconcat(OpcStr, " $dst, $b, $c"), 221193323Sed [(set GRRegs:$dst, (OpNode GRRegs:$b, immUs:$c))]>; 222193323Sed} 223193323Sed 224193323Sedmulticlass F3R_2RUS_np<string OpcStr> { 225193323Sed def _3r: _F3R< 226193323Sed (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), 227193323Sed !strconcat(OpcStr, " $dst, $b, $c"), 228193323Sed []>; 229193323Sed def _2rus : _F2RUS< 230193323Sed (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c), 231193323Sed !strconcat(OpcStr, " $dst, $b, $c"), 232193323Sed []>; 233193323Sed} 234193323Sed 235193323Sedmulticlass F3R_2RBITP<string OpcStr, SDNode OpNode> { 236193323Sed def _3r: _F3R< 237193323Sed (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), 238193323Sed !strconcat(OpcStr, " $dst, $b, $c"), 239193323Sed [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>; 240193323Sed def _2rus : _F2RUS< 241193323Sed (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c), 242193323Sed !strconcat(OpcStr, " $dst, $b, $c"), 243193323Sed [(set GRRegs:$dst, (OpNode GRRegs:$b, immBitp:$c))]>; 244193323Sed} 245193323Sed 246193323Sedclass F3R<string OpcStr, SDNode OpNode> : _F3R< 247193323Sed (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), 248193323Sed !strconcat(OpcStr, " $dst, $b, $c"), 249193323Sed [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>; 250193323Sed 251193323Sedclass F3R_np<string OpcStr> : _F3R< 252193323Sed (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), 253193323Sed !strconcat(OpcStr, " $dst, $b, $c"), 254193323Sed []>; 255193323Sed// Three operand long 256193323Sed 257193323Sed/// FL3R_L2RUS multiclass - Define a normal FL3R/FL2RUS pattern in one shot. 258193323Sedmulticlass FL3R_L2RUS<string OpcStr, SDNode OpNode> { 259193323Sed def _l3r: _FL3R< 260193323Sed (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), 261193323Sed !strconcat(OpcStr, " $dst, $b, $c"), 262193323Sed [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>; 263193323Sed def _l2rus : _FL2RUS< 264193323Sed (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c), 265193323Sed !strconcat(OpcStr, " $dst, $b, $c"), 266193323Sed [(set GRRegs:$dst, (OpNode GRRegs:$b, immUs:$c))]>; 267193323Sed} 268193323Sed 269193323Sed/// FL3R_L2RUS multiclass - Define a normal FL3R/FL2RUS pattern in one shot. 270193323Sedmulticlass FL3R_L2RBITP<string OpcStr, SDNode OpNode> { 271193323Sed def _l3r: _FL3R< 272193323Sed (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), 273193323Sed !strconcat(OpcStr, " $dst, $b, $c"), 274193323Sed [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>; 275193323Sed def _l2rus : _FL2RUS< 276193323Sed (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c), 277193323Sed !strconcat(OpcStr, " $dst, $b, $c"), 278193323Sed [(set GRRegs:$dst, (OpNode GRRegs:$b, immBitp:$c))]>; 279193323Sed} 280193323Sed 281193323Sedclass FL3R<string OpcStr, SDNode OpNode> : _FL3R< 282193323Sed (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), 283193323Sed !strconcat(OpcStr, " $dst, $b, $c"), 284193323Sed [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>; 285193323Sed 286193323Sed// Register - U6 287193323Sed// Operand register - U6 288193323Sedmulticlass FRU6_LRU6_branch<string OpcStr> { 289193323Sed def _ru6: _FRU6< 290193323Sed (outs), (ins GRRegs:$cond, brtarget:$dest), 291193323Sed !strconcat(OpcStr, " $cond, $dest"), 292193323Sed []>; 293193323Sed def _lru6: _FLRU6< 294193323Sed (outs), (ins GRRegs:$cond, brtarget:$dest), 295193323Sed !strconcat(OpcStr, " $cond, $dest"), 296193323Sed []>; 297193323Sed} 298193323Sed 299193323Sedmulticlass FRU6_LRU6_cp<string OpcStr> { 300193323Sed def _ru6: _FRU6< 301193323Sed (outs GRRegs:$dst), (ins i32imm:$a), 302193323Sed !strconcat(OpcStr, " $dst, cp[$a]"), 303193323Sed []>; 304193323Sed def _lru6: _FLRU6< 305193323Sed (outs GRRegs:$dst), (ins i32imm:$a), 306193323Sed !strconcat(OpcStr, " $dst, cp[$a]"), 307193323Sed []>; 308193323Sed} 309193323Sed 310193323Sed// U6 311193323Sedmulticlass FU6_LU6<string OpcStr, SDNode OpNode> { 312193323Sed def _u6: _FU6< 313193323Sed (outs), (ins i32imm:$b), 314193323Sed !strconcat(OpcStr, " $b"), 315193323Sed [(OpNode immU6:$b)]>; 316193323Sed def _lu6: _FLU6< 317193323Sed (outs), (ins i32imm:$b), 318193323Sed !strconcat(OpcStr, " $b"), 319193323Sed [(OpNode immU16:$b)]>; 320193323Sed} 321193323Sed 322193323Sedmulticlass FU6_LU6_np<string OpcStr> { 323193323Sed def _u6: _FU6< 324193323Sed (outs), (ins i32imm:$b), 325193323Sed !strconcat(OpcStr, " $b"), 326193323Sed []>; 327193323Sed def _lu6: _FLU6< 328193323Sed (outs), (ins i32imm:$b), 329193323Sed !strconcat(OpcStr, " $b"), 330193323Sed []>; 331193323Sed} 332193323Sed 333193323Sed// U10 334193323Sedmulticlass FU10_LU10_np<string OpcStr> { 335193323Sed def _u10: _FU10< 336193323Sed (outs), (ins i32imm:$b), 337193323Sed !strconcat(OpcStr, " $b"), 338193323Sed []>; 339193323Sed def _lu10: _FLU10< 340193323Sed (outs), (ins i32imm:$b), 341193323Sed !strconcat(OpcStr, " $b"), 342193323Sed []>; 343193323Sed} 344193323Sed 345193323Sed// Two operand short 346193323Sed 347193323Sedclass F2R_np<string OpcStr> : _F2R< 348193323Sed (outs GRRegs:$dst), (ins GRRegs:$b), 349193323Sed !strconcat(OpcStr, " $dst, $b"), 350193323Sed []>; 351193323Sed 352193323Sed// Two operand long 353193323Sed 354193323Sed//===----------------------------------------------------------------------===// 355193323Sed// Pseudo Instructions 356193323Sed//===----------------------------------------------------------------------===// 357193323Sed 358193323Sedlet Defs = [SP], Uses = [SP] in { 359193323Seddef ADJCALLSTACKDOWN : PseudoInstXCore<(outs), (ins i32imm:$amt), 360193323Sed "${:comment} ADJCALLSTACKDOWN $amt", 361193323Sed [(callseq_start timm:$amt)]>; 362193323Seddef ADJCALLSTACKUP : PseudoInstXCore<(outs), (ins i32imm:$amt1, i32imm:$amt2), 363193323Sed "${:comment} ADJCALLSTACKUP $amt1", 364193323Sed [(callseq_end timm:$amt1, timm:$amt2)]>; 365193323Sed} 366193323Sed 367193323Seddef LDWFI : PseudoInstXCore<(outs GRRegs:$dst), (ins MEMii:$addr), 368193323Sed "${:comment} LDWFI $dst, $addr", 369193323Sed [(set GRRegs:$dst, (load ADDRspii:$addr))]>; 370193323Sed 371193323Seddef LDAWFI : PseudoInstXCore<(outs GRRegs:$dst), (ins MEMii:$addr), 372193323Sed "${:comment} LDAWFI $dst, $addr", 373193323Sed [(set GRRegs:$dst, ADDRspii:$addr)]>; 374193323Sed 375193323Seddef STWFI : PseudoInstXCore<(outs), (ins GRRegs:$src, MEMii:$addr), 376193323Sed "${:comment} STWFI $src, $addr", 377193323Sed [(store GRRegs:$src, ADDRspii:$addr)]>; 378193323Sed 379198892Srdivacky// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after 380198892Srdivacky// instruction selection into a branch sequence. 381198892Srdivackylet usesCustomInserter = 1 in { 382193323Sed def SELECT_CC : PseudoInstXCore<(outs GRRegs:$dst), 383193323Sed (ins GRRegs:$cond, GRRegs:$T, GRRegs:$F), 384193323Sed "${:comment} SELECT_CC PSEUDO!", 385193323Sed [(set GRRegs:$dst, 386193323Sed (select GRRegs:$cond, GRRegs:$T, GRRegs:$F))]>; 387193323Sed} 388193323Sed 389193323Sed//===----------------------------------------------------------------------===// 390193323Sed// Instructions 391193323Sed//===----------------------------------------------------------------------===// 392193323Sed 393193323Sed// Three operand short 394193323Seddefm ADD : F3R_2RUS<"add", add>; 395193323Seddefm SUB : F3R_2RUS<"sub", sub>; 396193323Sedlet neverHasSideEffects = 1 in { 397193323Seddefm EQ : F3R_2RUS_np<"eq">; 398193323Seddef LSS_3r : F3R_np<"lss">; 399193323Seddef LSU_3r : F3R_np<"lsu">; 400193323Sed} 401193323Seddef AND_3r : F3R<"and", and>; 402193323Seddef OR_3r : F3R<"or", or>; 403193323Sed 404193323Sedlet mayLoad=1 in { 405193323Seddef LDW_3r : _F3R<(outs GRRegs:$dst), (ins GRRegs:$addr, GRRegs:$offset), 406193323Sed "ldw $dst, $addr[$offset]", 407193323Sed []>; 408193323Sed 409193323Seddef LDW_2rus : _F2RUS<(outs GRRegs:$dst), (ins GRRegs:$addr, i32imm:$offset), 410193323Sed "ldw $dst, $addr[$offset]", 411193323Sed []>; 412193323Sed 413193323Seddef LD16S_3r : _F3R<(outs GRRegs:$dst), (ins GRRegs:$addr, GRRegs:$offset), 414193323Sed "ld16s $dst, $addr[$offset]", 415193323Sed []>; 416193323Sed 417193323Seddef LD8U_3r : _F3R<(outs GRRegs:$dst), (ins GRRegs:$addr, GRRegs:$offset), 418193323Sed "ld8u $dst, $addr[$offset]", 419193323Sed []>; 420193323Sed} 421193323Sed 422193323Sedlet mayStore=1 in { 423193323Seddef STW_3r : _F3R<(outs), (ins GRRegs:$val, GRRegs:$addr, GRRegs:$offset), 424193323Sed "stw $val, $addr[$offset]", 425193323Sed []>; 426193323Sed 427193323Seddef STW_2rus : _F2RUS<(outs), (ins GRRegs:$val, GRRegs:$addr, i32imm:$offset), 428193323Sed "stw $val, $addr[$offset]", 429193323Sed []>; 430193323Sed} 431193323Sed 432193323Seddefm SHL : F3R_2RBITP<"shl", shl>; 433193323Seddefm SHR : F3R_2RBITP<"shr", srl>; 434193323Sed// TODO tsetr 435193323Sed 436193323Sed// Three operand long 437193323Seddef LDAWF_l3r : _FL3R<(outs GRRegs:$dst), (ins GRRegs:$addr, GRRegs:$offset), 438193323Sed "ldaw $dst, $addr[$offset]", 439193323Sed [(set GRRegs:$dst, (ldawf GRRegs:$addr, GRRegs:$offset))]>; 440193323Sed 441193323Sedlet neverHasSideEffects = 1 in 442193323Seddef LDAWF_l2rus : _FL2RUS<(outs GRRegs:$dst), 443193323Sed (ins GRRegs:$addr, i32imm:$offset), 444193323Sed "ldaw $dst, $addr[$offset]", 445193323Sed []>; 446193323Sed 447193323Seddef LDAWB_l3r : _FL3R<(outs GRRegs:$dst), (ins GRRegs:$addr, GRRegs:$offset), 448193323Sed "ldaw $dst, $addr[-$offset]", 449193323Sed [(set GRRegs:$dst, (ldawb GRRegs:$addr, GRRegs:$offset))]>; 450193323Sed 451193323Sedlet neverHasSideEffects = 1 in 452193323Seddef LDAWB_l2rus : _FL2RUS<(outs GRRegs:$dst), 453193323Sed (ins GRRegs:$addr, i32imm:$offset), 454193323Sed "ldaw $dst, $addr[-$offset]", 455193323Sed []>; 456193323Sed 457193323Seddef LDA16F_l3r : _FL3R<(outs GRRegs:$dst), (ins GRRegs:$addr, GRRegs:$offset), 458193323Sed "lda16 $dst, $addr[$offset]", 459193323Sed [(set GRRegs:$dst, (lda16f GRRegs:$addr, GRRegs:$offset))]>; 460193323Sed 461193323Seddef LDA16B_l3r : _FL3R<(outs GRRegs:$dst), (ins GRRegs:$addr, GRRegs:$offset), 462193323Sed "lda16 $dst, $addr[-$offset]", 463193323Sed [(set GRRegs:$dst, (lda16b GRRegs:$addr, GRRegs:$offset))]>; 464193323Sed 465193323Seddef MUL_l3r : FL3R<"mul", mul>; 466193323Sed// Instructions which may trap are marked as side effecting. 467193323Sedlet hasSideEffects = 1 in { 468193323Seddef DIVS_l3r : FL3R<"divs", sdiv>; 469193323Seddef DIVU_l3r : FL3R<"divu", udiv>; 470193323Seddef REMS_l3r : FL3R<"rems", srem>; 471193323Seddef REMU_l3r : FL3R<"remu", urem>; 472193323Sed} 473193323Seddef XOR_l3r : FL3R<"xor", xor>; 474193323Seddefm ASHR : FL3R_L2RBITP<"ashr", sra>; 475193323Sed// TODO crc32, crc8, inpw, outpw 476193323Sedlet mayStore=1 in { 477193323Seddef ST16_l3r : _FL3R<(outs), (ins GRRegs:$val, GRRegs:$addr, GRRegs:$offset), 478193323Sed "st16 $val, $addr[$offset]", 479193323Sed []>; 480193323Sed 481193323Seddef ST8_l3r : _FL3R<(outs), (ins GRRegs:$val, GRRegs:$addr, GRRegs:$offset), 482193323Sed "st8 $val, $addr[$offset]", 483193323Sed []>; 484193323Sed} 485193323Sed 486193323Sed// Four operand long 487198090Srdivackylet Constraints = "$src1 = $dst1,$src2 = $dst2" in { 488193323Seddef MACCU_l4r : _L4R<(outs GRRegs:$dst1, GRRegs:$dst2), 489193323Sed (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3, 490193323Sed GRRegs:$src4), 491193323Sed "maccu $dst1, $dst2, $src3, $src4", 492193323Sed []>; 493193323Sed 494193323Seddef MACCS_l4r : _L4R<(outs GRRegs:$dst1, GRRegs:$dst2), 495193323Sed (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3, 496193323Sed GRRegs:$src4), 497193323Sed "maccs $dst1, $dst2, $src3, $src4", 498193323Sed []>; 499193323Sed} 500193323Sed 501193323Sed// Five operand long 502193323Sed 503193323Seddef LADD_l5r : _L5R<(outs GRRegs:$dst1, GRRegs:$dst2), 504193323Sed (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3), 505193323Sed "ladd $dst1, $dst2, $src1, $src2, $src3", 506193323Sed []>; 507193323Sed 508193323Seddef LSUB_l5r : _L5R<(outs GRRegs:$dst1, GRRegs:$dst2), 509193323Sed (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3), 510193323Sed "lsub $dst1, $dst2, $src1, $src2, $src3", 511193323Sed []>; 512193323Sed 513193323Seddef LDIV_l5r : _L5R<(outs GRRegs:$dst1, GRRegs:$dst2), 514193323Sed (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3), 515193323Sed "ldiv $dst1, $dst2, $src1, $src2, $src3", 516193323Sed []>; 517193323Sed 518193323Sed// Six operand long 519193323Sed 520193323Seddef LMUL_l6r : _L6R<(outs GRRegs:$dst1, GRRegs:$dst2), 521193323Sed (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3, 522193323Sed GRRegs:$src4), 523193323Sed "lmul $dst1, $dst2, $src1, $src2, $src3, $src4", 524193323Sed []>; 525193323Sed 526193323Sed// Register - U6 527193323Sed 528193323Sed//let Uses = [DP] in ... 529193323Sedlet neverHasSideEffects = 1, isReMaterializable = 1 in 530193323Seddef LDAWDP_ru6: _FRU6<(outs GRRegs:$dst), (ins MEMii:$a), 531193323Sed "ldaw $dst, dp[$a]", 532193323Sed []>; 533193323Sed 534193323Sedlet isReMaterializable = 1 in 535193323Seddef LDAWDP_lru6: _FLRU6< 536193323Sed (outs GRRegs:$dst), (ins MEMii:$a), 537193323Sed "ldaw $dst, dp[$a]", 538193323Sed [(set GRRegs:$dst, ADDRdpii:$a)]>; 539193323Sed 540193323Sedlet mayLoad=1 in 541193323Seddef LDWDP_ru6: _FRU6<(outs GRRegs:$dst), (ins MEMii:$a), 542193323Sed "ldw $dst, dp[$a]", 543193323Sed []>; 544193323Sed 545193323Seddef LDWDP_lru6: _FLRU6< 546193323Sed (outs GRRegs:$dst), (ins MEMii:$a), 547193323Sed "ldw $dst, dp[$a]", 548193323Sed [(set GRRegs:$dst, (load ADDRdpii:$a))]>; 549193323Sed 550193323Sedlet mayStore=1 in 551193323Seddef STWDP_ru6 : _FRU6<(outs), (ins GRRegs:$val, MEMii:$addr), 552193323Sed "stw $val, dp[$addr]", 553193323Sed []>; 554193323Sed 555193323Seddef STWDP_lru6 : _FLRU6<(outs), (ins GRRegs:$val, MEMii:$addr), 556193323Sed "stw $val, dp[$addr]", 557193323Sed [(store GRRegs:$val, ADDRdpii:$addr)]>; 558193323Sed 559193323Sed//let Uses = [CP] in .. 560193323Sedlet mayLoad = 1, isReMaterializable = 1 in 561193323Seddefm LDWCP : FRU6_LRU6_cp<"ldw">; 562193323Sed 563193323Sedlet Uses = [SP] in { 564193323Sedlet mayStore=1 in { 565193323Seddef STWSP_ru6 : _FRU6< 566193323Sed (outs), (ins GRRegs:$val, i32imm:$index), 567193323Sed "stw $val, sp[$index]", 568193323Sed [(XCoreStwsp GRRegs:$val, immU6:$index)]>; 569193323Sed 570193323Seddef STWSP_lru6 : _FLRU6< 571193323Sed (outs), (ins GRRegs:$val, i32imm:$index), 572193323Sed "stw $val, sp[$index]", 573193323Sed [(XCoreStwsp GRRegs:$val, immU16:$index)]>; 574193323Sed} 575193323Sed 576193323Sedlet mayLoad=1 in { 577193323Seddef LDWSP_ru6 : _FRU6< 578193323Sed (outs GRRegs:$dst), (ins i32imm:$b), 579193323Sed "ldw $dst, sp[$b]", 580193323Sed []>; 581193323Sed 582193323Seddef LDWSP_lru6 : _FLRU6< 583193323Sed (outs GRRegs:$dst), (ins i32imm:$b), 584193323Sed "ldw $dst, sp[$b]", 585193323Sed []>; 586193323Sed} 587193323Sed 588193323Sedlet neverHasSideEffects = 1 in { 589193323Seddef LDAWSP_ru6 : _FRU6< 590193323Sed (outs GRRegs:$dst), (ins i32imm:$b), 591193323Sed "ldaw $dst, sp[$b]", 592193323Sed []>; 593193323Sed 594193323Seddef LDAWSP_lru6 : _FLRU6< 595193323Sed (outs GRRegs:$dst), (ins i32imm:$b), 596193323Sed "ldaw $dst, sp[$b]", 597193323Sed []>; 598193323Sed 599193323Seddef LDAWSP_ru6_RRegs : _FRU6< 600193323Sed (outs RRegs:$dst), (ins i32imm:$b), 601193323Sed "ldaw $dst, sp[$b]", 602193323Sed []>; 603193323Sed 604193323Seddef LDAWSP_lru6_RRegs : _FLRU6< 605193323Sed (outs RRegs:$dst), (ins i32imm:$b), 606193323Sed "ldaw $dst, sp[$b]", 607193323Sed []>; 608193323Sed} 609193323Sed} 610193323Sed 611193323Sedlet isReMaterializable = 1 in { 612193323Seddef LDC_ru6 : _FRU6< 613193323Sed (outs GRRegs:$dst), (ins i32imm:$b), 614193323Sed "ldc $dst, $b", 615193323Sed [(set GRRegs:$dst, immU6:$b)]>; 616193323Sed 617193323Seddef LDC_lru6 : _FLRU6< 618193323Sed (outs GRRegs:$dst), (ins i32imm:$b), 619193323Sed "ldc $dst, $b", 620193323Sed [(set GRRegs:$dst, immU16:$b)]>; 621193323Sed} 622193323Sed 623193323Sed// Operand register - U6 624193323Sed// TODO setc 625193323Sedlet isBranch = 1, isTerminator = 1 in { 626193323Seddefm BRFT: FRU6_LRU6_branch<"bt">; 627193323Seddefm BRBT: FRU6_LRU6_branch<"bt">; 628193323Seddefm BRFF: FRU6_LRU6_branch<"bf">; 629193323Seddefm BRBF: FRU6_LRU6_branch<"bf">; 630193323Sed} 631193323Sed 632193323Sed// U6 633193323Sedlet Defs = [SP], Uses = [SP] in { 634193323Sedlet neverHasSideEffects = 1 in 635193323Seddefm EXTSP : FU6_LU6_np<"extsp">; 636193323Sedlet mayStore = 1 in 637193323Seddefm ENTSP : FU6_LU6_np<"entsp">; 638193323Sed 639199481Srdivackylet isReturn = 1, isTerminator = 1, mayLoad = 1, isBarrier = 1 in { 640193323Seddefm RETSP : FU6_LU6<"retsp", XCoreRetsp>; 641193323Sed} 642193323Sed} 643193323Sed 644193323Sed// TODO extdp, kentsp, krestsp, blat, setsr 645193323Sed// clrsr, getsr, kalli 646204642Srdivackylet isBranch = 1, isTerminator = 1, isBarrier = 1 in { 647193323Seddef BRBU_u6 : _FU6< 648193323Sed (outs), 649193323Sed (ins brtarget:$target), 650193323Sed "bu $target", 651193323Sed []>; 652193323Sed 653193323Seddef BRBU_lu6 : _FLU6< 654193323Sed (outs), 655193323Sed (ins brtarget:$target), 656193323Sed "bu $target", 657193323Sed []>; 658193323Sed 659193323Seddef BRFU_u6 : _FU6< 660193323Sed (outs), 661193323Sed (ins brtarget:$target), 662193323Sed "bu $target", 663193323Sed []>; 664193323Sed 665193323Seddef BRFU_lu6 : _FLU6< 666193323Sed (outs), 667193323Sed (ins brtarget:$target), 668193323Sed "bu $target", 669193323Sed []>; 670193323Sed} 671193323Sed 672193323Sed//let Uses = [CP] in ... 673198090Srdivackylet Defs = [R11], neverHasSideEffects = 1, isReMaterializable = 1 in 674193323Seddef LDAWCP_u6: _FRU6<(outs), (ins MEMii:$a), 675193323Sed "ldaw r11, cp[$a]", 676193323Sed []>; 677193323Sed 678198090Srdivackylet Defs = [R11], isReMaterializable = 1 in 679193323Seddef LDAWCP_lu6: _FLRU6< 680193323Sed (outs), (ins MEMii:$a), 681193323Sed "ldaw r11, cp[$a]", 682193323Sed [(set R11, ADDRcpii:$a)]>; 683193323Sed 684193323Sed// U10 685193323Sed// TODO ldwcpl, blacp 686193323Sed 687193323Sedlet Defs = [R11], isReMaterializable = 1, neverHasSideEffects = 1 in 688193323Seddef LDAP_u10 : _FU10< 689193323Sed (outs), 690193323Sed (ins i32imm:$addr), 691193323Sed "ldap r11, $addr", 692193323Sed []>; 693193323Sed 694193323Sedlet Defs = [R11], isReMaterializable = 1 in 695193323Seddef LDAP_lu10 : _FLU10< 696193323Sed (outs), 697193323Sed (ins i32imm:$addr), 698193323Sed "ldap r11, $addr", 699193323Sed [(set R11, (pcrelwrapper tglobaladdr:$addr))]>; 700193323Sed 701199511Srdivackylet Defs = [R11], isReMaterializable = 1 in 702199511Srdivackydef LDAP_lu10_ba : _FLU10<(outs), 703199511Srdivacky (ins i32imm:$addr), 704199511Srdivacky "ldap r11, $addr", 705199511Srdivacky [(set R11, (pcrelwrapper tblockaddress:$addr))]>; 706199511Srdivacky 707193323Sedlet isCall=1, 708203954Srdivacky// All calls clobber the link register and the non-callee-saved registers: 709193323SedDefs = [R0, R1, R2, R3, R11, LR] in { 710193323Seddef BL_u10 : _FU10< 711193323Sed (outs), 712193323Sed (ins calltarget:$target, variable_ops), 713193323Sed "bl $target", 714193323Sed [(XCoreBranchLink immU10:$target)]>; 715193323Sed 716193323Seddef BL_lu10 : _FLU10< 717193323Sed (outs), 718193323Sed (ins calltarget:$target, variable_ops), 719193323Sed "bl $target", 720193323Sed [(XCoreBranchLink immU20:$target)]>; 721193323Sed} 722193323Sed 723193323Sed// Two operand short 724193323Sed// TODO getr, getst 725193323Seddef NOT : _F2R<(outs GRRegs:$dst), (ins GRRegs:$b), 726193323Sed "not $dst, $b", 727193323Sed [(set GRRegs:$dst, (not GRRegs:$b))]>; 728193323Sed 729193323Seddef NEG : _F2R<(outs GRRegs:$dst), (ins GRRegs:$b), 730193323Sed "neg $dst, $b", 731193323Sed [(set GRRegs:$dst, (ineg GRRegs:$b))]>; 732193323Sed 733193323Sed// TODO setd, eet, eef, getts, setpt, outct, inct, chkct, outt, intt, out, 734193323Sed// in, outshr, inshr, testct, testwct, tinitpc, tinitdp, tinitsp, tinitcp, 735193323Sed// tsetmr, sext (reg), zext (reg) 736210299Sedlet Constraints = "$src1 = $dst" in { 737193323Sedlet neverHasSideEffects = 1 in 738193323Seddef SEXT_rus : _FRUS<(outs GRRegs:$dst), (ins GRRegs:$src1, i32imm:$src2), 739193323Sed "sext $dst, $src2", 740193323Sed []>; 741193323Sed 742193323Sedlet neverHasSideEffects = 1 in 743193323Seddef ZEXT_rus : _FRUS<(outs GRRegs:$dst), (ins GRRegs:$src1, i32imm:$src2), 744193323Sed "zext $dst, $src2", 745193323Sed []>; 746193323Sed 747193323Seddef ANDNOT_2r : _F2R<(outs GRRegs:$dst), (ins GRRegs:$src1, GRRegs:$src2), 748193323Sed "andnot $dst, $src2", 749193323Sed [(set GRRegs:$dst, (and GRRegs:$src1, (not GRRegs:$src2)))]>; 750193323Sed} 751193323Sed 752193323Sedlet isReMaterializable = 1, neverHasSideEffects = 1 in 753193323Seddef MKMSK_rus : _FRUS<(outs GRRegs:$dst), (ins i32imm:$size), 754193323Sed "mkmsk $dst, $size", 755193323Sed []>; 756193323Sed 757193323Seddef MKMSK_2r : _FRUS<(outs GRRegs:$dst), (ins GRRegs:$size), 758193323Sed "mkmsk $dst, $size", 759193323Sed [(set GRRegs:$dst, (add (shl 1, GRRegs:$size), 0xffffffff))]>; 760193323Sed 761193323Sed// Two operand long 762193323Sed// TODO settw, setclk, setrdy, setpsc, endin, peek, 763193323Sed// getd, testlcl, tinitlr, getps, setps 764193323Seddef BITREV_l2r : _FL2R<(outs GRRegs:$dst), (ins GRRegs:$src), 765193323Sed "bitrev $dst, $src", 766193323Sed [(set GRRegs:$dst, (int_xcore_bitrev GRRegs:$src))]>; 767193323Sed 768193323Seddef BYTEREV_l2r : _FL2R<(outs GRRegs:$dst), (ins GRRegs:$src), 769193323Sed "byterev $dst, $src", 770193323Sed [(set GRRegs:$dst, (bswap GRRegs:$src))]>; 771193323Sed 772193323Seddef CLZ_l2r : _FL2R<(outs GRRegs:$dst), (ins GRRegs:$src), 773193323Sed "clz $dst, $src", 774193323Sed [(set GRRegs:$dst, (ctlz GRRegs:$src))]>; 775193323Sed 776193323Sed// One operand short 777193323Sed// TODO edu, eeu, waitet, waitef, freer, tstart, msync, mjoin, syncr, clrtp 778204642Srdivacky// setdp, setcp, setv, setev, kcall 779193323Sed// dgetreg 780204642Srdivackylet isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in 781193323Seddef BAU_1r : _F1R<(outs), (ins GRRegs:$addr), 782193323Sed "bau $addr", 783193323Sed [(brind GRRegs:$addr)]>; 784193323Sed 785204642Srdivackylet isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in 786204642Srdivackydef BR_JT : PseudoInstXCore<(outs), (ins InlineJT:$t, GRRegs:$i), 787204642Srdivacky "bru $i\n$t", 788204642Srdivacky [(XCoreBR_JT tjumptable:$t, GRRegs:$i)]>; 789204642Srdivacky 790204642Srdivackylet isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in 791204642Srdivackydef BR_JT32 : PseudoInstXCore<(outs), (ins InlineJT32:$t, GRRegs:$i), 792204642Srdivacky "bru $i\n$t", 793204642Srdivacky [(XCoreBR_JT32 tjumptable:$t, GRRegs:$i)]>; 794204642Srdivacky 795193323Sedlet Defs=[SP], neverHasSideEffects=1 in 796193323Seddef SETSP_1r : _F1R<(outs), (ins GRRegs:$src), 797193323Sed "set sp, $src", 798193323Sed []>; 799193323Sed 800204642Srdivackylet hasCtrlDep = 1 in 801193323Seddef ECALLT_1r : _F1R<(outs), (ins GRRegs:$src), 802193323Sed "ecallt $src", 803193323Sed []>; 804193323Sed 805204642Srdivackylet hasCtrlDep = 1 in 806193323Seddef ECALLF_1r : _F1R<(outs), (ins GRRegs:$src), 807193323Sed "ecallf $src", 808193323Sed []>; 809193323Sed 810193323Sedlet isCall=1, 811203954Srdivacky// All calls clobber the link register and the non-callee-saved registers: 812193323SedDefs = [R0, R1, R2, R3, R11, LR] in { 813193323Seddef BLA_1r : _F1R<(outs), (ins GRRegs:$addr, variable_ops), 814193323Sed "bla $addr", 815193323Sed [(XCoreBranchLink GRRegs:$addr)]>; 816193323Sed} 817193323Sed 818193323Sed// Zero operand short 819193323Sed// TODO waiteu, clre, ssync, freet, ldspc, stspc, ldssr, stssr, ldsed, stsed, 820193323Sed// stet, geted, getet, getkep, getksp, setkep, getid, kret, dcall, dret, 821193323Sed// dentsp, drestsp 822193323Sed 823193323Sedlet Defs = [R11] in 824193323Seddef GETID_0R : _F0R<(outs), (ins), 825193323Sed "get r11, id", 826193323Sed [(set R11, (int_xcore_getid))]>; 827193323Sed 828193323Sed//===----------------------------------------------------------------------===// 829193323Sed// Non-Instruction Patterns 830193323Sed//===----------------------------------------------------------------------===// 831193323Sed 832193323Seddef : Pat<(XCoreBranchLink tglobaladdr:$addr), (BL_lu10 tglobaladdr:$addr)>; 833193323Seddef : Pat<(XCoreBranchLink texternalsym:$addr), (BL_lu10 texternalsym:$addr)>; 834193323Sed 835193323Sed/// sext_inreg 836193323Seddef : Pat<(sext_inreg GRRegs:$b, i1), (SEXT_rus GRRegs:$b, 1)>; 837193323Seddef : Pat<(sext_inreg GRRegs:$b, i8), (SEXT_rus GRRegs:$b, 8)>; 838193323Seddef : Pat<(sext_inreg GRRegs:$b, i16), (SEXT_rus GRRegs:$b, 16)>; 839193323Sed 840193323Sed/// loads 841193323Seddef : Pat<(zextloadi8 (add GRRegs:$addr, GRRegs:$offset)), 842193323Sed (LD8U_3r GRRegs:$addr, GRRegs:$offset)>; 843193323Seddef : Pat<(zextloadi8 GRRegs:$addr), (LD8U_3r GRRegs:$addr, (LDC_ru6 0))>; 844193323Sed 845198090Srdivackydef : Pat<(sextloadi16 (lda16f GRRegs:$addr, GRRegs:$offset)), 846193323Sed (LD16S_3r GRRegs:$addr, GRRegs:$offset)>; 847193323Seddef : Pat<(sextloadi16 GRRegs:$addr), (LD16S_3r GRRegs:$addr, (LDC_ru6 0))>; 848193323Sed 849193323Seddef : Pat<(load (ldawf GRRegs:$addr, GRRegs:$offset)), 850193323Sed (LDW_3r GRRegs:$addr, GRRegs:$offset)>; 851193323Seddef : Pat<(load (add GRRegs:$addr, immUs4:$offset)), 852193323Sed (LDW_2rus GRRegs:$addr, (div4_xform immUs4:$offset))>; 853193323Seddef : Pat<(load GRRegs:$addr), (LDW_2rus GRRegs:$addr, 0)>; 854193323Sed 855193323Sed/// anyext 856193323Seddef : Pat<(extloadi8 (add GRRegs:$addr, GRRegs:$offset)), 857193323Sed (LD8U_3r GRRegs:$addr, GRRegs:$offset)>; 858193323Seddef : Pat<(extloadi8 GRRegs:$addr), (LD8U_3r GRRegs:$addr, (LDC_ru6 0))>; 859193323Seddef : Pat<(extloadi16 (lda16f GRRegs:$addr, GRRegs:$offset)), 860193323Sed (LD16S_3r GRRegs:$addr, GRRegs:$offset)>; 861193323Seddef : Pat<(extloadi16 GRRegs:$addr), (LD16S_3r GRRegs:$addr, (LDC_ru6 0))>; 862193323Sed 863193323Sed/// stores 864193323Seddef : Pat<(truncstorei8 GRRegs:$val, (add GRRegs:$addr, GRRegs:$offset)), 865193323Sed (ST8_l3r GRRegs:$val, GRRegs:$addr, GRRegs:$offset)>; 866193323Seddef : Pat<(truncstorei8 GRRegs:$val, GRRegs:$addr), 867193323Sed (ST8_l3r GRRegs:$val, GRRegs:$addr, (LDC_ru6 0))>; 868193323Sed 869193323Seddef : Pat<(truncstorei16 GRRegs:$val, (lda16f GRRegs:$addr, GRRegs:$offset)), 870193323Sed (ST16_l3r GRRegs:$val, GRRegs:$addr, GRRegs:$offset)>; 871193323Seddef : Pat<(truncstorei16 GRRegs:$val, GRRegs:$addr), 872193323Sed (ST16_l3r GRRegs:$val, GRRegs:$addr, (LDC_ru6 0))>; 873193323Sed 874193323Seddef : Pat<(store GRRegs:$val, (ldawf GRRegs:$addr, GRRegs:$offset)), 875193323Sed (STW_3r GRRegs:$val, GRRegs:$addr, GRRegs:$offset)>; 876193323Seddef : Pat<(store GRRegs:$val, (add GRRegs:$addr, immUs4:$offset)), 877193323Sed (STW_2rus GRRegs:$val, GRRegs:$addr, (div4_xform immUs4:$offset))>; 878193323Seddef : Pat<(store GRRegs:$val, GRRegs:$addr), 879193323Sed (STW_2rus GRRegs:$val, GRRegs:$addr, 0)>; 880193323Sed 881193323Sed/// cttz 882193323Seddef : Pat<(cttz GRRegs:$src), (CLZ_l2r (BITREV_l2r GRRegs:$src))>; 883193323Sed 884193323Sed/// trap 885193323Seddef : Pat<(trap), (ECALLF_1r (LDC_ru6 0))>; 886193323Sed 887193323Sed/// 888193323Sed/// branch patterns 889193323Sed/// 890193323Sed 891193323Sed// unconditional branch 892193323Seddef : Pat<(br bb:$addr), (BRFU_lu6 bb:$addr)>; 893193323Sed 894193323Sed// direct match equal/notequal zero brcond 895193323Seddef : Pat<(brcond (setne GRRegs:$lhs, 0), bb:$dst), 896193323Sed (BRFT_lru6 GRRegs:$lhs, bb:$dst)>; 897193323Seddef : Pat<(brcond (seteq GRRegs:$lhs, 0), bb:$dst), 898193323Sed (BRFF_lru6 GRRegs:$lhs, bb:$dst)>; 899193323Sed 900193323Seddef : Pat<(brcond (setle GRRegs:$lhs, GRRegs:$rhs), bb:$dst), 901193323Sed (BRFF_lru6 (LSS_3r GRRegs:$rhs, GRRegs:$lhs), bb:$dst)>; 902193323Seddef : Pat<(brcond (setule GRRegs:$lhs, GRRegs:$rhs), bb:$dst), 903193323Sed (BRFF_lru6 (LSU_3r GRRegs:$rhs, GRRegs:$lhs), bb:$dst)>; 904193323Seddef : Pat<(brcond (setge GRRegs:$lhs, GRRegs:$rhs), bb:$dst), 905193323Sed (BRFF_lru6 (LSS_3r GRRegs:$lhs, GRRegs:$rhs), bb:$dst)>; 906193323Seddef : Pat<(brcond (setuge GRRegs:$lhs, GRRegs:$rhs), bb:$dst), 907193323Sed (BRFF_lru6 (LSU_3r GRRegs:$lhs, GRRegs:$rhs), bb:$dst)>; 908193323Seddef : Pat<(brcond (setne GRRegs:$lhs, GRRegs:$rhs), bb:$dst), 909193323Sed (BRFF_lru6 (EQ_3r GRRegs:$lhs, GRRegs:$rhs), bb:$dst)>; 910193323Seddef : Pat<(brcond (setne GRRegs:$lhs, immUs:$rhs), bb:$dst), 911193323Sed (BRFF_lru6 (EQ_2rus GRRegs:$lhs, immUs:$rhs), bb:$dst)>; 912193323Sed 913193323Sed// generic brcond pattern 914193323Seddef : Pat<(brcond GRRegs:$cond, bb:$addr), (BRFT_lru6 GRRegs:$cond, bb:$addr)>; 915193323Sed 916193323Sed 917193323Sed/// 918193323Sed/// Select patterns 919193323Sed/// 920193323Sed 921193323Sed// direct match equal/notequal zero select 922193323Seddef : Pat<(select (setne GRRegs:$lhs, 0), GRRegs:$T, GRRegs:$F), 923193323Sed (SELECT_CC GRRegs:$lhs, GRRegs:$T, GRRegs:$F)>; 924193323Sed 925193323Seddef : Pat<(select (seteq GRRegs:$lhs, 0), GRRegs:$T, GRRegs:$F), 926193323Sed (SELECT_CC GRRegs:$lhs, GRRegs:$F, GRRegs:$T)>; 927193323Sed 928193323Seddef : Pat<(select (setle GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F), 929193323Sed (SELECT_CC (LSS_3r GRRegs:$rhs, GRRegs:$lhs), GRRegs:$F, GRRegs:$T)>; 930193323Seddef : Pat<(select (setule GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F), 931193323Sed (SELECT_CC (LSU_3r GRRegs:$rhs, GRRegs:$lhs), GRRegs:$F, GRRegs:$T)>; 932193323Seddef : Pat<(select (setge GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F), 933193323Sed (SELECT_CC (LSS_3r GRRegs:$lhs, GRRegs:$rhs), GRRegs:$F, GRRegs:$T)>; 934193323Seddef : Pat<(select (setuge GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F), 935193323Sed (SELECT_CC (LSU_3r GRRegs:$lhs, GRRegs:$rhs), GRRegs:$F, GRRegs:$T)>; 936193323Seddef : Pat<(select (setne GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F), 937193323Sed (SELECT_CC (EQ_3r GRRegs:$lhs, GRRegs:$rhs), GRRegs:$F, GRRegs:$T)>; 938193323Seddef : Pat<(select (setne GRRegs:$lhs, immUs:$rhs), GRRegs:$T, GRRegs:$F), 939193323Sed (SELECT_CC (EQ_2rus GRRegs:$lhs, immUs:$rhs), GRRegs:$F, GRRegs:$T)>; 940193323Sed 941193323Sed/// 942193323Sed/// setcc patterns, only matched when none of the above brcond 943193323Sed/// patterns match 944193323Sed/// 945193323Sed 946193323Sed// setcc 2 register operands 947193323Seddef : Pat<(setle GRRegs:$lhs, GRRegs:$rhs), 948193323Sed (EQ_2rus (LSS_3r GRRegs:$rhs, GRRegs:$lhs), 0)>; 949193323Seddef : Pat<(setule GRRegs:$lhs, GRRegs:$rhs), 950193323Sed (EQ_2rus (LSU_3r GRRegs:$rhs, GRRegs:$lhs), 0)>; 951193323Sed 952193323Seddef : Pat<(setgt GRRegs:$lhs, GRRegs:$rhs), 953193323Sed (LSS_3r GRRegs:$rhs, GRRegs:$lhs)>; 954193323Seddef : Pat<(setugt GRRegs:$lhs, GRRegs:$rhs), 955193323Sed (LSU_3r GRRegs:$rhs, GRRegs:$lhs)>; 956193323Sed 957193323Seddef : Pat<(setge GRRegs:$lhs, GRRegs:$rhs), 958193323Sed (EQ_2rus (LSS_3r GRRegs:$lhs, GRRegs:$rhs), 0)>; 959193323Seddef : Pat<(setuge GRRegs:$lhs, GRRegs:$rhs), 960193323Sed (EQ_2rus (LSU_3r GRRegs:$lhs, GRRegs:$rhs), 0)>; 961193323Sed 962193323Seddef : Pat<(setlt GRRegs:$lhs, GRRegs:$rhs), 963193323Sed (LSS_3r GRRegs:$lhs, GRRegs:$rhs)>; 964193323Seddef : Pat<(setult GRRegs:$lhs, GRRegs:$rhs), 965193323Sed (LSU_3r GRRegs:$lhs, GRRegs:$rhs)>; 966193323Sed 967193323Seddef : Pat<(setne GRRegs:$lhs, GRRegs:$rhs), 968193323Sed (EQ_2rus (EQ_3r GRRegs:$lhs, GRRegs:$rhs), 0)>; 969193323Sed 970193323Seddef : Pat<(seteq GRRegs:$lhs, GRRegs:$rhs), 971193323Sed (EQ_3r GRRegs:$lhs, GRRegs:$rhs)>; 972193323Sed 973193323Sed// setcc reg/imm operands 974193323Seddef : Pat<(seteq GRRegs:$lhs, immUs:$rhs), 975193323Sed (EQ_2rus GRRegs:$lhs, immUs:$rhs)>; 976193323Seddef : Pat<(setne GRRegs:$lhs, immUs:$rhs), 977193323Sed (EQ_2rus (EQ_2rus GRRegs:$lhs, immUs:$rhs), 0)>; 978193323Sed 979193323Sed// misc 980193323Seddef : Pat<(add GRRegs:$addr, immUs4:$offset), 981193323Sed (LDAWF_l2rus GRRegs:$addr, (div4_xform immUs4:$offset))>; 982193323Sed 983193323Seddef : Pat<(sub GRRegs:$addr, immUs4:$offset), 984193323Sed (LDAWB_l2rus GRRegs:$addr, (div4_xform immUs4:$offset))>; 985193323Sed 986193323Seddef : Pat<(and GRRegs:$val, immMskBitp:$mask), 987193323Sed (ZEXT_rus GRRegs:$val, (msksize_xform immMskBitp:$mask))>; 988193323Sed 989193323Sed// (sub X, imm) gets canonicalized to (add X, -imm). Match this form. 990193323Seddef : Pat<(add GRRegs:$src1, immUsNeg:$src2), 991193323Sed (SUB_2rus GRRegs:$src1, (neg_xform immUsNeg:$src2))>; 992193323Sed 993193323Seddef : Pat<(add GRRegs:$src1, immUs4Neg:$src2), 994193323Sed (LDAWB_l2rus GRRegs:$src1, (div4neg_xform immUs4Neg:$src2))>; 995193323Sed 996193323Sed/// 997193323Sed/// Some peepholes 998193323Sed/// 999193323Sed 1000193323Seddef : Pat<(mul GRRegs:$src, 3), 1001193323Sed (LDA16F_l3r GRRegs:$src, GRRegs:$src)>; 1002193323Sed 1003193323Seddef : Pat<(mul GRRegs:$src, 5), 1004193323Sed (LDAWF_l3r GRRegs:$src, GRRegs:$src)>; 1005193323Sed 1006193323Seddef : Pat<(mul GRRegs:$src, -3), 1007193323Sed (LDAWB_l3r GRRegs:$src, GRRegs:$src)>; 1008193323Sed 1009193323Sed// ashr X, 32 is equivalent to ashr X, 31 on the XCore. 1010193323Seddef : Pat<(sra GRRegs:$src, 31), 1011193323Sed (ASHR_l2rus GRRegs:$src, 32)>; 1012193323Sed 1013198090Srdivackydef : Pat<(brcond (setlt GRRegs:$lhs, 0), bb:$dst), 1014198090Srdivacky (BRFT_lru6 (ASHR_l2rus GRRegs:$lhs, 32), bb:$dst)>; 1015198090Srdivacky 1016198090Srdivacky// setge X, 0 is canonicalized to setgt X, -1 1017198090Srdivackydef : Pat<(brcond (setgt GRRegs:$lhs, -1), bb:$dst), 1018198090Srdivacky (BRFF_lru6 (ASHR_l2rus GRRegs:$lhs, 32), bb:$dst)>; 1019198090Srdivacky 1020198090Srdivackydef : Pat<(select (setlt GRRegs:$lhs, 0), GRRegs:$T, GRRegs:$F), 1021198090Srdivacky (SELECT_CC (ASHR_l2rus GRRegs:$lhs, 32), GRRegs:$T, GRRegs:$F)>; 1022198090Srdivacky 1023198090Srdivackydef : Pat<(select (setgt GRRegs:$lhs, -1), GRRegs:$T, GRRegs:$F), 1024198090Srdivacky (SELECT_CC (ASHR_l2rus GRRegs:$lhs, 32), GRRegs:$F, GRRegs:$T)>; 1025198090Srdivacky 1026198090Srdivackydef : Pat<(setgt GRRegs:$lhs, -1), 1027198090Srdivacky (EQ_2rus (ASHR_l2rus GRRegs:$lhs, 32), 0)>; 1028198090Srdivacky 1029198090Srdivackydef : Pat<(sra (shl GRRegs:$src, immBpwSubBitp:$imm), immBpwSubBitp:$imm), 1030198090Srdivacky (SEXT_rus GRRegs:$src, (bpwsub_xform immBpwSubBitp:$imm))>; 1031