XCoreInstrInfo.td revision 203954
1193323Sed//===- XCoreInstrInfo.td - Target Description for XCore ----*- tablegen -*-===// 2193323Sed// 3193323Sed// The LLVM Compiler Infrastructure 4193323Sed// 5193323Sed// This file is distributed under the University of Illinois Open Source 6193323Sed// License. See LICENSE.TXT for details. 7193323Sed// 8193323Sed//===----------------------------------------------------------------------===// 9193323Sed// 10193323Sed// This file describes the XCore instructions in TableGen format. 11193323Sed// 12193323Sed//===----------------------------------------------------------------------===// 13193323Sed 14193323Sed// Uses of CP, DP are not currently reflected in the patterns, since 15193323Sed// having a physical register as an operand prevents loop hoisting and 16193323Sed// since the value of these registers never changes during the life of the 17193323Sed// function. 18193323Sed 19193323Sed//===----------------------------------------------------------------------===// 20193323Sed// Instruction format superclass. 21193323Sed//===----------------------------------------------------------------------===// 22193323Sed 23193323Sedinclude "XCoreInstrFormats.td" 24193323Sed 25193323Sed//===----------------------------------------------------------------------===// 26193323Sed// XCore specific DAG Nodes. 27193323Sed// 28193323Sed 29193323Sed// Call 30193323Seddef SDT_XCoreBranchLink : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>; 31193323Seddef XCoreBranchLink : SDNode<"XCoreISD::BL",SDT_XCoreBranchLink, 32193323Sed [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>; 33193323Sed 34193323Seddef XCoreRetsp : SDNode<"XCoreISD::RETSP", SDTNone, 35193323Sed [SDNPHasChain, SDNPOptInFlag]>; 36193323Sed 37193323Seddef SDT_XCoreAddress : SDTypeProfile<1, 1, 38193323Sed [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>; 39193323Sed 40193323Seddef pcrelwrapper : SDNode<"XCoreISD::PCRelativeWrapper", SDT_XCoreAddress, 41193323Sed []>; 42193323Sed 43193323Seddef dprelwrapper : SDNode<"XCoreISD::DPRelativeWrapper", SDT_XCoreAddress, 44193323Sed []>; 45193323Sed 46193323Seddef cprelwrapper : SDNode<"XCoreISD::CPRelativeWrapper", SDT_XCoreAddress, 47193323Sed []>; 48193323Sed 49193323Seddef SDT_XCoreStwsp : SDTypeProfile<0, 2, [SDTCisInt<1>]>; 50193323Seddef XCoreStwsp : SDNode<"XCoreISD::STWSP", SDT_XCoreStwsp, 51193323Sed [SDNPHasChain]>; 52193323Sed 53193323Sed// These are target-independent nodes, but have target-specific formats. 54193323Seddef SDT_XCoreCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>; 55193323Seddef SDT_XCoreCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, 56193323Sed SDTCisVT<1, i32> ]>; 57193323Sed 58193323Seddef callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_XCoreCallSeqStart, 59193323Sed [SDNPHasChain, SDNPOutFlag]>; 60193323Seddef callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_XCoreCallSeqEnd, 61193323Sed [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>; 62193323Sed 63193323Sed//===----------------------------------------------------------------------===// 64193323Sed// Instruction Pattern Stuff 65193323Sed//===----------------------------------------------------------------------===// 66193323Sed 67193323Seddef div4_xform : SDNodeXForm<imm, [{ 68193323Sed // Transformation function: imm/4 69193323Sed assert(N->getZExtValue() % 4 == 0); 70193323Sed return getI32Imm(N->getZExtValue()/4); 71193323Sed}]>; 72193323Sed 73193323Seddef msksize_xform : SDNodeXForm<imm, [{ 74193323Sed // Transformation function: get the size of a mask 75193323Sed assert(isMask_32(N->getZExtValue())); 76193323Sed // look for the first non-zero bit 77193323Sed return getI32Imm(32 - CountLeadingZeros_32(N->getZExtValue())); 78193323Sed}]>; 79193323Sed 80193323Seddef neg_xform : SDNodeXForm<imm, [{ 81193323Sed // Transformation function: -imm 82193323Sed uint32_t value = N->getZExtValue(); 83193323Sed return getI32Imm(-value); 84193323Sed}]>; 85193323Sed 86198090Srdivackydef bpwsub_xform : SDNodeXForm<imm, [{ 87198090Srdivacky // Transformation function: 32-imm 88198090Srdivacky uint32_t value = N->getZExtValue(); 89198090Srdivacky return getI32Imm(32-value); 90198090Srdivacky}]>; 91198090Srdivacky 92193323Seddef div4neg_xform : SDNodeXForm<imm, [{ 93193323Sed // Transformation function: -imm/4 94193323Sed uint32_t value = N->getZExtValue(); 95193323Sed assert(-value % 4 == 0); 96193323Sed return getI32Imm(-value/4); 97193323Sed}]>; 98193323Sed 99193323Seddef immUs4Neg : PatLeaf<(imm), [{ 100193323Sed uint32_t value = (uint32_t)N->getZExtValue(); 101193323Sed return (-value)%4 == 0 && (-value)/4 <= 11; 102193323Sed}]>; 103193323Sed 104193323Seddef immUs4 : PatLeaf<(imm), [{ 105193323Sed uint32_t value = (uint32_t)N->getZExtValue(); 106193323Sed return value%4 == 0 && value/4 <= 11; 107193323Sed}]>; 108193323Sed 109193323Seddef immUsNeg : PatLeaf<(imm), [{ 110193323Sed return -((uint32_t)N->getZExtValue()) <= 11; 111193323Sed}]>; 112193323Sed 113193323Seddef immUs : PatLeaf<(imm), [{ 114193323Sed return (uint32_t)N->getZExtValue() <= 11; 115193323Sed}]>; 116193323Sed 117193323Seddef immU6 : PatLeaf<(imm), [{ 118193323Sed return (uint32_t)N->getZExtValue() < (1 << 6); 119193323Sed}]>; 120193323Sed 121193323Seddef immU10 : PatLeaf<(imm), [{ 122193323Sed return (uint32_t)N->getZExtValue() < (1 << 10); 123193323Sed}]>; 124193323Sed 125193323Seddef immU16 : PatLeaf<(imm), [{ 126193323Sed return (uint32_t)N->getZExtValue() < (1 << 16); 127193323Sed}]>; 128193323Sed 129193323Seddef immU20 : PatLeaf<(imm), [{ 130193323Sed return (uint32_t)N->getZExtValue() < (1 << 20); 131193323Sed}]>; 132193323Sed 133193323Seddef immMskBitp : PatLeaf<(imm), [{ 134193323Sed uint32_t value = (uint32_t)N->getZExtValue(); 135193323Sed if (!isMask_32(value)) { 136193323Sed return false; 137193323Sed } 138193323Sed int msksize = 32 - CountLeadingZeros_32(value); 139193323Sed return (msksize >= 1 && msksize <= 8) 140193323Sed || msksize == 16 141193323Sed || msksize == 24 142193323Sed || msksize == 32; 143193323Sed}]>; 144193323Sed 145193323Seddef immBitp : PatLeaf<(imm), [{ 146193323Sed uint32_t value = (uint32_t)N->getZExtValue(); 147193323Sed return (value >= 1 && value <= 8) 148193323Sed || value == 16 149193323Sed || value == 24 150193323Sed || value == 32; 151193323Sed}]>; 152193323Sed 153198090Srdivackydef immBpwSubBitp : PatLeaf<(imm), [{ 154198090Srdivacky uint32_t value = (uint32_t)N->getZExtValue(); 155198090Srdivacky return (value >= 24 && value <= 31) 156198090Srdivacky || value == 16 157198090Srdivacky || value == 8 158198090Srdivacky || value == 0; 159198090Srdivacky}]>; 160198090Srdivacky 161193323Seddef lda16f : PatFrag<(ops node:$addr, node:$offset), 162193323Sed (add node:$addr, (shl node:$offset, 1))>; 163193323Seddef lda16b : PatFrag<(ops node:$addr, node:$offset), 164193323Sed (sub node:$addr, (shl node:$offset, 1))>; 165193323Seddef ldawf : PatFrag<(ops node:$addr, node:$offset), 166193323Sed (add node:$addr, (shl node:$offset, 2))>; 167193323Seddef ldawb : PatFrag<(ops node:$addr, node:$offset), 168193323Sed (sub node:$addr, (shl node:$offset, 2))>; 169193323Sed 170193323Sed// Instruction operand types 171193323Seddef calltarget : Operand<i32>; 172193323Seddef brtarget : Operand<OtherVT>; 173193323Seddef pclabel : Operand<i32>; 174193323Sed 175193323Sed// Addressing modes 176193323Seddef ADDRspii : ComplexPattern<i32, 2, "SelectADDRspii", [add, frameindex], []>; 177193323Seddef ADDRdpii : ComplexPattern<i32, 2, "SelectADDRdpii", [add, dprelwrapper], 178193323Sed []>; 179193323Seddef ADDRcpii : ComplexPattern<i32, 2, "SelectADDRcpii", [add, cprelwrapper], 180193323Sed []>; 181193323Sed 182193323Sed// Address operands 183193323Seddef MEMii : Operand<i32> { 184193323Sed let PrintMethod = "printMemOperand"; 185193323Sed let MIOperandInfo = (ops i32imm, i32imm); 186193323Sed} 187193323Sed 188193323Sed//===----------------------------------------------------------------------===// 189193323Sed// Instruction Class Templates 190193323Sed//===----------------------------------------------------------------------===// 191193323Sed 192193323Sed// Three operand short 193193323Sed 194193323Sedmulticlass F3R_2RUS<string OpcStr, SDNode OpNode> { 195193323Sed def _3r: _F3R< 196193323Sed (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), 197193323Sed !strconcat(OpcStr, " $dst, $b, $c"), 198193323Sed [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>; 199193323Sed def _2rus : _F2RUS< 200193323Sed (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c), 201193323Sed !strconcat(OpcStr, " $dst, $b, $c"), 202193323Sed [(set GRRegs:$dst, (OpNode GRRegs:$b, immUs:$c))]>; 203193323Sed} 204193323Sed 205193323Sedmulticlass F3R_2RUS_np<string OpcStr> { 206193323Sed def _3r: _F3R< 207193323Sed (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), 208193323Sed !strconcat(OpcStr, " $dst, $b, $c"), 209193323Sed []>; 210193323Sed def _2rus : _F2RUS< 211193323Sed (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c), 212193323Sed !strconcat(OpcStr, " $dst, $b, $c"), 213193323Sed []>; 214193323Sed} 215193323Sed 216193323Sedmulticlass F3R_2RBITP<string OpcStr, SDNode OpNode> { 217193323Sed def _3r: _F3R< 218193323Sed (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), 219193323Sed !strconcat(OpcStr, " $dst, $b, $c"), 220193323Sed [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>; 221193323Sed def _2rus : _F2RUS< 222193323Sed (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c), 223193323Sed !strconcat(OpcStr, " $dst, $b, $c"), 224193323Sed [(set GRRegs:$dst, (OpNode GRRegs:$b, immBitp:$c))]>; 225193323Sed} 226193323Sed 227193323Sedclass F3R<string OpcStr, SDNode OpNode> : _F3R< 228193323Sed (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), 229193323Sed !strconcat(OpcStr, " $dst, $b, $c"), 230193323Sed [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>; 231193323Sed 232193323Sedclass F3R_np<string OpcStr> : _F3R< 233193323Sed (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), 234193323Sed !strconcat(OpcStr, " $dst, $b, $c"), 235193323Sed []>; 236193323Sed// Three operand long 237193323Sed 238193323Sed/// FL3R_L2RUS multiclass - Define a normal FL3R/FL2RUS pattern in one shot. 239193323Sedmulticlass FL3R_L2RUS<string OpcStr, SDNode OpNode> { 240193323Sed def _l3r: _FL3R< 241193323Sed (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), 242193323Sed !strconcat(OpcStr, " $dst, $b, $c"), 243193323Sed [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>; 244193323Sed def _l2rus : _FL2RUS< 245193323Sed (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c), 246193323Sed !strconcat(OpcStr, " $dst, $b, $c"), 247193323Sed [(set GRRegs:$dst, (OpNode GRRegs:$b, immUs:$c))]>; 248193323Sed} 249193323Sed 250193323Sed/// FL3R_L2RUS multiclass - Define a normal FL3R/FL2RUS pattern in one shot. 251193323Sedmulticlass FL3R_L2RBITP<string OpcStr, SDNode OpNode> { 252193323Sed def _l3r: _FL3R< 253193323Sed (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), 254193323Sed !strconcat(OpcStr, " $dst, $b, $c"), 255193323Sed [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>; 256193323Sed def _l2rus : _FL2RUS< 257193323Sed (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c), 258193323Sed !strconcat(OpcStr, " $dst, $b, $c"), 259193323Sed [(set GRRegs:$dst, (OpNode GRRegs:$b, immBitp:$c))]>; 260193323Sed} 261193323Sed 262193323Sedclass FL3R<string OpcStr, SDNode OpNode> : _FL3R< 263193323Sed (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), 264193323Sed !strconcat(OpcStr, " $dst, $b, $c"), 265193323Sed [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>; 266193323Sed 267193323Sed// Register - U6 268193323Sed// Operand register - U6 269193323Sedmulticlass FRU6_LRU6_branch<string OpcStr> { 270193323Sed def _ru6: _FRU6< 271193323Sed (outs), (ins GRRegs:$cond, brtarget:$dest), 272193323Sed !strconcat(OpcStr, " $cond, $dest"), 273193323Sed []>; 274193323Sed def _lru6: _FLRU6< 275193323Sed (outs), (ins GRRegs:$cond, brtarget:$dest), 276193323Sed !strconcat(OpcStr, " $cond, $dest"), 277193323Sed []>; 278193323Sed} 279193323Sed 280193323Sedmulticlass FRU6_LRU6_cp<string OpcStr> { 281193323Sed def _ru6: _FRU6< 282193323Sed (outs GRRegs:$dst), (ins i32imm:$a), 283193323Sed !strconcat(OpcStr, " $dst, cp[$a]"), 284193323Sed []>; 285193323Sed def _lru6: _FLRU6< 286193323Sed (outs GRRegs:$dst), (ins i32imm:$a), 287193323Sed !strconcat(OpcStr, " $dst, cp[$a]"), 288193323Sed []>; 289193323Sed} 290193323Sed 291193323Sed// U6 292193323Sedmulticlass FU6_LU6<string OpcStr, SDNode OpNode> { 293193323Sed def _u6: _FU6< 294193323Sed (outs), (ins i32imm:$b), 295193323Sed !strconcat(OpcStr, " $b"), 296193323Sed [(OpNode immU6:$b)]>; 297193323Sed def _lu6: _FLU6< 298193323Sed (outs), (ins i32imm:$b), 299193323Sed !strconcat(OpcStr, " $b"), 300193323Sed [(OpNode immU16:$b)]>; 301193323Sed} 302193323Sed 303193323Sedmulticlass FU6_LU6_np<string OpcStr> { 304193323Sed def _u6: _FU6< 305193323Sed (outs), (ins i32imm:$b), 306193323Sed !strconcat(OpcStr, " $b"), 307193323Sed []>; 308193323Sed def _lu6: _FLU6< 309193323Sed (outs), (ins i32imm:$b), 310193323Sed !strconcat(OpcStr, " $b"), 311193323Sed []>; 312193323Sed} 313193323Sed 314193323Sed// U10 315193323Sedmulticlass FU10_LU10_np<string OpcStr> { 316193323Sed def _u10: _FU10< 317193323Sed (outs), (ins i32imm:$b), 318193323Sed !strconcat(OpcStr, " $b"), 319193323Sed []>; 320193323Sed def _lu10: _FLU10< 321193323Sed (outs), (ins i32imm:$b), 322193323Sed !strconcat(OpcStr, " $b"), 323193323Sed []>; 324193323Sed} 325193323Sed 326193323Sed// Two operand short 327193323Sed 328193323Sedclass F2R_np<string OpcStr> : _F2R< 329193323Sed (outs GRRegs:$dst), (ins GRRegs:$b), 330193323Sed !strconcat(OpcStr, " $dst, $b"), 331193323Sed []>; 332193323Sed 333193323Sed// Two operand long 334193323Sed 335193323Sed//===----------------------------------------------------------------------===// 336193323Sed// Pseudo Instructions 337193323Sed//===----------------------------------------------------------------------===// 338193323Sed 339193323Sedlet Defs = [SP], Uses = [SP] in { 340193323Seddef ADJCALLSTACKDOWN : PseudoInstXCore<(outs), (ins i32imm:$amt), 341193323Sed "${:comment} ADJCALLSTACKDOWN $amt", 342193323Sed [(callseq_start timm:$amt)]>; 343193323Seddef ADJCALLSTACKUP : PseudoInstXCore<(outs), (ins i32imm:$amt1, i32imm:$amt2), 344193323Sed "${:comment} ADJCALLSTACKUP $amt1", 345193323Sed [(callseq_end timm:$amt1, timm:$amt2)]>; 346193323Sed} 347193323Sed 348193323Seddef LDWFI : PseudoInstXCore<(outs GRRegs:$dst), (ins MEMii:$addr), 349193323Sed "${:comment} LDWFI $dst, $addr", 350193323Sed [(set GRRegs:$dst, (load ADDRspii:$addr))]>; 351193323Sed 352193323Seddef LDAWFI : PseudoInstXCore<(outs GRRegs:$dst), (ins MEMii:$addr), 353193323Sed "${:comment} LDAWFI $dst, $addr", 354193323Sed [(set GRRegs:$dst, ADDRspii:$addr)]>; 355193323Sed 356193323Seddef STWFI : PseudoInstXCore<(outs), (ins GRRegs:$src, MEMii:$addr), 357193323Sed "${:comment} STWFI $src, $addr", 358193323Sed [(store GRRegs:$src, ADDRspii:$addr)]>; 359193323Sed 360198892Srdivacky// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after 361198892Srdivacky// instruction selection into a branch sequence. 362198892Srdivackylet usesCustomInserter = 1 in { 363193323Sed def SELECT_CC : PseudoInstXCore<(outs GRRegs:$dst), 364193323Sed (ins GRRegs:$cond, GRRegs:$T, GRRegs:$F), 365193323Sed "${:comment} SELECT_CC PSEUDO!", 366193323Sed [(set GRRegs:$dst, 367193323Sed (select GRRegs:$cond, GRRegs:$T, GRRegs:$F))]>; 368193323Sed} 369193323Sed 370193323Sed//===----------------------------------------------------------------------===// 371193323Sed// Instructions 372193323Sed//===----------------------------------------------------------------------===// 373193323Sed 374193323Sed// Three operand short 375193323Seddefm ADD : F3R_2RUS<"add", add>; 376193323Seddefm SUB : F3R_2RUS<"sub", sub>; 377193323Sedlet neverHasSideEffects = 1 in { 378193323Seddefm EQ : F3R_2RUS_np<"eq">; 379193323Seddef LSS_3r : F3R_np<"lss">; 380193323Seddef LSU_3r : F3R_np<"lsu">; 381193323Sed} 382193323Seddef AND_3r : F3R<"and", and>; 383193323Seddef OR_3r : F3R<"or", or>; 384193323Sed 385193323Sedlet mayLoad=1 in { 386193323Seddef LDW_3r : _F3R<(outs GRRegs:$dst), (ins GRRegs:$addr, GRRegs:$offset), 387193323Sed "ldw $dst, $addr[$offset]", 388193323Sed []>; 389193323Sed 390193323Seddef LDW_2rus : _F2RUS<(outs GRRegs:$dst), (ins GRRegs:$addr, i32imm:$offset), 391193323Sed "ldw $dst, $addr[$offset]", 392193323Sed []>; 393193323Sed 394193323Seddef LD16S_3r : _F3R<(outs GRRegs:$dst), (ins GRRegs:$addr, GRRegs:$offset), 395193323Sed "ld16s $dst, $addr[$offset]", 396193323Sed []>; 397193323Sed 398193323Seddef LD8U_3r : _F3R<(outs GRRegs:$dst), (ins GRRegs:$addr, GRRegs:$offset), 399193323Sed "ld8u $dst, $addr[$offset]", 400193323Sed []>; 401193323Sed} 402193323Sed 403193323Sedlet mayStore=1 in { 404193323Seddef STW_3r : _F3R<(outs), (ins GRRegs:$val, GRRegs:$addr, GRRegs:$offset), 405193323Sed "stw $val, $addr[$offset]", 406193323Sed []>; 407193323Sed 408193323Seddef STW_2rus : _F2RUS<(outs), (ins GRRegs:$val, GRRegs:$addr, i32imm:$offset), 409193323Sed "stw $val, $addr[$offset]", 410193323Sed []>; 411193323Sed} 412193323Sed 413193323Seddefm SHL : F3R_2RBITP<"shl", shl>; 414193323Seddefm SHR : F3R_2RBITP<"shr", srl>; 415193323Sed// TODO tsetr 416193323Sed 417193323Sed// Three operand long 418193323Seddef LDAWF_l3r : _FL3R<(outs GRRegs:$dst), (ins GRRegs:$addr, GRRegs:$offset), 419193323Sed "ldaw $dst, $addr[$offset]", 420193323Sed [(set GRRegs:$dst, (ldawf GRRegs:$addr, GRRegs:$offset))]>; 421193323Sed 422193323Sedlet neverHasSideEffects = 1 in 423193323Seddef LDAWF_l2rus : _FL2RUS<(outs GRRegs:$dst), 424193323Sed (ins GRRegs:$addr, i32imm:$offset), 425193323Sed "ldaw $dst, $addr[$offset]", 426193323Sed []>; 427193323Sed 428193323Seddef LDAWB_l3r : _FL3R<(outs GRRegs:$dst), (ins GRRegs:$addr, GRRegs:$offset), 429193323Sed "ldaw $dst, $addr[-$offset]", 430193323Sed [(set GRRegs:$dst, (ldawb GRRegs:$addr, GRRegs:$offset))]>; 431193323Sed 432193323Sedlet neverHasSideEffects = 1 in 433193323Seddef LDAWB_l2rus : _FL2RUS<(outs GRRegs:$dst), 434193323Sed (ins GRRegs:$addr, i32imm:$offset), 435193323Sed "ldaw $dst, $addr[-$offset]", 436193323Sed []>; 437193323Sed 438193323Seddef LDA16F_l3r : _FL3R<(outs GRRegs:$dst), (ins GRRegs:$addr, GRRegs:$offset), 439193323Sed "lda16 $dst, $addr[$offset]", 440193323Sed [(set GRRegs:$dst, (lda16f GRRegs:$addr, GRRegs:$offset))]>; 441193323Sed 442193323Seddef LDA16B_l3r : _FL3R<(outs GRRegs:$dst), (ins GRRegs:$addr, GRRegs:$offset), 443193323Sed "lda16 $dst, $addr[-$offset]", 444193323Sed [(set GRRegs:$dst, (lda16b GRRegs:$addr, GRRegs:$offset))]>; 445193323Sed 446193323Seddef MUL_l3r : FL3R<"mul", mul>; 447193323Sed// Instructions which may trap are marked as side effecting. 448193323Sedlet hasSideEffects = 1 in { 449193323Seddef DIVS_l3r : FL3R<"divs", sdiv>; 450193323Seddef DIVU_l3r : FL3R<"divu", udiv>; 451193323Seddef REMS_l3r : FL3R<"rems", srem>; 452193323Seddef REMU_l3r : FL3R<"remu", urem>; 453193323Sed} 454193323Seddef XOR_l3r : FL3R<"xor", xor>; 455193323Seddefm ASHR : FL3R_L2RBITP<"ashr", sra>; 456193323Sed// TODO crc32, crc8, inpw, outpw 457193323Sedlet mayStore=1 in { 458193323Seddef ST16_l3r : _FL3R<(outs), (ins GRRegs:$val, GRRegs:$addr, GRRegs:$offset), 459193323Sed "st16 $val, $addr[$offset]", 460193323Sed []>; 461193323Sed 462193323Seddef ST8_l3r : _FL3R<(outs), (ins GRRegs:$val, GRRegs:$addr, GRRegs:$offset), 463193323Sed "st8 $val, $addr[$offset]", 464193323Sed []>; 465193323Sed} 466193323Sed 467193323Sed// Four operand long 468198090Srdivackylet Constraints = "$src1 = $dst1,$src2 = $dst2" in { 469193323Seddef MACCU_l4r : _L4R<(outs GRRegs:$dst1, GRRegs:$dst2), 470193323Sed (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3, 471193323Sed GRRegs:$src4), 472193323Sed "maccu $dst1, $dst2, $src3, $src4", 473193323Sed []>; 474193323Sed 475193323Seddef MACCS_l4r : _L4R<(outs GRRegs:$dst1, GRRegs:$dst2), 476193323Sed (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3, 477193323Sed GRRegs:$src4), 478193323Sed "maccs $dst1, $dst2, $src3, $src4", 479193323Sed []>; 480193323Sed} 481193323Sed 482193323Sed// Five operand long 483193323Sed 484193323Seddef LADD_l5r : _L5R<(outs GRRegs:$dst1, GRRegs:$dst2), 485193323Sed (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3), 486193323Sed "ladd $dst1, $dst2, $src1, $src2, $src3", 487193323Sed []>; 488193323Sed 489193323Seddef LSUB_l5r : _L5R<(outs GRRegs:$dst1, GRRegs:$dst2), 490193323Sed (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3), 491193323Sed "lsub $dst1, $dst2, $src1, $src2, $src3", 492193323Sed []>; 493193323Sed 494193323Seddef LDIV_l5r : _L5R<(outs GRRegs:$dst1, GRRegs:$dst2), 495193323Sed (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3), 496193323Sed "ldiv $dst1, $dst2, $src1, $src2, $src3", 497193323Sed []>; 498193323Sed 499193323Sed// Six operand long 500193323Sed 501193323Seddef LMUL_l6r : _L6R<(outs GRRegs:$dst1, GRRegs:$dst2), 502193323Sed (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3, 503193323Sed GRRegs:$src4), 504193323Sed "lmul $dst1, $dst2, $src1, $src2, $src3, $src4", 505193323Sed []>; 506193323Sed 507193323Sed// Register - U6 508193323Sed 509193323Sed//let Uses = [DP] in ... 510193323Sedlet neverHasSideEffects = 1, isReMaterializable = 1 in 511193323Seddef LDAWDP_ru6: _FRU6<(outs GRRegs:$dst), (ins MEMii:$a), 512193323Sed "ldaw $dst, dp[$a]", 513193323Sed []>; 514193323Sed 515193323Sedlet isReMaterializable = 1 in 516193323Seddef LDAWDP_lru6: _FLRU6< 517193323Sed (outs GRRegs:$dst), (ins MEMii:$a), 518193323Sed "ldaw $dst, dp[$a]", 519193323Sed [(set GRRegs:$dst, ADDRdpii:$a)]>; 520193323Sed 521193323Sedlet mayLoad=1 in 522193323Seddef LDWDP_ru6: _FRU6<(outs GRRegs:$dst), (ins MEMii:$a), 523193323Sed "ldw $dst, dp[$a]", 524193323Sed []>; 525193323Sed 526193323Seddef LDWDP_lru6: _FLRU6< 527193323Sed (outs GRRegs:$dst), (ins MEMii:$a), 528193323Sed "ldw $dst, dp[$a]", 529193323Sed [(set GRRegs:$dst, (load ADDRdpii:$a))]>; 530193323Sed 531193323Sedlet mayStore=1 in 532193323Seddef STWDP_ru6 : _FRU6<(outs), (ins GRRegs:$val, MEMii:$addr), 533193323Sed "stw $val, dp[$addr]", 534193323Sed []>; 535193323Sed 536193323Seddef STWDP_lru6 : _FLRU6<(outs), (ins GRRegs:$val, MEMii:$addr), 537193323Sed "stw $val, dp[$addr]", 538193323Sed [(store GRRegs:$val, ADDRdpii:$addr)]>; 539193323Sed 540193323Sed//let Uses = [CP] in .. 541193323Sedlet mayLoad = 1, isReMaterializable = 1 in 542193323Seddefm LDWCP : FRU6_LRU6_cp<"ldw">; 543193323Sed 544193323Sedlet Uses = [SP] in { 545193323Sedlet mayStore=1 in { 546193323Seddef STWSP_ru6 : _FRU6< 547193323Sed (outs), (ins GRRegs:$val, i32imm:$index), 548193323Sed "stw $val, sp[$index]", 549193323Sed [(XCoreStwsp GRRegs:$val, immU6:$index)]>; 550193323Sed 551193323Seddef STWSP_lru6 : _FLRU6< 552193323Sed (outs), (ins GRRegs:$val, i32imm:$index), 553193323Sed "stw $val, sp[$index]", 554193323Sed [(XCoreStwsp GRRegs:$val, immU16:$index)]>; 555193323Sed} 556193323Sed 557193323Sedlet mayLoad=1 in { 558193323Seddef LDWSP_ru6 : _FRU6< 559193323Sed (outs GRRegs:$dst), (ins i32imm:$b), 560193323Sed "ldw $dst, sp[$b]", 561193323Sed []>; 562193323Sed 563193323Seddef LDWSP_lru6 : _FLRU6< 564193323Sed (outs GRRegs:$dst), (ins i32imm:$b), 565193323Sed "ldw $dst, sp[$b]", 566193323Sed []>; 567193323Sed} 568193323Sed 569193323Sedlet neverHasSideEffects = 1 in { 570193323Seddef LDAWSP_ru6 : _FRU6< 571193323Sed (outs GRRegs:$dst), (ins i32imm:$b), 572193323Sed "ldaw $dst, sp[$b]", 573193323Sed []>; 574193323Sed 575193323Seddef LDAWSP_lru6 : _FLRU6< 576193323Sed (outs GRRegs:$dst), (ins i32imm:$b), 577193323Sed "ldaw $dst, sp[$b]", 578193323Sed []>; 579193323Sed 580193323Seddef LDAWSP_ru6_RRegs : _FRU6< 581193323Sed (outs RRegs:$dst), (ins i32imm:$b), 582193323Sed "ldaw $dst, sp[$b]", 583193323Sed []>; 584193323Sed 585193323Seddef LDAWSP_lru6_RRegs : _FLRU6< 586193323Sed (outs RRegs:$dst), (ins i32imm:$b), 587193323Sed "ldaw $dst, sp[$b]", 588193323Sed []>; 589193323Sed} 590193323Sed} 591193323Sed 592193323Sedlet isReMaterializable = 1 in { 593193323Seddef LDC_ru6 : _FRU6< 594193323Sed (outs GRRegs:$dst), (ins i32imm:$b), 595193323Sed "ldc $dst, $b", 596193323Sed [(set GRRegs:$dst, immU6:$b)]>; 597193323Sed 598193323Seddef LDC_lru6 : _FLRU6< 599193323Sed (outs GRRegs:$dst), (ins i32imm:$b), 600193323Sed "ldc $dst, $b", 601193323Sed [(set GRRegs:$dst, immU16:$b)]>; 602193323Sed} 603193323Sed 604193323Sed// Operand register - U6 605193323Sed// TODO setc 606193323Sedlet isBranch = 1, isTerminator = 1 in { 607193323Seddefm BRFT: FRU6_LRU6_branch<"bt">; 608193323Seddefm BRBT: FRU6_LRU6_branch<"bt">; 609193323Seddefm BRFF: FRU6_LRU6_branch<"bf">; 610193323Seddefm BRBF: FRU6_LRU6_branch<"bf">; 611193323Sed} 612193323Sed 613193323Sed// U6 614193323Sedlet Defs = [SP], Uses = [SP] in { 615193323Sedlet neverHasSideEffects = 1 in 616193323Seddefm EXTSP : FU6_LU6_np<"extsp">; 617193323Sedlet mayStore = 1 in 618193323Seddefm ENTSP : FU6_LU6_np<"entsp">; 619193323Sed 620199481Srdivackylet isReturn = 1, isTerminator = 1, mayLoad = 1, isBarrier = 1 in { 621193323Seddefm RETSP : FU6_LU6<"retsp", XCoreRetsp>; 622193323Sed} 623193323Sed} 624193323Sed 625193323Sed// TODO extdp, kentsp, krestsp, blat, setsr 626193323Sed// clrsr, getsr, kalli 627193323Sedlet isBranch = 1, isTerminator = 1 in { 628193323Seddef BRBU_u6 : _FU6< 629193323Sed (outs), 630193323Sed (ins brtarget:$target), 631193323Sed "bu $target", 632193323Sed []>; 633193323Sed 634193323Seddef BRBU_lu6 : _FLU6< 635193323Sed (outs), 636193323Sed (ins brtarget:$target), 637193323Sed "bu $target", 638193323Sed []>; 639193323Sed 640193323Seddef BRFU_u6 : _FU6< 641193323Sed (outs), 642193323Sed (ins brtarget:$target), 643193323Sed "bu $target", 644193323Sed []>; 645193323Sed 646193323Seddef BRFU_lu6 : _FLU6< 647193323Sed (outs), 648193323Sed (ins brtarget:$target), 649193323Sed "bu $target", 650193323Sed []>; 651193323Sed} 652193323Sed 653193323Sed//let Uses = [CP] in ... 654198090Srdivackylet Defs = [R11], neverHasSideEffects = 1, isReMaterializable = 1 in 655193323Seddef LDAWCP_u6: _FRU6<(outs), (ins MEMii:$a), 656193323Sed "ldaw r11, cp[$a]", 657193323Sed []>; 658193323Sed 659198090Srdivackylet Defs = [R11], isReMaterializable = 1 in 660193323Seddef LDAWCP_lu6: _FLRU6< 661193323Sed (outs), (ins MEMii:$a), 662193323Sed "ldaw r11, cp[$a]", 663193323Sed [(set R11, ADDRcpii:$a)]>; 664193323Sed 665193323Sed// U10 666193323Sed// TODO ldwcpl, blacp 667193323Sed 668193323Sedlet Defs = [R11], isReMaterializable = 1, neverHasSideEffects = 1 in 669193323Seddef LDAP_u10 : _FU10< 670193323Sed (outs), 671193323Sed (ins i32imm:$addr), 672193323Sed "ldap r11, $addr", 673193323Sed []>; 674193323Sed 675193323Sedlet Defs = [R11], isReMaterializable = 1 in 676193323Seddef LDAP_lu10 : _FLU10< 677193323Sed (outs), 678193323Sed (ins i32imm:$addr), 679193323Sed "ldap r11, $addr", 680193323Sed [(set R11, (pcrelwrapper tglobaladdr:$addr))]>; 681193323Sed 682199511Srdivackylet Defs = [R11], isReMaterializable = 1 in 683199511Srdivackydef LDAP_lu10_ba : _FLU10<(outs), 684199511Srdivacky (ins i32imm:$addr), 685199511Srdivacky "ldap r11, $addr", 686199511Srdivacky [(set R11, (pcrelwrapper tblockaddress:$addr))]>; 687199511Srdivacky 688193323Sedlet isCall=1, 689203954Srdivacky// All calls clobber the link register and the non-callee-saved registers: 690193323SedDefs = [R0, R1, R2, R3, R11, LR] in { 691193323Seddef BL_u10 : _FU10< 692193323Sed (outs), 693193323Sed (ins calltarget:$target, variable_ops), 694193323Sed "bl $target", 695193323Sed [(XCoreBranchLink immU10:$target)]>; 696193323Sed 697193323Seddef BL_lu10 : _FLU10< 698193323Sed (outs), 699193323Sed (ins calltarget:$target, variable_ops), 700193323Sed "bl $target", 701193323Sed [(XCoreBranchLink immU20:$target)]>; 702193323Sed} 703193323Sed 704193323Sed// Two operand short 705193323Sed// TODO getr, getst 706193323Seddef NOT : _F2R<(outs GRRegs:$dst), (ins GRRegs:$b), 707193323Sed "not $dst, $b", 708193323Sed [(set GRRegs:$dst, (not GRRegs:$b))]>; 709193323Sed 710193323Seddef NEG : _F2R<(outs GRRegs:$dst), (ins GRRegs:$b), 711193323Sed "neg $dst, $b", 712193323Sed [(set GRRegs:$dst, (ineg GRRegs:$b))]>; 713193323Sed 714193323Sed// TODO setd, eet, eef, getts, setpt, outct, inct, chkct, outt, intt, out, 715193323Sed// in, outshr, inshr, testct, testwct, tinitpc, tinitdp, tinitsp, tinitcp, 716193323Sed// tsetmr, sext (reg), zext (reg) 717193323Sedlet isTwoAddress = 1 in { 718193323Sedlet neverHasSideEffects = 1 in 719193323Seddef SEXT_rus : _FRUS<(outs GRRegs:$dst), (ins GRRegs:$src1, i32imm:$src2), 720193323Sed "sext $dst, $src2", 721193323Sed []>; 722193323Sed 723193323Sedlet neverHasSideEffects = 1 in 724193323Seddef ZEXT_rus : _FRUS<(outs GRRegs:$dst), (ins GRRegs:$src1, i32imm:$src2), 725193323Sed "zext $dst, $src2", 726193323Sed []>; 727193323Sed 728193323Seddef ANDNOT_2r : _F2R<(outs GRRegs:$dst), (ins GRRegs:$src1, GRRegs:$src2), 729193323Sed "andnot $dst, $src2", 730193323Sed [(set GRRegs:$dst, (and GRRegs:$src1, (not GRRegs:$src2)))]>; 731193323Sed} 732193323Sed 733193323Sedlet isReMaterializable = 1, neverHasSideEffects = 1 in 734193323Seddef MKMSK_rus : _FRUS<(outs GRRegs:$dst), (ins i32imm:$size), 735193323Sed "mkmsk $dst, $size", 736193323Sed []>; 737193323Sed 738193323Seddef MKMSK_2r : _FRUS<(outs GRRegs:$dst), (ins GRRegs:$size), 739193323Sed "mkmsk $dst, $size", 740193323Sed [(set GRRegs:$dst, (add (shl 1, GRRegs:$size), 0xffffffff))]>; 741193323Sed 742193323Sed// Two operand long 743193323Sed// TODO settw, setclk, setrdy, setpsc, endin, peek, 744193323Sed// getd, testlcl, tinitlr, getps, setps 745193323Seddef BITREV_l2r : _FL2R<(outs GRRegs:$dst), (ins GRRegs:$src), 746193323Sed "bitrev $dst, $src", 747193323Sed [(set GRRegs:$dst, (int_xcore_bitrev GRRegs:$src))]>; 748193323Sed 749193323Seddef BYTEREV_l2r : _FL2R<(outs GRRegs:$dst), (ins GRRegs:$src), 750193323Sed "byterev $dst, $src", 751193323Sed [(set GRRegs:$dst, (bswap GRRegs:$src))]>; 752193323Sed 753193323Seddef CLZ_l2r : _FL2R<(outs GRRegs:$dst), (ins GRRegs:$src), 754193323Sed "clz $dst, $src", 755193323Sed [(set GRRegs:$dst, (ctlz GRRegs:$src))]>; 756193323Sed 757193323Sed// One operand short 758193323Sed// TODO edu, eeu, waitet, waitef, freer, tstart, msync, mjoin, syncr, clrtp 759193323Sed// bru, setdp, setcp, setv, setev, kcall 760193323Sed// dgetreg 761193323Sedlet isBranch=1, isIndirectBranch=1, isTerminator=1 in 762193323Seddef BAU_1r : _F1R<(outs), (ins GRRegs:$addr), 763193323Sed "bau $addr", 764193323Sed [(brind GRRegs:$addr)]>; 765193323Sed 766193323Sedlet Defs=[SP], neverHasSideEffects=1 in 767193323Seddef SETSP_1r : _F1R<(outs), (ins GRRegs:$src), 768193323Sed "set sp, $src", 769193323Sed []>; 770193323Sed 771193323Sedlet isBarrier = 1, hasCtrlDep = 1 in 772193323Seddef ECALLT_1r : _F1R<(outs), (ins GRRegs:$src), 773193323Sed "ecallt $src", 774193323Sed []>; 775193323Sed 776193323Sedlet isBarrier = 1, hasCtrlDep = 1 in 777193323Seddef ECALLF_1r : _F1R<(outs), (ins GRRegs:$src), 778193323Sed "ecallf $src", 779193323Sed []>; 780193323Sed 781193323Sedlet isCall=1, 782203954Srdivacky// All calls clobber the link register and the non-callee-saved registers: 783193323SedDefs = [R0, R1, R2, R3, R11, LR] in { 784193323Seddef BLA_1r : _F1R<(outs), (ins GRRegs:$addr, variable_ops), 785193323Sed "bla $addr", 786193323Sed [(XCoreBranchLink GRRegs:$addr)]>; 787193323Sed} 788193323Sed 789193323Sed// Zero operand short 790193323Sed// TODO waiteu, clre, ssync, freet, ldspc, stspc, ldssr, stssr, ldsed, stsed, 791193323Sed// stet, geted, getet, getkep, getksp, setkep, getid, kret, dcall, dret, 792193323Sed// dentsp, drestsp 793193323Sed 794193323Sedlet Defs = [R11] in 795193323Seddef GETID_0R : _F0R<(outs), (ins), 796193323Sed "get r11, id", 797193323Sed [(set R11, (int_xcore_getid))]>; 798193323Sed 799193323Sed//===----------------------------------------------------------------------===// 800193323Sed// Non-Instruction Patterns 801193323Sed//===----------------------------------------------------------------------===// 802193323Sed 803193323Seddef : Pat<(XCoreBranchLink tglobaladdr:$addr), (BL_lu10 tglobaladdr:$addr)>; 804193323Seddef : Pat<(XCoreBranchLink texternalsym:$addr), (BL_lu10 texternalsym:$addr)>; 805193323Sed 806193323Sed/// sext_inreg 807193323Seddef : Pat<(sext_inreg GRRegs:$b, i1), (SEXT_rus GRRegs:$b, 1)>; 808193323Seddef : Pat<(sext_inreg GRRegs:$b, i8), (SEXT_rus GRRegs:$b, 8)>; 809193323Seddef : Pat<(sext_inreg GRRegs:$b, i16), (SEXT_rus GRRegs:$b, 16)>; 810193323Sed 811193323Sed/// loads 812193323Seddef : Pat<(zextloadi8 (add GRRegs:$addr, GRRegs:$offset)), 813193323Sed (LD8U_3r GRRegs:$addr, GRRegs:$offset)>; 814193323Seddef : Pat<(zextloadi8 GRRegs:$addr), (LD8U_3r GRRegs:$addr, (LDC_ru6 0))>; 815193323Sed 816198090Srdivackydef : Pat<(sextloadi16 (lda16f GRRegs:$addr, GRRegs:$offset)), 817193323Sed (LD16S_3r GRRegs:$addr, GRRegs:$offset)>; 818193323Seddef : Pat<(sextloadi16 GRRegs:$addr), (LD16S_3r GRRegs:$addr, (LDC_ru6 0))>; 819193323Sed 820193323Seddef : Pat<(load (ldawf GRRegs:$addr, GRRegs:$offset)), 821193323Sed (LDW_3r GRRegs:$addr, GRRegs:$offset)>; 822193323Seddef : Pat<(load (add GRRegs:$addr, immUs4:$offset)), 823193323Sed (LDW_2rus GRRegs:$addr, (div4_xform immUs4:$offset))>; 824193323Seddef : Pat<(load GRRegs:$addr), (LDW_2rus GRRegs:$addr, 0)>; 825193323Sed 826193323Sed/// anyext 827193323Seddef : Pat<(extloadi8 (add GRRegs:$addr, GRRegs:$offset)), 828193323Sed (LD8U_3r GRRegs:$addr, GRRegs:$offset)>; 829193323Seddef : Pat<(extloadi8 GRRegs:$addr), (LD8U_3r GRRegs:$addr, (LDC_ru6 0))>; 830193323Seddef : Pat<(extloadi16 (lda16f GRRegs:$addr, GRRegs:$offset)), 831193323Sed (LD16S_3r GRRegs:$addr, GRRegs:$offset)>; 832193323Seddef : Pat<(extloadi16 GRRegs:$addr), (LD16S_3r GRRegs:$addr, (LDC_ru6 0))>; 833193323Sed 834193323Sed/// stores 835193323Seddef : Pat<(truncstorei8 GRRegs:$val, (add GRRegs:$addr, GRRegs:$offset)), 836193323Sed (ST8_l3r GRRegs:$val, GRRegs:$addr, GRRegs:$offset)>; 837193323Seddef : Pat<(truncstorei8 GRRegs:$val, GRRegs:$addr), 838193323Sed (ST8_l3r GRRegs:$val, GRRegs:$addr, (LDC_ru6 0))>; 839193323Sed 840193323Seddef : Pat<(truncstorei16 GRRegs:$val, (lda16f GRRegs:$addr, GRRegs:$offset)), 841193323Sed (ST16_l3r GRRegs:$val, GRRegs:$addr, GRRegs:$offset)>; 842193323Seddef : Pat<(truncstorei16 GRRegs:$val, GRRegs:$addr), 843193323Sed (ST16_l3r GRRegs:$val, GRRegs:$addr, (LDC_ru6 0))>; 844193323Sed 845193323Seddef : Pat<(store GRRegs:$val, (ldawf GRRegs:$addr, GRRegs:$offset)), 846193323Sed (STW_3r GRRegs:$val, GRRegs:$addr, GRRegs:$offset)>; 847193323Seddef : Pat<(store GRRegs:$val, (add GRRegs:$addr, immUs4:$offset)), 848193323Sed (STW_2rus GRRegs:$val, GRRegs:$addr, (div4_xform immUs4:$offset))>; 849193323Seddef : Pat<(store GRRegs:$val, GRRegs:$addr), 850193323Sed (STW_2rus GRRegs:$val, GRRegs:$addr, 0)>; 851193323Sed 852193323Sed/// cttz 853193323Seddef : Pat<(cttz GRRegs:$src), (CLZ_l2r (BITREV_l2r GRRegs:$src))>; 854193323Sed 855193323Sed/// trap 856193323Seddef : Pat<(trap), (ECALLF_1r (LDC_ru6 0))>; 857193323Sed 858193323Sed/// 859193323Sed/// branch patterns 860193323Sed/// 861193323Sed 862193323Sed// unconditional branch 863193323Seddef : Pat<(br bb:$addr), (BRFU_lu6 bb:$addr)>; 864193323Sed 865193323Sed// direct match equal/notequal zero brcond 866193323Seddef : Pat<(brcond (setne GRRegs:$lhs, 0), bb:$dst), 867193323Sed (BRFT_lru6 GRRegs:$lhs, bb:$dst)>; 868193323Seddef : Pat<(brcond (seteq GRRegs:$lhs, 0), bb:$dst), 869193323Sed (BRFF_lru6 GRRegs:$lhs, bb:$dst)>; 870193323Sed 871193323Seddef : Pat<(brcond (setle GRRegs:$lhs, GRRegs:$rhs), bb:$dst), 872193323Sed (BRFF_lru6 (LSS_3r GRRegs:$rhs, GRRegs:$lhs), bb:$dst)>; 873193323Seddef : Pat<(brcond (setule GRRegs:$lhs, GRRegs:$rhs), bb:$dst), 874193323Sed (BRFF_lru6 (LSU_3r GRRegs:$rhs, GRRegs:$lhs), bb:$dst)>; 875193323Seddef : Pat<(brcond (setge GRRegs:$lhs, GRRegs:$rhs), bb:$dst), 876193323Sed (BRFF_lru6 (LSS_3r GRRegs:$lhs, GRRegs:$rhs), bb:$dst)>; 877193323Seddef : Pat<(brcond (setuge GRRegs:$lhs, GRRegs:$rhs), bb:$dst), 878193323Sed (BRFF_lru6 (LSU_3r GRRegs:$lhs, GRRegs:$rhs), bb:$dst)>; 879193323Seddef : Pat<(brcond (setne GRRegs:$lhs, GRRegs:$rhs), bb:$dst), 880193323Sed (BRFF_lru6 (EQ_3r GRRegs:$lhs, GRRegs:$rhs), bb:$dst)>; 881193323Seddef : Pat<(brcond (setne GRRegs:$lhs, immUs:$rhs), bb:$dst), 882193323Sed (BRFF_lru6 (EQ_2rus GRRegs:$lhs, immUs:$rhs), bb:$dst)>; 883193323Sed 884193323Sed// generic brcond pattern 885193323Seddef : Pat<(brcond GRRegs:$cond, bb:$addr), (BRFT_lru6 GRRegs:$cond, bb:$addr)>; 886193323Sed 887193323Sed 888193323Sed/// 889193323Sed/// Select patterns 890193323Sed/// 891193323Sed 892193323Sed// direct match equal/notequal zero select 893193323Seddef : Pat<(select (setne GRRegs:$lhs, 0), GRRegs:$T, GRRegs:$F), 894193323Sed (SELECT_CC GRRegs:$lhs, GRRegs:$T, GRRegs:$F)>; 895193323Sed 896193323Seddef : Pat<(select (seteq GRRegs:$lhs, 0), GRRegs:$T, GRRegs:$F), 897193323Sed (SELECT_CC GRRegs:$lhs, GRRegs:$F, GRRegs:$T)>; 898193323Sed 899193323Seddef : Pat<(select (setle GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F), 900193323Sed (SELECT_CC (LSS_3r GRRegs:$rhs, GRRegs:$lhs), GRRegs:$F, GRRegs:$T)>; 901193323Seddef : Pat<(select (setule GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F), 902193323Sed (SELECT_CC (LSU_3r GRRegs:$rhs, GRRegs:$lhs), GRRegs:$F, GRRegs:$T)>; 903193323Seddef : Pat<(select (setge GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F), 904193323Sed (SELECT_CC (LSS_3r GRRegs:$lhs, GRRegs:$rhs), GRRegs:$F, GRRegs:$T)>; 905193323Seddef : Pat<(select (setuge GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F), 906193323Sed (SELECT_CC (LSU_3r GRRegs:$lhs, GRRegs:$rhs), GRRegs:$F, GRRegs:$T)>; 907193323Seddef : Pat<(select (setne GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F), 908193323Sed (SELECT_CC (EQ_3r GRRegs:$lhs, GRRegs:$rhs), GRRegs:$F, GRRegs:$T)>; 909193323Seddef : Pat<(select (setne GRRegs:$lhs, immUs:$rhs), GRRegs:$T, GRRegs:$F), 910193323Sed (SELECT_CC (EQ_2rus GRRegs:$lhs, immUs:$rhs), GRRegs:$F, GRRegs:$T)>; 911193323Sed 912193323Sed/// 913193323Sed/// setcc patterns, only matched when none of the above brcond 914193323Sed/// patterns match 915193323Sed/// 916193323Sed 917193323Sed// setcc 2 register operands 918193323Seddef : Pat<(setle GRRegs:$lhs, GRRegs:$rhs), 919193323Sed (EQ_2rus (LSS_3r GRRegs:$rhs, GRRegs:$lhs), 0)>; 920193323Seddef : Pat<(setule GRRegs:$lhs, GRRegs:$rhs), 921193323Sed (EQ_2rus (LSU_3r GRRegs:$rhs, GRRegs:$lhs), 0)>; 922193323Sed 923193323Seddef : Pat<(setgt GRRegs:$lhs, GRRegs:$rhs), 924193323Sed (LSS_3r GRRegs:$rhs, GRRegs:$lhs)>; 925193323Seddef : Pat<(setugt GRRegs:$lhs, GRRegs:$rhs), 926193323Sed (LSU_3r GRRegs:$rhs, GRRegs:$lhs)>; 927193323Sed 928193323Seddef : Pat<(setge GRRegs:$lhs, GRRegs:$rhs), 929193323Sed (EQ_2rus (LSS_3r GRRegs:$lhs, GRRegs:$rhs), 0)>; 930193323Seddef : Pat<(setuge GRRegs:$lhs, GRRegs:$rhs), 931193323Sed (EQ_2rus (LSU_3r GRRegs:$lhs, GRRegs:$rhs), 0)>; 932193323Sed 933193323Seddef : Pat<(setlt GRRegs:$lhs, GRRegs:$rhs), 934193323Sed (LSS_3r GRRegs:$lhs, GRRegs:$rhs)>; 935193323Seddef : Pat<(setult GRRegs:$lhs, GRRegs:$rhs), 936193323Sed (LSU_3r GRRegs:$lhs, GRRegs:$rhs)>; 937193323Sed 938193323Seddef : Pat<(setne GRRegs:$lhs, GRRegs:$rhs), 939193323Sed (EQ_2rus (EQ_3r GRRegs:$lhs, GRRegs:$rhs), 0)>; 940193323Sed 941193323Seddef : Pat<(seteq GRRegs:$lhs, GRRegs:$rhs), 942193323Sed (EQ_3r GRRegs:$lhs, GRRegs:$rhs)>; 943193323Sed 944193323Sed// setcc reg/imm operands 945193323Seddef : Pat<(seteq GRRegs:$lhs, immUs:$rhs), 946193323Sed (EQ_2rus GRRegs:$lhs, immUs:$rhs)>; 947193323Seddef : Pat<(setne GRRegs:$lhs, immUs:$rhs), 948193323Sed (EQ_2rus (EQ_2rus GRRegs:$lhs, immUs:$rhs), 0)>; 949193323Sed 950193323Sed// misc 951193323Seddef : Pat<(add GRRegs:$addr, immUs4:$offset), 952193323Sed (LDAWF_l2rus GRRegs:$addr, (div4_xform immUs4:$offset))>; 953193323Sed 954193323Seddef : Pat<(sub GRRegs:$addr, immUs4:$offset), 955193323Sed (LDAWB_l2rus GRRegs:$addr, (div4_xform immUs4:$offset))>; 956193323Sed 957193323Seddef : Pat<(and GRRegs:$val, immMskBitp:$mask), 958193323Sed (ZEXT_rus GRRegs:$val, (msksize_xform immMskBitp:$mask))>; 959193323Sed 960193323Sed// (sub X, imm) gets canonicalized to (add X, -imm). Match this form. 961193323Seddef : Pat<(add GRRegs:$src1, immUsNeg:$src2), 962193323Sed (SUB_2rus GRRegs:$src1, (neg_xform immUsNeg:$src2))>; 963193323Sed 964193323Seddef : Pat<(add GRRegs:$src1, immUs4Neg:$src2), 965193323Sed (LDAWB_l2rus GRRegs:$src1, (div4neg_xform immUs4Neg:$src2))>; 966193323Sed 967193323Sed/// 968193323Sed/// Some peepholes 969193323Sed/// 970193323Sed 971193323Seddef : Pat<(mul GRRegs:$src, 3), 972193323Sed (LDA16F_l3r GRRegs:$src, GRRegs:$src)>; 973193323Sed 974193323Seddef : Pat<(mul GRRegs:$src, 5), 975193323Sed (LDAWF_l3r GRRegs:$src, GRRegs:$src)>; 976193323Sed 977193323Seddef : Pat<(mul GRRegs:$src, -3), 978193323Sed (LDAWB_l3r GRRegs:$src, GRRegs:$src)>; 979193323Sed 980193323Sed// ashr X, 32 is equivalent to ashr X, 31 on the XCore. 981193323Seddef : Pat<(sra GRRegs:$src, 31), 982193323Sed (ASHR_l2rus GRRegs:$src, 32)>; 983193323Sed 984198090Srdivackydef : Pat<(brcond (setlt GRRegs:$lhs, 0), bb:$dst), 985198090Srdivacky (BRFT_lru6 (ASHR_l2rus GRRegs:$lhs, 32), bb:$dst)>; 986198090Srdivacky 987198090Srdivacky// setge X, 0 is canonicalized to setgt X, -1 988198090Srdivackydef : Pat<(brcond (setgt GRRegs:$lhs, -1), bb:$dst), 989198090Srdivacky (BRFF_lru6 (ASHR_l2rus GRRegs:$lhs, 32), bb:$dst)>; 990198090Srdivacky 991198090Srdivackydef : Pat<(select (setlt GRRegs:$lhs, 0), GRRegs:$T, GRRegs:$F), 992198090Srdivacky (SELECT_CC (ASHR_l2rus GRRegs:$lhs, 32), GRRegs:$T, GRRegs:$F)>; 993198090Srdivacky 994198090Srdivackydef : Pat<(select (setgt GRRegs:$lhs, -1), GRRegs:$T, GRRegs:$F), 995198090Srdivacky (SELECT_CC (ASHR_l2rus GRRegs:$lhs, 32), GRRegs:$F, GRRegs:$T)>; 996198090Srdivacky 997198090Srdivackydef : Pat<(setgt GRRegs:$lhs, -1), 998198090Srdivacky (EQ_2rus (ASHR_l2rus GRRegs:$lhs, 32), 0)>; 999198090Srdivacky 1000198090Srdivackydef : Pat<(sra (shl GRRegs:$src, immBpwSubBitp:$imm), immBpwSubBitp:$imm), 1001198090Srdivacky (SEXT_rus GRRegs:$src, (bpwsub_xform immBpwSubBitp:$imm))>; 1002