XCoreISelLowering.h revision 249423 
1//===-- XCoreISelLowering.h - XCore DAG Lowering Interface ------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the interfaces that XCore uses to lower LLVM code into a
11// selection DAG.
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef XCOREISELLOWERING_H
16#define XCOREISELLOWERING_H
17
18#include "XCore.h"
19#include "llvm/CodeGen/SelectionDAG.h"
20#include "llvm/Target/TargetLowering.h"
21
22namespace llvm {
23
24  // Forward delcarations
25  class XCoreSubtarget;
26  class XCoreTargetMachine;
27
28  namespace XCoreISD {
29    enum NodeType {
30      // Start the numbering where the builtin ops and target ops leave off.
31      FIRST_NUMBER = ISD::BUILTIN_OP_END,
32
33      // Branch and link (call)
34      BL,
35
36      // pc relative address
37      PCRelativeWrapper,
38
39      // dp relative address
40      DPRelativeWrapper,
41
42      // cp relative address
43      CPRelativeWrapper,
44
45      // Store word to stack
46      STWSP,
47
48      // Corresponds to retsp instruction
49      RETSP,
50
51      // Corresponds to LADD instruction
52      LADD,
53
54      // Corresponds to LSUB instruction
55      LSUB,
56
57      // Corresponds to LMUL instruction
58      LMUL,
59
60      // Corresponds to MACCU instruction
61      MACCU,
62
63      // Corresponds to MACCS instruction
64      MACCS,
65
66      // Corresponds to CRC8 instruction
67      CRC8,
68
69      // Jumptable branch.
70      BR_JT,
71
72      // Jumptable branch using long branches for each entry.
73      BR_JT32
74    };
75  }
76
77  //===--------------------------------------------------------------------===//
78  // TargetLowering Implementation
79  //===--------------------------------------------------------------------===//
80  class XCoreTargetLowering : public TargetLowering
81  {
82  public:
83
84    explicit XCoreTargetLowering(XCoreTargetMachine &TM);
85
86    virtual unsigned getJumpTableEncoding() const;
87    virtual MVT getScalarShiftAmountTy(EVT LHSTy) const { return MVT::i32; }
88
89    /// LowerOperation - Provide custom lowering hooks for some operations.
90    virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
91
92    /// ReplaceNodeResults - Replace the results of node with an illegal result
93    /// type with new values built out of custom code.
94    ///
95    virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
96                                    SelectionDAG &DAG) const;
97
98    /// getTargetNodeName - This method returns the name of a target specific
99    //  DAG node.
100    virtual const char *getTargetNodeName(unsigned Opcode) const;
101
102    virtual MachineBasicBlock *
103      EmitInstrWithCustomInserter(MachineInstr *MI,
104                                  MachineBasicBlock *MBB) const;
105
106    virtual bool isLegalAddressingMode(const AddrMode &AM,
107                                       Type *Ty) const;
108
109  private:
110    const XCoreTargetMachine &TM;
111    const XCoreSubtarget &Subtarget;
112
113    // Lower Operand helpers
114    SDValue LowerCCCArguments(SDValue Chain,
115                              CallingConv::ID CallConv,
116                              bool isVarArg,
117                              const SmallVectorImpl<ISD::InputArg> &Ins,
118                              DebugLoc dl, SelectionDAG &DAG,
119                              SmallVectorImpl<SDValue> &InVals) const;
120    SDValue LowerCCCCallTo(SDValue Chain, SDValue Callee,
121                           CallingConv::ID CallConv, bool isVarArg,
122                           bool isTailCall,
123                           const SmallVectorImpl<ISD::OutputArg> &Outs,
124                           const SmallVectorImpl<SDValue> &OutVals,
125                           const SmallVectorImpl<ISD::InputArg> &Ins,
126                           DebugLoc dl, SelectionDAG &DAG,
127                           SmallVectorImpl<SDValue> &InVals) const;
128    SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
129                            CallingConv::ID CallConv, bool isVarArg,
130                            const SmallVectorImpl<ISD::InputArg> &Ins,
131                            DebugLoc dl, SelectionDAG &DAG,
132                            SmallVectorImpl<SDValue> &InVals) const;
133    SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const;
134    SDValue getGlobalAddressWrapper(SDValue GA, const GlobalValue *GV,
135                                    SelectionDAG &DAG) const;
136
137    // Lower Operand specifics
138    SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
139    SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
140    SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
141    SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
142    SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
143    SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
144    SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
145    SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
146    SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const;
147    SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
148    SDValue LowerUMUL_LOHI(SDValue Op, SelectionDAG &DAG) const;
149    SDValue LowerSMUL_LOHI(SDValue Op, SelectionDAG &DAG) const;
150    SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
151    SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
152    SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
153    SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
154
155    // Inline asm support
156    std::pair<unsigned, const TargetRegisterClass*>
157    getRegForInlineAsmConstraint(const std::string &Constraint,
158                                 EVT VT) const;
159
160    // Expand specifics
161    SDValue TryExpandADDWithMul(SDNode *Op, SelectionDAG &DAG) const;
162    SDValue ExpandADDSUB(SDNode *Op, SelectionDAG &DAG) const;
163
164    virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
165
166    virtual void computeMaskedBitsForTargetNode(const SDValue Op,
167                                                APInt &KnownZero,
168                                                APInt &KnownOne,
169                                                const SelectionDAG &DAG,
170                                                unsigned Depth = 0) const;
171
172    virtual SDValue
173      LowerFormalArguments(SDValue Chain,
174                           CallingConv::ID CallConv,
175                           bool isVarArg,
176                           const SmallVectorImpl<ISD::InputArg> &Ins,
177                           DebugLoc dl, SelectionDAG &DAG,
178                           SmallVectorImpl<SDValue> &InVals) const;
179
180    virtual SDValue
181      LowerCall(TargetLowering::CallLoweringInfo &CLI,
182                SmallVectorImpl<SDValue> &InVals) const;
183
184    virtual SDValue
185      LowerReturn(SDValue Chain,
186                  CallingConv::ID CallConv, bool isVarArg,
187                  const SmallVectorImpl<ISD::OutputArg> &Outs,
188                  const SmallVectorImpl<SDValue> &OutVals,
189                  DebugLoc dl, SelectionDAG &DAG) const;
190
191    virtual bool
192      CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
193                     bool isVarArg,
194                     const SmallVectorImpl<ISD::OutputArg> &ArgsFlags,
195                     LLVMContext &Context) const;
196  };
197}
198
199#endif // XCOREISELLOWERING_H
200