XCoreISelLowering.h revision 226633 
1//===-- XCoreISelLowering.h - XCore DAG Lowering Interface ------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the interfaces that XCore uses to lower LLVM code into a
11// selection DAG.
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef XCOREISELLOWERING_H
16#define XCOREISELLOWERING_H
17
18#include "llvm/CodeGen/SelectionDAG.h"
19#include "llvm/Target/TargetLowering.h"
20#include "XCore.h"
21
22namespace llvm {
23
24  // Forward delcarations
25  class XCoreSubtarget;
26  class XCoreTargetMachine;
27
28  namespace XCoreISD {
29    enum NodeType {
30      // Start the numbering where the builtin ops and target ops leave off.
31      FIRST_NUMBER = ISD::BUILTIN_OP_END,
32
33      // Branch and link (call)
34      BL,
35
36      // pc relative address
37      PCRelativeWrapper,
38
39      // dp relative address
40      DPRelativeWrapper,
41
42      // cp relative address
43      CPRelativeWrapper,
44
45      // Store word to stack
46      STWSP,
47
48      // Corresponds to retsp instruction
49      RETSP,
50
51      // Corresponds to LADD instruction
52      LADD,
53
54      // Corresponds to LSUB instruction
55      LSUB,
56
57      // Corresponds to LMUL instruction
58      LMUL,
59
60      // Corresponds to MACCU instruction
61      MACCU,
62
63      // Corresponds to MACCS instruction
64      MACCS,
65
66      // Jumptable branch.
67      BR_JT,
68
69      // Jumptable branch using long branches for each entry.
70      BR_JT32
71    };
72  }
73
74  //===--------------------------------------------------------------------===//
75  // TargetLowering Implementation
76  //===--------------------------------------------------------------------===//
77  class XCoreTargetLowering : public TargetLowering
78  {
79  public:
80
81    explicit XCoreTargetLowering(XCoreTargetMachine &TM);
82
83    virtual unsigned getJumpTableEncoding() const;
84    virtual MVT getShiftAmountTy(EVT LHSTy) const { return MVT::i32; }
85
86    /// LowerOperation - Provide custom lowering hooks for some operations.
87    virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
88
89    /// ReplaceNodeResults - Replace the results of node with an illegal result
90    /// type with new values built out of custom code.
91    ///
92    virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
93                                    SelectionDAG &DAG) const;
94
95    /// getTargetNodeName - This method returns the name of a target specific
96    //  DAG node.
97    virtual const char *getTargetNodeName(unsigned Opcode) const;
98
99    virtual MachineBasicBlock *
100      EmitInstrWithCustomInserter(MachineInstr *MI,
101                                  MachineBasicBlock *MBB) const;
102
103    virtual bool isLegalAddressingMode(const AddrMode &AM,
104                                       Type *Ty) const;
105
106  private:
107    const XCoreTargetMachine &TM;
108    const XCoreSubtarget &Subtarget;
109
110    // Lower Operand helpers
111    SDValue LowerCCCArguments(SDValue Chain,
112                              CallingConv::ID CallConv,
113                              bool isVarArg,
114                              const SmallVectorImpl<ISD::InputArg> &Ins,
115                              DebugLoc dl, SelectionDAG &DAG,
116                              SmallVectorImpl<SDValue> &InVals) const;
117    SDValue LowerCCCCallTo(SDValue Chain, SDValue Callee,
118                           CallingConv::ID CallConv, bool isVarArg,
119                           bool isTailCall,
120                           const SmallVectorImpl<ISD::OutputArg> &Outs,
121                           const SmallVectorImpl<SDValue> &OutVals,
122                           const SmallVectorImpl<ISD::InputArg> &Ins,
123                           DebugLoc dl, SelectionDAG &DAG,
124                           SmallVectorImpl<SDValue> &InVals) const;
125    SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
126                            CallingConv::ID CallConv, bool isVarArg,
127                            const SmallVectorImpl<ISD::InputArg> &Ins,
128                            DebugLoc dl, SelectionDAG &DAG,
129                            SmallVectorImpl<SDValue> &InVals) const;
130    SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const;
131    SDValue getGlobalAddressWrapper(SDValue GA, const GlobalValue *GV,
132                                    SelectionDAG &DAG) const;
133
134    // Lower Operand specifics
135    SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
136    SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
137    SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
138    SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
139    SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
140    SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
141    SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
142    SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
143    SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const;
144    SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
145    SDValue LowerUMUL_LOHI(SDValue Op, SelectionDAG &DAG) const;
146    SDValue LowerSMUL_LOHI(SDValue Op, SelectionDAG &DAG) const;
147    SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
148    SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
149    SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
150
151    // Inline asm support
152    std::pair<unsigned, const TargetRegisterClass*>
153    getRegForInlineAsmConstraint(const std::string &Constraint,
154				 EVT VT) const;
155
156    // Expand specifics
157    SDValue TryExpandADDWithMul(SDNode *Op, SelectionDAG &DAG) const;
158    SDValue ExpandADDSUB(SDNode *Op, SelectionDAG &DAG) const;
159
160    virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
161
162    virtual void computeMaskedBitsForTargetNode(const SDValue Op,
163                                                const APInt &Mask,
164                                                APInt &KnownZero,
165                                                APInt &KnownOne,
166                                                const SelectionDAG &DAG,
167                                                unsigned Depth = 0) const;
168
169    virtual SDValue
170      LowerFormalArguments(SDValue Chain,
171                           CallingConv::ID CallConv,
172                           bool isVarArg,
173                           const SmallVectorImpl<ISD::InputArg> &Ins,
174                           DebugLoc dl, SelectionDAG &DAG,
175                           SmallVectorImpl<SDValue> &InVals) const;
176
177    virtual SDValue
178      LowerCall(SDValue Chain, SDValue Callee,
179                CallingConv::ID CallConv, bool isVarArg,
180                bool &isTailCall,
181                const SmallVectorImpl<ISD::OutputArg> &Outs,
182                const SmallVectorImpl<SDValue> &OutVals,
183                const SmallVectorImpl<ISD::InputArg> &Ins,
184                DebugLoc dl, SelectionDAG &DAG,
185                SmallVectorImpl<SDValue> &InVals) const;
186
187    virtual SDValue
188      LowerReturn(SDValue Chain,
189                  CallingConv::ID CallConv, bool isVarArg,
190                  const SmallVectorImpl<ISD::OutputArg> &Outs,
191                  const SmallVectorImpl<SDValue> &OutVals,
192                  DebugLoc dl, SelectionDAG &DAG) const;
193
194    virtual bool
195      CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
196		     bool isVarArg,
197                     const SmallVectorImpl<ISD::OutputArg> &ArgsFlags,
198                     LLVMContext &Context) const;
199  };
200}
201
202#endif // XCOREISELLOWERING_H
203