XCoreISelLowering.h revision 219077
1//===-- XCoreISelLowering.h - XCore DAG Lowering Interface ------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the interfaces that XCore uses to lower LLVM code into a 11// selection DAG. 12// 13//===----------------------------------------------------------------------===// 14 15#ifndef XCOREISELLOWERING_H 16#define XCOREISELLOWERING_H 17 18#include "llvm/CodeGen/SelectionDAG.h" 19#include "llvm/Target/TargetLowering.h" 20#include "XCore.h" 21 22namespace llvm { 23 24 // Forward delcarations 25 class XCoreSubtarget; 26 class XCoreTargetMachine; 27 28 namespace XCoreISD { 29 enum NodeType { 30 // Start the numbering where the builtin ops and target ops leave off. 31 FIRST_NUMBER = ISD::BUILTIN_OP_END, 32 33 // Branch and link (call) 34 BL, 35 36 // pc relative address 37 PCRelativeWrapper, 38 39 // dp relative address 40 DPRelativeWrapper, 41 42 // cp relative address 43 CPRelativeWrapper, 44 45 // Store word to stack 46 STWSP, 47 48 // Corresponds to retsp instruction 49 RETSP, 50 51 // Corresponds to LADD instruction 52 LADD, 53 54 // Corresponds to LSUB instruction 55 LSUB, 56 57 // Corresponds to LMUL instruction 58 LMUL, 59 60 // Corresponds to MACCU instruction 61 MACCU, 62 63 // Corresponds to MACCS instruction 64 MACCS, 65 66 // Jumptable branch. 67 BR_JT, 68 69 // Jumptable branch using long branches for each entry. 70 BR_JT32 71 }; 72 } 73 74 //===--------------------------------------------------------------------===// 75 // TargetLowering Implementation 76 //===--------------------------------------------------------------------===// 77 class XCoreTargetLowering : public TargetLowering 78 { 79 public: 80 81 explicit XCoreTargetLowering(XCoreTargetMachine &TM); 82 83 virtual unsigned getJumpTableEncoding() const; 84 virtual MVT getShiftAmountTy(EVT LHSTy) const { return MVT::i32; } 85 86 /// LowerOperation - Provide custom lowering hooks for some operations. 87 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const; 88 89 /// ReplaceNodeResults - Replace the results of node with an illegal result 90 /// type with new values built out of custom code. 91 /// 92 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results, 93 SelectionDAG &DAG) const; 94 95 /// getTargetNodeName - This method returns the name of a target specific 96 // DAG node. 97 virtual const char *getTargetNodeName(unsigned Opcode) const; 98 99 virtual MachineBasicBlock * 100 EmitInstrWithCustomInserter(MachineInstr *MI, 101 MachineBasicBlock *MBB) const; 102 103 virtual bool isLegalAddressingMode(const AddrMode &AM, 104 const Type *Ty) const; 105 106 /// getFunctionAlignment - Return the Log2 alignment of this function. 107 virtual unsigned getFunctionAlignment(const Function *F) const; 108 109 private: 110 const XCoreTargetMachine &TM; 111 const XCoreSubtarget &Subtarget; 112 113 // Lower Operand helpers 114 SDValue LowerCCCArguments(SDValue Chain, 115 CallingConv::ID CallConv, 116 bool isVarArg, 117 const SmallVectorImpl<ISD::InputArg> &Ins, 118 DebugLoc dl, SelectionDAG &DAG, 119 SmallVectorImpl<SDValue> &InVals) const; 120 SDValue LowerCCCCallTo(SDValue Chain, SDValue Callee, 121 CallingConv::ID CallConv, bool isVarArg, 122 bool isTailCall, 123 const SmallVectorImpl<ISD::OutputArg> &Outs, 124 const SmallVectorImpl<SDValue> &OutVals, 125 const SmallVectorImpl<ISD::InputArg> &Ins, 126 DebugLoc dl, SelectionDAG &DAG, 127 SmallVectorImpl<SDValue> &InVals) const; 128 SDValue LowerCallResult(SDValue Chain, SDValue InFlag, 129 CallingConv::ID CallConv, bool isVarArg, 130 const SmallVectorImpl<ISD::InputArg> &Ins, 131 DebugLoc dl, SelectionDAG &DAG, 132 SmallVectorImpl<SDValue> &InVals) const; 133 SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const; 134 SDValue getGlobalAddressWrapper(SDValue GA, const GlobalValue *GV, 135 SelectionDAG &DAG) const; 136 137 // Lower Operand specifics 138 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const; 139 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const; 140 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const; 141 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const; 142 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const; 143 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const; 144 SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const; 145 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const; 146 SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const; 147 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const; 148 SDValue LowerUMUL_LOHI(SDValue Op, SelectionDAG &DAG) const; 149 SDValue LowerSMUL_LOHI(SDValue Op, SelectionDAG &DAG) const; 150 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const; 151 SDValue LowerTRAMPOLINE(SDValue Op, SelectionDAG &DAG) const; 152 153 // Inline asm support 154 std::vector<unsigned> 155 getRegClassForInlineAsmConstraint(const std::string &Constraint, 156 EVT VT) const; 157 158 // Expand specifics 159 SDValue TryExpandADDWithMul(SDNode *Op, SelectionDAG &DAG) const; 160 SDValue ExpandADDSUB(SDNode *Op, SelectionDAG &DAG) const; 161 162 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const; 163 164 virtual void computeMaskedBitsForTargetNode(const SDValue Op, 165 const APInt &Mask, 166 APInt &KnownZero, 167 APInt &KnownOne, 168 const SelectionDAG &DAG, 169 unsigned Depth = 0) const; 170 171 virtual SDValue 172 LowerFormalArguments(SDValue Chain, 173 CallingConv::ID CallConv, 174 bool isVarArg, 175 const SmallVectorImpl<ISD::InputArg> &Ins, 176 DebugLoc dl, SelectionDAG &DAG, 177 SmallVectorImpl<SDValue> &InVals) const; 178 179 virtual SDValue 180 LowerCall(SDValue Chain, SDValue Callee, 181 CallingConv::ID CallConv, bool isVarArg, 182 bool &isTailCall, 183 const SmallVectorImpl<ISD::OutputArg> &Outs, 184 const SmallVectorImpl<SDValue> &OutVals, 185 const SmallVectorImpl<ISD::InputArg> &Ins, 186 DebugLoc dl, SelectionDAG &DAG, 187 SmallVectorImpl<SDValue> &InVals) const; 188 189 virtual SDValue 190 LowerReturn(SDValue Chain, 191 CallingConv::ID CallConv, bool isVarArg, 192 const SmallVectorImpl<ISD::OutputArg> &Outs, 193 const SmallVectorImpl<SDValue> &OutVals, 194 DebugLoc dl, SelectionDAG &DAG) const; 195 196 virtual bool 197 CanLowerReturn(CallingConv::ID CallConv, bool isVarArg, 198 const SmallVectorImpl<ISD::OutputArg> &ArgsFlags, 199 LLVMContext &Context) const; 200 }; 201} 202 203#endif // XCOREISELLOWERING_H 204