XCoreISelLowering.h revision 205218 
1//===-- XCoreISelLowering.h - XCore DAG Lowering Interface ------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the interfaces that XCore uses to lower LLVM code into a
11// selection DAG.
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef XCOREISELLOWERING_H
16#define XCOREISELLOWERING_H
17
18#include "llvm/CodeGen/SelectionDAG.h"
19#include "llvm/Target/TargetLowering.h"
20#include "XCore.h"
21
22namespace llvm {
23
24  // Forward delcarations
25  class XCoreSubtarget;
26  class XCoreTargetMachine;
27
28  namespace XCoreISD {
29    enum NodeType {
30      // Start the numbering where the builtin ops and target ops leave off.
31      FIRST_NUMBER = ISD::BUILTIN_OP_END,
32
33      // Branch and link (call)
34      BL,
35
36      // pc relative address
37      PCRelativeWrapper,
38
39      // dp relative address
40      DPRelativeWrapper,
41
42      // cp relative address
43      CPRelativeWrapper,
44
45      // Store word to stack
46      STWSP,
47
48      // Corresponds to retsp instruction
49      RETSP,
50
51      // Corresponds to LADD instruction
52      LADD,
53
54      // Corresponds to LSUB instruction
55      LSUB,
56
57      // Corresponds to LMUL instruction
58      LMUL,
59
60      // Corresponds to MACCU instruction
61      MACCU,
62
63      // Corresponds to MACCS instruction
64      MACCS,
65
66      // Jumptable branch.
67      BR_JT,
68
69      // Jumptable branch using long branches for each entry.
70      BR_JT32
71    };
72  }
73
74  //===--------------------------------------------------------------------===//
75  // TargetLowering Implementation
76  //===--------------------------------------------------------------------===//
77  class XCoreTargetLowering : public TargetLowering
78  {
79  public:
80
81    explicit XCoreTargetLowering(XCoreTargetMachine &TM);
82
83    virtual unsigned getJumpTableEncoding() const;
84
85    /// LowerOperation - Provide custom lowering hooks for some operations.
86    virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG);
87
88    /// ReplaceNodeResults - Replace the results of node with an illegal result
89    /// type with new values built out of custom code.
90    ///
91    virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
92                                    SelectionDAG &DAG);
93
94    /// getTargetNodeName - This method returns the name of a target specific
95    //  DAG node.
96    virtual const char *getTargetNodeName(unsigned Opcode) const;
97
98    virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI,
99                                                         MachineBasicBlock *MBB,
100                    DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const;
101
102    virtual bool isLegalAddressingMode(const AddrMode &AM,
103                                       const Type *Ty) const;
104
105    /// getFunctionAlignment - Return the Log2 alignment of this function.
106    virtual unsigned getFunctionAlignment(const Function *F) const;
107
108  private:
109    const XCoreTargetMachine &TM;
110    const XCoreSubtarget &Subtarget;
111
112    // Lower Operand helpers
113    SDValue LowerCCCArguments(SDValue Chain,
114                              CallingConv::ID CallConv,
115                              bool isVarArg,
116                              const SmallVectorImpl<ISD::InputArg> &Ins,
117                              DebugLoc dl, SelectionDAG &DAG,
118                              SmallVectorImpl<SDValue> &InVals);
119    SDValue LowerCCCCallTo(SDValue Chain, SDValue Callee,
120                           CallingConv::ID CallConv, bool isVarArg,
121                           bool isTailCall,
122                           const SmallVectorImpl<ISD::OutputArg> &Outs,
123                           const SmallVectorImpl<ISD::InputArg> &Ins,
124                           DebugLoc dl, SelectionDAG &DAG,
125                           SmallVectorImpl<SDValue> &InVals);
126    SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
127                            CallingConv::ID CallConv, bool isVarArg,
128                            const SmallVectorImpl<ISD::InputArg> &Ins,
129                            DebugLoc dl, SelectionDAG &DAG,
130                            SmallVectorImpl<SDValue> &InVals);
131    SDValue getReturnAddressFrameIndex(SelectionDAG &DAG);
132    SDValue getGlobalAddressWrapper(SDValue GA, GlobalValue *GV,
133                                    SelectionDAG &DAG);
134
135    // Lower Operand specifics
136    SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG);
137    SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG);
138    SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG);
139    SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG);
140    SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG);
141    SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG);
142    SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG);
143    SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG);
144    SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG);
145    SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG);
146    SDValue LowerUMUL_LOHI(SDValue Op, SelectionDAG &DAG);
147    SDValue LowerSMUL_LOHI(SDValue Op, SelectionDAG &DAG);
148    SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG);
149
150    // Inline asm support
151    std::vector<unsigned>
152    getRegClassForInlineAsmConstraint(const std::string &Constraint,
153              EVT VT) const;
154
155    // Expand specifics
156    SDValue TryExpandADDWithMul(SDNode *Op, SelectionDAG &DAG);
157    SDValue ExpandADDSUB(SDNode *Op, SelectionDAG &DAG);
158
159    virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
160
161    virtual void computeMaskedBitsForTargetNode(const SDValue Op,
162                                                const APInt &Mask,
163                                                APInt &KnownZero,
164                                                APInt &KnownOne,
165                                                const SelectionDAG &DAG,
166                                                unsigned Depth = 0) const;
167
168    virtual SDValue
169      LowerFormalArguments(SDValue Chain,
170                           CallingConv::ID CallConv,
171                           bool isVarArg,
172                           const SmallVectorImpl<ISD::InputArg> &Ins,
173                           DebugLoc dl, SelectionDAG &DAG,
174                           SmallVectorImpl<SDValue> &InVals);
175
176    virtual SDValue
177      LowerCall(SDValue Chain, SDValue Callee,
178                CallingConv::ID CallConv, bool isVarArg,
179                bool &isTailCall,
180                const SmallVectorImpl<ISD::OutputArg> &Outs,
181                const SmallVectorImpl<ISD::InputArg> &Ins,
182                DebugLoc dl, SelectionDAG &DAG,
183                SmallVectorImpl<SDValue> &InVals);
184
185    virtual SDValue
186      LowerReturn(SDValue Chain,
187                  CallingConv::ID CallConv, bool isVarArg,
188                  const SmallVectorImpl<ISD::OutputArg> &Outs,
189                  DebugLoc dl, SelectionDAG &DAG);
190
191    virtual bool
192      CanLowerReturn(CallingConv::ID CallConv, bool isVarArg,
193                     const SmallVectorImpl<EVT> &OutTys,
194                     const SmallVectorImpl<ISD::ArgFlagsTy> &ArgsFlags,
195                     SelectionDAG &DAG);
196  };
197}
198
199#endif // XCOREISELLOWERING_H
200