X86FastISel.cpp revision 204792
1//===-- X86FastISel.cpp - X86 FastISel implementation ---------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the X86-specific support for the FastISel class. Much 11// of the target-specific code is generated by tablegen in the file 12// X86GenFastISel.inc, which is #included here. 13// 14//===----------------------------------------------------------------------===// 15 16#include "X86.h" 17#include "X86InstrBuilder.h" 18#include "X86ISelLowering.h" 19#include "X86RegisterInfo.h" 20#include "X86Subtarget.h" 21#include "X86TargetMachine.h" 22#include "llvm/CallingConv.h" 23#include "llvm/DerivedTypes.h" 24#include "llvm/GlobalVariable.h" 25#include "llvm/Instructions.h" 26#include "llvm/IntrinsicInst.h" 27#include "llvm/CodeGen/FastISel.h" 28#include "llvm/CodeGen/MachineConstantPool.h" 29#include "llvm/CodeGen/MachineFrameInfo.h" 30#include "llvm/CodeGen/MachineRegisterInfo.h" 31#include "llvm/Support/CallSite.h" 32#include "llvm/Support/ErrorHandling.h" 33#include "llvm/Support/GetElementPtrTypeIterator.h" 34#include "llvm/Target/TargetOptions.h" 35using namespace llvm; 36 37namespace { 38 39class X86FastISel : public FastISel { 40 /// Subtarget - Keep a pointer to the X86Subtarget around so that we can 41 /// make the right decision when generating code for different targets. 42 const X86Subtarget *Subtarget; 43 44 /// StackPtr - Register used as the stack pointer. 45 /// 46 unsigned StackPtr; 47 48 /// X86ScalarSSEf32, X86ScalarSSEf64 - Select between SSE or x87 49 /// floating point ops. 50 /// When SSE is available, use it for f32 operations. 51 /// When SSE2 is available, use it for f64 operations. 52 bool X86ScalarSSEf64; 53 bool X86ScalarSSEf32; 54 55public: 56 explicit X86FastISel(MachineFunction &mf, 57 MachineModuleInfo *mmi, 58 DwarfWriter *dw, 59 DenseMap<const Value *, unsigned> &vm, 60 DenseMap<const BasicBlock *, MachineBasicBlock *> &bm, 61 DenseMap<const AllocaInst *, int> &am 62#ifndef NDEBUG 63 , SmallSet<Instruction*, 8> &cil 64#endif 65 ) 66 : FastISel(mf, mmi, dw, vm, bm, am 67#ifndef NDEBUG 68 , cil 69#endif 70 ) { 71 Subtarget = &TM.getSubtarget<X86Subtarget>(); 72 StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP; 73 X86ScalarSSEf64 = Subtarget->hasSSE2(); 74 X86ScalarSSEf32 = Subtarget->hasSSE1(); 75 } 76 77 virtual bool TargetSelectInstruction(Instruction *I); 78 79#include "X86GenFastISel.inc" 80 81private: 82 bool X86FastEmitCompare(Value *LHS, Value *RHS, EVT VT); 83 84 bool X86FastEmitLoad(EVT VT, const X86AddressMode &AM, unsigned &RR); 85 86 bool X86FastEmitStore(EVT VT, Value *Val, 87 const X86AddressMode &AM); 88 bool X86FastEmitStore(EVT VT, unsigned Val, 89 const X86AddressMode &AM); 90 91 bool X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT, unsigned Src, EVT SrcVT, 92 unsigned &ResultReg); 93 94 bool X86SelectAddress(Value *V, X86AddressMode &AM); 95 bool X86SelectCallAddress(Value *V, X86AddressMode &AM); 96 97 bool X86SelectLoad(Instruction *I); 98 99 bool X86SelectStore(Instruction *I); 100 101 bool X86SelectCmp(Instruction *I); 102 103 bool X86SelectZExt(Instruction *I); 104 105 bool X86SelectBranch(Instruction *I); 106 107 bool X86SelectShift(Instruction *I); 108 109 bool X86SelectSelect(Instruction *I); 110 111 bool X86SelectTrunc(Instruction *I); 112 113 bool X86SelectFPExt(Instruction *I); 114 bool X86SelectFPTrunc(Instruction *I); 115 116 bool X86SelectExtractValue(Instruction *I); 117 118 bool X86VisitIntrinsicCall(IntrinsicInst &I); 119 bool X86SelectCall(Instruction *I); 120 121 CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool isTailCall = false); 122 123 const X86InstrInfo *getInstrInfo() const { 124 return getTargetMachine()->getInstrInfo(); 125 } 126 const X86TargetMachine *getTargetMachine() const { 127 return static_cast<const X86TargetMachine *>(&TM); 128 } 129 130 unsigned TargetMaterializeConstant(Constant *C); 131 132 unsigned TargetMaterializeAlloca(AllocaInst *C); 133 134 /// isScalarFPTypeInSSEReg - Return true if the specified scalar FP type is 135 /// computed in an SSE register, not on the X87 floating point stack. 136 bool isScalarFPTypeInSSEReg(EVT VT) const { 137 return (VT == MVT::f64 && X86ScalarSSEf64) || // f64 is when SSE2 138 (VT == MVT::f32 && X86ScalarSSEf32); // f32 is when SSE1 139 } 140 141 bool isTypeLegal(const Type *Ty, EVT &VT, bool AllowI1 = false); 142}; 143 144} // end anonymous namespace. 145 146bool X86FastISel::isTypeLegal(const Type *Ty, EVT &VT, bool AllowI1) { 147 VT = TLI.getValueType(Ty, /*HandleUnknown=*/true); 148 if (VT == MVT::Other || !VT.isSimple()) 149 // Unhandled type. Halt "fast" selection and bail. 150 return false; 151 152 // For now, require SSE/SSE2 for performing floating-point operations, 153 // since x87 requires additional work. 154 if (VT == MVT::f64 && !X86ScalarSSEf64) 155 return false; 156 if (VT == MVT::f32 && !X86ScalarSSEf32) 157 return false; 158 // Similarly, no f80 support yet. 159 if (VT == MVT::f80) 160 return false; 161 // We only handle legal types. For example, on x86-32 the instruction 162 // selector contains all of the 64-bit instructions from x86-64, 163 // under the assumption that i64 won't be used if the target doesn't 164 // support it. 165 return (AllowI1 && VT == MVT::i1) || TLI.isTypeLegal(VT); 166} 167 168#include "X86GenCallingConv.inc" 169 170/// CCAssignFnForCall - Selects the correct CCAssignFn for a given calling 171/// convention. 172CCAssignFn *X86FastISel::CCAssignFnForCall(CallingConv::ID CC, 173 bool isTaillCall) { 174 if (Subtarget->is64Bit()) { 175 if (Subtarget->isTargetWin64()) 176 return CC_X86_Win64_C; 177 else 178 return CC_X86_64_C; 179 } 180 181 if (CC == CallingConv::X86_FastCall) 182 return CC_X86_32_FastCall; 183 else if (CC == CallingConv::Fast) 184 return CC_X86_32_FastCC; 185 else 186 return CC_X86_32_C; 187} 188 189/// X86FastEmitLoad - Emit a machine instruction to load a value of type VT. 190/// The address is either pre-computed, i.e. Ptr, or a GlobalAddress, i.e. GV. 191/// Return true and the result register by reference if it is possible. 192bool X86FastISel::X86FastEmitLoad(EVT VT, const X86AddressMode &AM, 193 unsigned &ResultReg) { 194 // Get opcode and regclass of the output for the given load instruction. 195 unsigned Opc = 0; 196 const TargetRegisterClass *RC = NULL; 197 switch (VT.getSimpleVT().SimpleTy) { 198 default: return false; 199 case MVT::i1: 200 case MVT::i8: 201 Opc = X86::MOV8rm; 202 RC = X86::GR8RegisterClass; 203 break; 204 case MVT::i16: 205 Opc = X86::MOV16rm; 206 RC = X86::GR16RegisterClass; 207 break; 208 case MVT::i32: 209 Opc = X86::MOV32rm; 210 RC = X86::GR32RegisterClass; 211 break; 212 case MVT::i64: 213 // Must be in x86-64 mode. 214 Opc = X86::MOV64rm; 215 RC = X86::GR64RegisterClass; 216 break; 217 case MVT::f32: 218 if (Subtarget->hasSSE1()) { 219 Opc = X86::MOVSSrm; 220 RC = X86::FR32RegisterClass; 221 } else { 222 Opc = X86::LD_Fp32m; 223 RC = X86::RFP32RegisterClass; 224 } 225 break; 226 case MVT::f64: 227 if (Subtarget->hasSSE2()) { 228 Opc = X86::MOVSDrm; 229 RC = X86::FR64RegisterClass; 230 } else { 231 Opc = X86::LD_Fp64m; 232 RC = X86::RFP64RegisterClass; 233 } 234 break; 235 case MVT::f80: 236 // No f80 support yet. 237 return false; 238 } 239 240 ResultReg = createResultReg(RC); 241 addFullAddress(BuildMI(MBB, DL, TII.get(Opc), ResultReg), AM); 242 return true; 243} 244 245/// X86FastEmitStore - Emit a machine instruction to store a value Val of 246/// type VT. The address is either pre-computed, consisted of a base ptr, Ptr 247/// and a displacement offset, or a GlobalAddress, 248/// i.e. V. Return true if it is possible. 249bool 250X86FastISel::X86FastEmitStore(EVT VT, unsigned Val, 251 const X86AddressMode &AM) { 252 // Get opcode and regclass of the output for the given store instruction. 253 unsigned Opc = 0; 254 switch (VT.getSimpleVT().SimpleTy) { 255 case MVT::f80: // No f80 support yet. 256 default: return false; 257 case MVT::i1: { 258 // Mask out all but lowest bit. 259 unsigned AndResult = createResultReg(X86::GR8RegisterClass); 260 BuildMI(MBB, DL, 261 TII.get(X86::AND8ri), AndResult).addReg(Val).addImm(1); 262 Val = AndResult; 263 } 264 // FALLTHROUGH, handling i1 as i8. 265 case MVT::i8: Opc = X86::MOV8mr; break; 266 case MVT::i16: Opc = X86::MOV16mr; break; 267 case MVT::i32: Opc = X86::MOV32mr; break; 268 case MVT::i64: Opc = X86::MOV64mr; break; // Must be in x86-64 mode. 269 case MVT::f32: 270 Opc = Subtarget->hasSSE1() ? X86::MOVSSmr : X86::ST_Fp32m; 271 break; 272 case MVT::f64: 273 Opc = Subtarget->hasSSE2() ? X86::MOVSDmr : X86::ST_Fp64m; 274 break; 275 } 276 277 addFullAddress(BuildMI(MBB, DL, TII.get(Opc)), AM).addReg(Val); 278 return true; 279} 280 281bool X86FastISel::X86FastEmitStore(EVT VT, Value *Val, 282 const X86AddressMode &AM) { 283 // Handle 'null' like i32/i64 0. 284 if (isa<ConstantPointerNull>(Val)) 285 Val = Constant::getNullValue(TD.getIntPtrType(Val->getContext())); 286 287 // If this is a store of a simple constant, fold the constant into the store. 288 if (ConstantInt *CI = dyn_cast<ConstantInt>(Val)) { 289 unsigned Opc = 0; 290 bool Signed = true; 291 switch (VT.getSimpleVT().SimpleTy) { 292 default: break; 293 case MVT::i1: Signed = false; // FALLTHROUGH to handle as i8. 294 case MVT::i8: Opc = X86::MOV8mi; break; 295 case MVT::i16: Opc = X86::MOV16mi; break; 296 case MVT::i32: Opc = X86::MOV32mi; break; 297 case MVT::i64: 298 // Must be a 32-bit sign extended value. 299 if ((int)CI->getSExtValue() == CI->getSExtValue()) 300 Opc = X86::MOV64mi32; 301 break; 302 } 303 304 if (Opc) { 305 addFullAddress(BuildMI(MBB, DL, TII.get(Opc)), AM) 306 .addImm(Signed ? CI->getSExtValue() : 307 CI->getZExtValue()); 308 return true; 309 } 310 } 311 312 unsigned ValReg = getRegForValue(Val); 313 if (ValReg == 0) 314 return false; 315 316 return X86FastEmitStore(VT, ValReg, AM); 317} 318 319/// X86FastEmitExtend - Emit a machine instruction to extend a value Src of 320/// type SrcVT to type DstVT using the specified extension opcode Opc (e.g. 321/// ISD::SIGN_EXTEND). 322bool X86FastISel::X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT, 323 unsigned Src, EVT SrcVT, 324 unsigned &ResultReg) { 325 unsigned RR = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Opc, Src); 326 327 if (RR != 0) { 328 ResultReg = RR; 329 return true; 330 } else 331 return false; 332} 333 334/// X86SelectAddress - Attempt to fill in an address from the given value. 335/// 336bool X86FastISel::X86SelectAddress(Value *V, X86AddressMode &AM) { 337 User *U = NULL; 338 unsigned Opcode = Instruction::UserOp1; 339 if (Instruction *I = dyn_cast<Instruction>(V)) { 340 Opcode = I->getOpcode(); 341 U = I; 342 } else if (ConstantExpr *C = dyn_cast<ConstantExpr>(V)) { 343 Opcode = C->getOpcode(); 344 U = C; 345 } 346 347 switch (Opcode) { 348 default: break; 349 case Instruction::BitCast: 350 // Look past bitcasts. 351 return X86SelectAddress(U->getOperand(0), AM); 352 353 case Instruction::IntToPtr: 354 // Look past no-op inttoptrs. 355 if (TLI.getValueType(U->getOperand(0)->getType()) == TLI.getPointerTy()) 356 return X86SelectAddress(U->getOperand(0), AM); 357 break; 358 359 case Instruction::PtrToInt: 360 // Look past no-op ptrtoints. 361 if (TLI.getValueType(U->getType()) == TLI.getPointerTy()) 362 return X86SelectAddress(U->getOperand(0), AM); 363 break; 364 365 case Instruction::Alloca: { 366 // Do static allocas. 367 const AllocaInst *A = cast<AllocaInst>(V); 368 DenseMap<const AllocaInst*, int>::iterator SI = StaticAllocaMap.find(A); 369 if (SI != StaticAllocaMap.end()) { 370 AM.BaseType = X86AddressMode::FrameIndexBase; 371 AM.Base.FrameIndex = SI->second; 372 return true; 373 } 374 break; 375 } 376 377 case Instruction::Add: { 378 // Adds of constants are common and easy enough. 379 if (ConstantInt *CI = dyn_cast<ConstantInt>(U->getOperand(1))) { 380 uint64_t Disp = (int32_t)AM.Disp + (uint64_t)CI->getSExtValue(); 381 // They have to fit in the 32-bit signed displacement field though. 382 if (isInt32(Disp)) { 383 AM.Disp = (uint32_t)Disp; 384 return X86SelectAddress(U->getOperand(0), AM); 385 } 386 } 387 break; 388 } 389 390 case Instruction::GetElementPtr: { 391 X86AddressMode SavedAM = AM; 392 393 // Pattern-match simple GEPs. 394 uint64_t Disp = (int32_t)AM.Disp; 395 unsigned IndexReg = AM.IndexReg; 396 unsigned Scale = AM.Scale; 397 gep_type_iterator GTI = gep_type_begin(U); 398 // Iterate through the indices, folding what we can. Constants can be 399 // folded, and one dynamic index can be handled, if the scale is supported. 400 for (User::op_iterator i = U->op_begin() + 1, e = U->op_end(); 401 i != e; ++i, ++GTI) { 402 Value *Op = *i; 403 if (const StructType *STy = dyn_cast<StructType>(*GTI)) { 404 const StructLayout *SL = TD.getStructLayout(STy); 405 unsigned Idx = cast<ConstantInt>(Op)->getZExtValue(); 406 Disp += SL->getElementOffset(Idx); 407 } else { 408 uint64_t S = TD.getTypeAllocSize(GTI.getIndexedType()); 409 if (ConstantInt *CI = dyn_cast<ConstantInt>(Op)) { 410 // Constant-offset addressing. 411 Disp += CI->getSExtValue() * S; 412 } else if (IndexReg == 0 && 413 (!AM.GV || !Subtarget->isPICStyleRIPRel()) && 414 (S == 1 || S == 2 || S == 4 || S == 8)) { 415 // Scaled-index addressing. 416 Scale = S; 417 IndexReg = getRegForGEPIndex(Op); 418 if (IndexReg == 0) 419 return false; 420 } else 421 // Unsupported. 422 goto unsupported_gep; 423 } 424 } 425 // Check for displacement overflow. 426 if (!isInt32(Disp)) 427 break; 428 // Ok, the GEP indices were covered by constant-offset and scaled-index 429 // addressing. Update the address state and move on to examining the base. 430 AM.IndexReg = IndexReg; 431 AM.Scale = Scale; 432 AM.Disp = (uint32_t)Disp; 433 if (X86SelectAddress(U->getOperand(0), AM)) 434 return true; 435 436 // If we couldn't merge the sub value into this addr mode, revert back to 437 // our address and just match the value instead of completely failing. 438 AM = SavedAM; 439 break; 440 unsupported_gep: 441 // Ok, the GEP indices weren't all covered. 442 break; 443 } 444 } 445 446 // Handle constant address. 447 if (GlobalValue *GV = dyn_cast<GlobalValue>(V)) { 448 // Can't handle alternate code models yet. 449 if (TM.getCodeModel() != CodeModel::Small) 450 return false; 451 452 // RIP-relative addresses can't have additional register operands. 453 if (Subtarget->isPICStyleRIPRel() && 454 (AM.Base.Reg != 0 || AM.IndexReg != 0)) 455 return false; 456 457 // Can't handle TLS yet. 458 if (GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV)) 459 if (GVar->isThreadLocal()) 460 return false; 461 462 // Okay, we've committed to selecting this global. Set up the basic address. 463 AM.GV = GV; 464 465 // Allow the subtarget to classify the global. 466 unsigned char GVFlags = Subtarget->ClassifyGlobalReference(GV, TM); 467 468 // If this reference is relative to the pic base, set it now. 469 if (isGlobalRelativeToPICBase(GVFlags)) { 470 // FIXME: How do we know Base.Reg is free?? 471 AM.Base.Reg = getInstrInfo()->getGlobalBaseReg(&MF); 472 } 473 474 // Unless the ABI requires an extra load, return a direct reference to 475 // the global. 476 if (!isGlobalStubReference(GVFlags)) { 477 if (Subtarget->isPICStyleRIPRel()) { 478 // Use rip-relative addressing if we can. Above we verified that the 479 // base and index registers are unused. 480 assert(AM.Base.Reg == 0 && AM.IndexReg == 0); 481 AM.Base.Reg = X86::RIP; 482 } 483 AM.GVOpFlags = GVFlags; 484 return true; 485 } 486 487 // Ok, we need to do a load from a stub. If we've already loaded from this 488 // stub, reuse the loaded pointer, otherwise emit the load now. 489 DenseMap<const Value*, unsigned>::iterator I = LocalValueMap.find(V); 490 unsigned LoadReg; 491 if (I != LocalValueMap.end() && I->second != 0) { 492 LoadReg = I->second; 493 } else { 494 // Issue load from stub. 495 unsigned Opc = 0; 496 const TargetRegisterClass *RC = NULL; 497 X86AddressMode StubAM; 498 StubAM.Base.Reg = AM.Base.Reg; 499 StubAM.GV = GV; 500 StubAM.GVOpFlags = GVFlags; 501 502 if (TLI.getPointerTy() == MVT::i64) { 503 Opc = X86::MOV64rm; 504 RC = X86::GR64RegisterClass; 505 506 if (Subtarget->isPICStyleRIPRel()) 507 StubAM.Base.Reg = X86::RIP; 508 } else { 509 Opc = X86::MOV32rm; 510 RC = X86::GR32RegisterClass; 511 } 512 513 LoadReg = createResultReg(RC); 514 addFullAddress(BuildMI(MBB, DL, TII.get(Opc), LoadReg), StubAM); 515 516 // Prevent loading GV stub multiple times in same MBB. 517 LocalValueMap[V] = LoadReg; 518 } 519 520 // Now construct the final address. Note that the Disp, Scale, 521 // and Index values may already be set here. 522 AM.Base.Reg = LoadReg; 523 AM.GV = 0; 524 return true; 525 } 526 527 // If all else fails, try to materialize the value in a register. 528 if (!AM.GV || !Subtarget->isPICStyleRIPRel()) { 529 if (AM.Base.Reg == 0) { 530 AM.Base.Reg = getRegForValue(V); 531 return AM.Base.Reg != 0; 532 } 533 if (AM.IndexReg == 0) { 534 assert(AM.Scale == 1 && "Scale with no index!"); 535 AM.IndexReg = getRegForValue(V); 536 return AM.IndexReg != 0; 537 } 538 } 539 540 return false; 541} 542 543/// X86SelectCallAddress - Attempt to fill in an address from the given value. 544/// 545bool X86FastISel::X86SelectCallAddress(Value *V, X86AddressMode &AM) { 546 User *U = NULL; 547 unsigned Opcode = Instruction::UserOp1; 548 if (Instruction *I = dyn_cast<Instruction>(V)) { 549 Opcode = I->getOpcode(); 550 U = I; 551 } else if (ConstantExpr *C = dyn_cast<ConstantExpr>(V)) { 552 Opcode = C->getOpcode(); 553 U = C; 554 } 555 556 switch (Opcode) { 557 default: break; 558 case Instruction::BitCast: 559 // Look past bitcasts. 560 return X86SelectCallAddress(U->getOperand(0), AM); 561 562 case Instruction::IntToPtr: 563 // Look past no-op inttoptrs. 564 if (TLI.getValueType(U->getOperand(0)->getType()) == TLI.getPointerTy()) 565 return X86SelectCallAddress(U->getOperand(0), AM); 566 break; 567 568 case Instruction::PtrToInt: 569 // Look past no-op ptrtoints. 570 if (TLI.getValueType(U->getType()) == TLI.getPointerTy()) 571 return X86SelectCallAddress(U->getOperand(0), AM); 572 break; 573 } 574 575 // Handle constant address. 576 if (GlobalValue *GV = dyn_cast<GlobalValue>(V)) { 577 // Can't handle alternate code models yet. 578 if (TM.getCodeModel() != CodeModel::Small) 579 return false; 580 581 // RIP-relative addresses can't have additional register operands. 582 if (Subtarget->isPICStyleRIPRel() && 583 (AM.Base.Reg != 0 || AM.IndexReg != 0)) 584 return false; 585 586 // Can't handle TLS or DLLImport. 587 if (GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV)) 588 if (GVar->isThreadLocal() || GVar->hasDLLImportLinkage()) 589 return false; 590 591 // Okay, we've committed to selecting this global. Set up the basic address. 592 AM.GV = GV; 593 594 // No ABI requires an extra load for anything other than DLLImport, which 595 // we rejected above. Return a direct reference to the global. 596 if (Subtarget->isPICStyleRIPRel()) { 597 // Use rip-relative addressing if we can. Above we verified that the 598 // base and index registers are unused. 599 assert(AM.Base.Reg == 0 && AM.IndexReg == 0); 600 AM.Base.Reg = X86::RIP; 601 } else if (Subtarget->isPICStyleStubPIC()) { 602 AM.GVOpFlags = X86II::MO_PIC_BASE_OFFSET; 603 } else if (Subtarget->isPICStyleGOT()) { 604 AM.GVOpFlags = X86II::MO_GOTOFF; 605 } 606 607 return true; 608 } 609 610 // If all else fails, try to materialize the value in a register. 611 if (!AM.GV || !Subtarget->isPICStyleRIPRel()) { 612 if (AM.Base.Reg == 0) { 613 AM.Base.Reg = getRegForValue(V); 614 return AM.Base.Reg != 0; 615 } 616 if (AM.IndexReg == 0) { 617 assert(AM.Scale == 1 && "Scale with no index!"); 618 AM.IndexReg = getRegForValue(V); 619 return AM.IndexReg != 0; 620 } 621 } 622 623 return false; 624} 625 626 627/// X86SelectStore - Select and emit code to implement store instructions. 628bool X86FastISel::X86SelectStore(Instruction* I) { 629 EVT VT; 630 if (!isTypeLegal(I->getOperand(0)->getType(), VT, /*AllowI1=*/true)) 631 return false; 632 633 X86AddressMode AM; 634 if (!X86SelectAddress(I->getOperand(1), AM)) 635 return false; 636 637 return X86FastEmitStore(VT, I->getOperand(0), AM); 638} 639 640/// X86SelectLoad - Select and emit code to implement load instructions. 641/// 642bool X86FastISel::X86SelectLoad(Instruction *I) { 643 EVT VT; 644 if (!isTypeLegal(I->getType(), VT, /*AllowI1=*/true)) 645 return false; 646 647 X86AddressMode AM; 648 if (!X86SelectAddress(I->getOperand(0), AM)) 649 return false; 650 651 unsigned ResultReg = 0; 652 if (X86FastEmitLoad(VT, AM, ResultReg)) { 653 UpdateValueMap(I, ResultReg); 654 return true; 655 } 656 return false; 657} 658 659static unsigned X86ChooseCmpOpcode(EVT VT) { 660 switch (VT.getSimpleVT().SimpleTy) { 661 default: return 0; 662 case MVT::i8: return X86::CMP8rr; 663 case MVT::i16: return X86::CMP16rr; 664 case MVT::i32: return X86::CMP32rr; 665 case MVT::i64: return X86::CMP64rr; 666 case MVT::f32: return X86::UCOMISSrr; 667 case MVT::f64: return X86::UCOMISDrr; 668 } 669} 670 671/// X86ChooseCmpImmediateOpcode - If we have a comparison with RHS as the RHS 672/// of the comparison, return an opcode that works for the compare (e.g. 673/// CMP32ri) otherwise return 0. 674static unsigned X86ChooseCmpImmediateOpcode(EVT VT, ConstantInt *RHSC) { 675 switch (VT.getSimpleVT().SimpleTy) { 676 // Otherwise, we can't fold the immediate into this comparison. 677 default: return 0; 678 case MVT::i8: return X86::CMP8ri; 679 case MVT::i16: return X86::CMP16ri; 680 case MVT::i32: return X86::CMP32ri; 681 case MVT::i64: 682 // 64-bit comparisons are only valid if the immediate fits in a 32-bit sext 683 // field. 684 if ((int)RHSC->getSExtValue() == RHSC->getSExtValue()) 685 return X86::CMP64ri32; 686 return 0; 687 } 688} 689 690bool X86FastISel::X86FastEmitCompare(Value *Op0, Value *Op1, EVT VT) { 691 unsigned Op0Reg = getRegForValue(Op0); 692 if (Op0Reg == 0) return false; 693 694 // Handle 'null' like i32/i64 0. 695 if (isa<ConstantPointerNull>(Op1)) 696 Op1 = Constant::getNullValue(TD.getIntPtrType(Op0->getContext())); 697 698 // We have two options: compare with register or immediate. If the RHS of 699 // the compare is an immediate that we can fold into this compare, use 700 // CMPri, otherwise use CMPrr. 701 if (ConstantInt *Op1C = dyn_cast<ConstantInt>(Op1)) { 702 if (unsigned CompareImmOpc = X86ChooseCmpImmediateOpcode(VT, Op1C)) { 703 BuildMI(MBB, DL, TII.get(CompareImmOpc)).addReg(Op0Reg) 704 .addImm(Op1C->getSExtValue()); 705 return true; 706 } 707 } 708 709 unsigned CompareOpc = X86ChooseCmpOpcode(VT); 710 if (CompareOpc == 0) return false; 711 712 unsigned Op1Reg = getRegForValue(Op1); 713 if (Op1Reg == 0) return false; 714 BuildMI(MBB, DL, TII.get(CompareOpc)).addReg(Op0Reg).addReg(Op1Reg); 715 716 return true; 717} 718 719bool X86FastISel::X86SelectCmp(Instruction *I) { 720 CmpInst *CI = cast<CmpInst>(I); 721 722 EVT VT; 723 if (!isTypeLegal(I->getOperand(0)->getType(), VT)) 724 return false; 725 726 unsigned ResultReg = createResultReg(&X86::GR8RegClass); 727 unsigned SetCCOpc; 728 bool SwapArgs; // false -> compare Op0, Op1. true -> compare Op1, Op0. 729 switch (CI->getPredicate()) { 730 case CmpInst::FCMP_OEQ: { 731 if (!X86FastEmitCompare(CI->getOperand(0), CI->getOperand(1), VT)) 732 return false; 733 734 unsigned EReg = createResultReg(&X86::GR8RegClass); 735 unsigned NPReg = createResultReg(&X86::GR8RegClass); 736 BuildMI(MBB, DL, TII.get(X86::SETEr), EReg); 737 BuildMI(MBB, DL, TII.get(X86::SETNPr), NPReg); 738 BuildMI(MBB, DL, 739 TII.get(X86::AND8rr), ResultReg).addReg(NPReg).addReg(EReg); 740 UpdateValueMap(I, ResultReg); 741 return true; 742 } 743 case CmpInst::FCMP_UNE: { 744 if (!X86FastEmitCompare(CI->getOperand(0), CI->getOperand(1), VT)) 745 return false; 746 747 unsigned NEReg = createResultReg(&X86::GR8RegClass); 748 unsigned PReg = createResultReg(&X86::GR8RegClass); 749 BuildMI(MBB, DL, TII.get(X86::SETNEr), NEReg); 750 BuildMI(MBB, DL, TII.get(X86::SETPr), PReg); 751 BuildMI(MBB, DL, TII.get(X86::OR8rr), ResultReg).addReg(PReg).addReg(NEReg); 752 UpdateValueMap(I, ResultReg); 753 return true; 754 } 755 case CmpInst::FCMP_OGT: SwapArgs = false; SetCCOpc = X86::SETAr; break; 756 case CmpInst::FCMP_OGE: SwapArgs = false; SetCCOpc = X86::SETAEr; break; 757 case CmpInst::FCMP_OLT: SwapArgs = true; SetCCOpc = X86::SETAr; break; 758 case CmpInst::FCMP_OLE: SwapArgs = true; SetCCOpc = X86::SETAEr; break; 759 case CmpInst::FCMP_ONE: SwapArgs = false; SetCCOpc = X86::SETNEr; break; 760 case CmpInst::FCMP_ORD: SwapArgs = false; SetCCOpc = X86::SETNPr; break; 761 case CmpInst::FCMP_UNO: SwapArgs = false; SetCCOpc = X86::SETPr; break; 762 case CmpInst::FCMP_UEQ: SwapArgs = false; SetCCOpc = X86::SETEr; break; 763 case CmpInst::FCMP_UGT: SwapArgs = true; SetCCOpc = X86::SETBr; break; 764 case CmpInst::FCMP_UGE: SwapArgs = true; SetCCOpc = X86::SETBEr; break; 765 case CmpInst::FCMP_ULT: SwapArgs = false; SetCCOpc = X86::SETBr; break; 766 case CmpInst::FCMP_ULE: SwapArgs = false; SetCCOpc = X86::SETBEr; break; 767 768 case CmpInst::ICMP_EQ: SwapArgs = false; SetCCOpc = X86::SETEr; break; 769 case CmpInst::ICMP_NE: SwapArgs = false; SetCCOpc = X86::SETNEr; break; 770 case CmpInst::ICMP_UGT: SwapArgs = false; SetCCOpc = X86::SETAr; break; 771 case CmpInst::ICMP_UGE: SwapArgs = false; SetCCOpc = X86::SETAEr; break; 772 case CmpInst::ICMP_ULT: SwapArgs = false; SetCCOpc = X86::SETBr; break; 773 case CmpInst::ICMP_ULE: SwapArgs = false; SetCCOpc = X86::SETBEr; break; 774 case CmpInst::ICMP_SGT: SwapArgs = false; SetCCOpc = X86::SETGr; break; 775 case CmpInst::ICMP_SGE: SwapArgs = false; SetCCOpc = X86::SETGEr; break; 776 case CmpInst::ICMP_SLT: SwapArgs = false; SetCCOpc = X86::SETLr; break; 777 case CmpInst::ICMP_SLE: SwapArgs = false; SetCCOpc = X86::SETLEr; break; 778 default: 779 return false; 780 } 781 782 Value *Op0 = CI->getOperand(0), *Op1 = CI->getOperand(1); 783 if (SwapArgs) 784 std::swap(Op0, Op1); 785 786 // Emit a compare of Op0/Op1. 787 if (!X86FastEmitCompare(Op0, Op1, VT)) 788 return false; 789 790 BuildMI(MBB, DL, TII.get(SetCCOpc), ResultReg); 791 UpdateValueMap(I, ResultReg); 792 return true; 793} 794 795bool X86FastISel::X86SelectZExt(Instruction *I) { 796 // Handle zero-extension from i1 to i8, which is common. 797 if (I->getType()->isIntegerTy(8) && 798 I->getOperand(0)->getType()->isIntegerTy(1)) { 799 unsigned ResultReg = getRegForValue(I->getOperand(0)); 800 if (ResultReg == 0) return false; 801 // Set the high bits to zero. 802 ResultReg = FastEmitZExtFromI1(MVT::i8, ResultReg); 803 if (ResultReg == 0) return false; 804 UpdateValueMap(I, ResultReg); 805 return true; 806 } 807 808 return false; 809} 810 811 812bool X86FastISel::X86SelectBranch(Instruction *I) { 813 // Unconditional branches are selected by tablegen-generated code. 814 // Handle a conditional branch. 815 BranchInst *BI = cast<BranchInst>(I); 816 MachineBasicBlock *TrueMBB = MBBMap[BI->getSuccessor(0)]; 817 MachineBasicBlock *FalseMBB = MBBMap[BI->getSuccessor(1)]; 818 819 // Fold the common case of a conditional branch with a comparison. 820 if (CmpInst *CI = dyn_cast<CmpInst>(BI->getCondition())) { 821 if (CI->hasOneUse()) { 822 EVT VT = TLI.getValueType(CI->getOperand(0)->getType()); 823 824 // Try to take advantage of fallthrough opportunities. 825 CmpInst::Predicate Predicate = CI->getPredicate(); 826 if (MBB->isLayoutSuccessor(TrueMBB)) { 827 std::swap(TrueMBB, FalseMBB); 828 Predicate = CmpInst::getInversePredicate(Predicate); 829 } 830 831 bool SwapArgs; // false -> compare Op0, Op1. true -> compare Op1, Op0. 832 unsigned BranchOpc; // Opcode to jump on, e.g. "X86::JA" 833 834 switch (Predicate) { 835 case CmpInst::FCMP_OEQ: 836 std::swap(TrueMBB, FalseMBB); 837 Predicate = CmpInst::FCMP_UNE; 838 // FALL THROUGH 839 case CmpInst::FCMP_UNE: SwapArgs = false; BranchOpc = X86::JNE_4; break; 840 case CmpInst::FCMP_OGT: SwapArgs = false; BranchOpc = X86::JA_4; break; 841 case CmpInst::FCMP_OGE: SwapArgs = false; BranchOpc = X86::JAE_4; break; 842 case CmpInst::FCMP_OLT: SwapArgs = true; BranchOpc = X86::JA_4; break; 843 case CmpInst::FCMP_OLE: SwapArgs = true; BranchOpc = X86::JAE_4; break; 844 case CmpInst::FCMP_ONE: SwapArgs = false; BranchOpc = X86::JNE_4; break; 845 case CmpInst::FCMP_ORD: SwapArgs = false; BranchOpc = X86::JNP_4; break; 846 case CmpInst::FCMP_UNO: SwapArgs = false; BranchOpc = X86::JP_4; break; 847 case CmpInst::FCMP_UEQ: SwapArgs = false; BranchOpc = X86::JE_4; break; 848 case CmpInst::FCMP_UGT: SwapArgs = true; BranchOpc = X86::JB_4; break; 849 case CmpInst::FCMP_UGE: SwapArgs = true; BranchOpc = X86::JBE_4; break; 850 case CmpInst::FCMP_ULT: SwapArgs = false; BranchOpc = X86::JB_4; break; 851 case CmpInst::FCMP_ULE: SwapArgs = false; BranchOpc = X86::JBE_4; break; 852 853 case CmpInst::ICMP_EQ: SwapArgs = false; BranchOpc = X86::JE_4; break; 854 case CmpInst::ICMP_NE: SwapArgs = false; BranchOpc = X86::JNE_4; break; 855 case CmpInst::ICMP_UGT: SwapArgs = false; BranchOpc = X86::JA_4; break; 856 case CmpInst::ICMP_UGE: SwapArgs = false; BranchOpc = X86::JAE_4; break; 857 case CmpInst::ICMP_ULT: SwapArgs = false; BranchOpc = X86::JB_4; break; 858 case CmpInst::ICMP_ULE: SwapArgs = false; BranchOpc = X86::JBE_4; break; 859 case CmpInst::ICMP_SGT: SwapArgs = false; BranchOpc = X86::JG_4; break; 860 case CmpInst::ICMP_SGE: SwapArgs = false; BranchOpc = X86::JGE_4; break; 861 case CmpInst::ICMP_SLT: SwapArgs = false; BranchOpc = X86::JL_4; break; 862 case CmpInst::ICMP_SLE: SwapArgs = false; BranchOpc = X86::JLE_4; break; 863 default: 864 return false; 865 } 866 867 Value *Op0 = CI->getOperand(0), *Op1 = CI->getOperand(1); 868 if (SwapArgs) 869 std::swap(Op0, Op1); 870 871 // Emit a compare of the LHS and RHS, setting the flags. 872 if (!X86FastEmitCompare(Op0, Op1, VT)) 873 return false; 874 875 BuildMI(MBB, DL, TII.get(BranchOpc)).addMBB(TrueMBB); 876 877 if (Predicate == CmpInst::FCMP_UNE) { 878 // X86 requires a second branch to handle UNE (and OEQ, 879 // which is mapped to UNE above). 880 BuildMI(MBB, DL, TII.get(X86::JP_4)).addMBB(TrueMBB); 881 } 882 883 FastEmitBranch(FalseMBB); 884 MBB->addSuccessor(TrueMBB); 885 return true; 886 } 887 } else if (ExtractValueInst *EI = 888 dyn_cast<ExtractValueInst>(BI->getCondition())) { 889 // Check to see if the branch instruction is from an "arithmetic with 890 // overflow" intrinsic. The main way these intrinsics are used is: 891 // 892 // %t = call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 %v1, i32 %v2) 893 // %sum = extractvalue { i32, i1 } %t, 0 894 // %obit = extractvalue { i32, i1 } %t, 1 895 // br i1 %obit, label %overflow, label %normal 896 // 897 // The %sum and %obit are converted in an ADD and a SETO/SETB before 898 // reaching the branch. Therefore, we search backwards through the MBB 899 // looking for the SETO/SETB instruction. If an instruction modifies the 900 // EFLAGS register before we reach the SETO/SETB instruction, then we can't 901 // convert the branch into a JO/JB instruction. 902 if (IntrinsicInst *CI = dyn_cast<IntrinsicInst>(EI->getAggregateOperand())){ 903 if (CI->getIntrinsicID() == Intrinsic::sadd_with_overflow || 904 CI->getIntrinsicID() == Intrinsic::uadd_with_overflow) { 905 const MachineInstr *SetMI = 0; 906 unsigned Reg = lookUpRegForValue(EI); 907 908 for (MachineBasicBlock::const_reverse_iterator 909 RI = MBB->rbegin(), RE = MBB->rend(); RI != RE; ++RI) { 910 const MachineInstr &MI = *RI; 911 912 if (MI.modifiesRegister(Reg)) { 913 unsigned Src, Dst, SrcSR, DstSR; 914 915 if (getInstrInfo()->isMoveInstr(MI, Src, Dst, SrcSR, DstSR)) { 916 Reg = Src; 917 continue; 918 } 919 920 SetMI = &MI; 921 break; 922 } 923 924 const TargetInstrDesc &TID = MI.getDesc(); 925 if (TID.hasUnmodeledSideEffects() || 926 TID.hasImplicitDefOfPhysReg(X86::EFLAGS)) 927 break; 928 } 929 930 if (SetMI) { 931 unsigned OpCode = SetMI->getOpcode(); 932 933 if (OpCode == X86::SETOr || OpCode == X86::SETBr) { 934 BuildMI(MBB, DL, TII.get(OpCode == X86::SETOr ? 935 X86::JO_4 : X86::JB_4)) 936 .addMBB(TrueMBB); 937 FastEmitBranch(FalseMBB); 938 MBB->addSuccessor(TrueMBB); 939 return true; 940 } 941 } 942 } 943 } 944 } 945 946 // Otherwise do a clumsy setcc and re-test it. 947 unsigned OpReg = getRegForValue(BI->getCondition()); 948 if (OpReg == 0) return false; 949 950 BuildMI(MBB, DL, TII.get(X86::TEST8rr)).addReg(OpReg).addReg(OpReg); 951 BuildMI(MBB, DL, TII.get(X86::JNE_4)).addMBB(TrueMBB); 952 FastEmitBranch(FalseMBB); 953 MBB->addSuccessor(TrueMBB); 954 return true; 955} 956 957bool X86FastISel::X86SelectShift(Instruction *I) { 958 unsigned CReg = 0, OpReg = 0, OpImm = 0; 959 const TargetRegisterClass *RC = NULL; 960 if (I->getType()->isIntegerTy(8)) { 961 CReg = X86::CL; 962 RC = &X86::GR8RegClass; 963 switch (I->getOpcode()) { 964 case Instruction::LShr: OpReg = X86::SHR8rCL; OpImm = X86::SHR8ri; break; 965 case Instruction::AShr: OpReg = X86::SAR8rCL; OpImm = X86::SAR8ri; break; 966 case Instruction::Shl: OpReg = X86::SHL8rCL; OpImm = X86::SHL8ri; break; 967 default: return false; 968 } 969 } else if (I->getType()->isIntegerTy(16)) { 970 CReg = X86::CX; 971 RC = &X86::GR16RegClass; 972 switch (I->getOpcode()) { 973 case Instruction::LShr: OpReg = X86::SHR16rCL; OpImm = X86::SHR16ri; break; 974 case Instruction::AShr: OpReg = X86::SAR16rCL; OpImm = X86::SAR16ri; break; 975 case Instruction::Shl: OpReg = X86::SHL16rCL; OpImm = X86::SHL16ri; break; 976 default: return false; 977 } 978 } else if (I->getType()->isIntegerTy(32)) { 979 CReg = X86::ECX; 980 RC = &X86::GR32RegClass; 981 switch (I->getOpcode()) { 982 case Instruction::LShr: OpReg = X86::SHR32rCL; OpImm = X86::SHR32ri; break; 983 case Instruction::AShr: OpReg = X86::SAR32rCL; OpImm = X86::SAR32ri; break; 984 case Instruction::Shl: OpReg = X86::SHL32rCL; OpImm = X86::SHL32ri; break; 985 default: return false; 986 } 987 } else if (I->getType()->isIntegerTy(64)) { 988 CReg = X86::RCX; 989 RC = &X86::GR64RegClass; 990 switch (I->getOpcode()) { 991 case Instruction::LShr: OpReg = X86::SHR64rCL; OpImm = X86::SHR64ri; break; 992 case Instruction::AShr: OpReg = X86::SAR64rCL; OpImm = X86::SAR64ri; break; 993 case Instruction::Shl: OpReg = X86::SHL64rCL; OpImm = X86::SHL64ri; break; 994 default: return false; 995 } 996 } else { 997 return false; 998 } 999 1000 EVT VT = TLI.getValueType(I->getType(), /*HandleUnknown=*/true); 1001 if (VT == MVT::Other || !isTypeLegal(I->getType(), VT)) 1002 return false; 1003 1004 unsigned Op0Reg = getRegForValue(I->getOperand(0)); 1005 if (Op0Reg == 0) return false; 1006 1007 // Fold immediate in shl(x,3). 1008 if (ConstantInt *CI = dyn_cast<ConstantInt>(I->getOperand(1))) { 1009 unsigned ResultReg = createResultReg(RC); 1010 BuildMI(MBB, DL, TII.get(OpImm), 1011 ResultReg).addReg(Op0Reg).addImm(CI->getZExtValue() & 0xff); 1012 UpdateValueMap(I, ResultReg); 1013 return true; 1014 } 1015 1016 unsigned Op1Reg = getRegForValue(I->getOperand(1)); 1017 if (Op1Reg == 0) return false; 1018 TII.copyRegToReg(*MBB, MBB->end(), CReg, Op1Reg, RC, RC); 1019 1020 // The shift instruction uses X86::CL. If we defined a super-register 1021 // of X86::CL, emit an EXTRACT_SUBREG to precisely describe what 1022 // we're doing here. 1023 if (CReg != X86::CL) 1024 BuildMI(MBB, DL, TII.get(TargetOpcode::EXTRACT_SUBREG), X86::CL) 1025 .addReg(CReg).addImm(X86::SUBREG_8BIT); 1026 1027 unsigned ResultReg = createResultReg(RC); 1028 BuildMI(MBB, DL, TII.get(OpReg), ResultReg).addReg(Op0Reg); 1029 UpdateValueMap(I, ResultReg); 1030 return true; 1031} 1032 1033bool X86FastISel::X86SelectSelect(Instruction *I) { 1034 EVT VT = TLI.getValueType(I->getType(), /*HandleUnknown=*/true); 1035 if (VT == MVT::Other || !isTypeLegal(I->getType(), VT)) 1036 return false; 1037 1038 unsigned Opc = 0; 1039 const TargetRegisterClass *RC = NULL; 1040 if (VT.getSimpleVT() == MVT::i16) { 1041 Opc = X86::CMOVE16rr; 1042 RC = &X86::GR16RegClass; 1043 } else if (VT.getSimpleVT() == MVT::i32) { 1044 Opc = X86::CMOVE32rr; 1045 RC = &X86::GR32RegClass; 1046 } else if (VT.getSimpleVT() == MVT::i64) { 1047 Opc = X86::CMOVE64rr; 1048 RC = &X86::GR64RegClass; 1049 } else { 1050 return false; 1051 } 1052 1053 unsigned Op0Reg = getRegForValue(I->getOperand(0)); 1054 if (Op0Reg == 0) return false; 1055 unsigned Op1Reg = getRegForValue(I->getOperand(1)); 1056 if (Op1Reg == 0) return false; 1057 unsigned Op2Reg = getRegForValue(I->getOperand(2)); 1058 if (Op2Reg == 0) return false; 1059 1060 BuildMI(MBB, DL, TII.get(X86::TEST8rr)).addReg(Op0Reg).addReg(Op0Reg); 1061 unsigned ResultReg = createResultReg(RC); 1062 BuildMI(MBB, DL, TII.get(Opc), ResultReg).addReg(Op1Reg).addReg(Op2Reg); 1063 UpdateValueMap(I, ResultReg); 1064 return true; 1065} 1066 1067bool X86FastISel::X86SelectFPExt(Instruction *I) { 1068 // fpext from float to double. 1069 if (Subtarget->hasSSE2() && 1070 I->getType()->isDoubleTy()) { 1071 Value *V = I->getOperand(0); 1072 if (V->getType()->isFloatTy()) { 1073 unsigned OpReg = getRegForValue(V); 1074 if (OpReg == 0) return false; 1075 unsigned ResultReg = createResultReg(X86::FR64RegisterClass); 1076 BuildMI(MBB, DL, TII.get(X86::CVTSS2SDrr), ResultReg).addReg(OpReg); 1077 UpdateValueMap(I, ResultReg); 1078 return true; 1079 } 1080 } 1081 1082 return false; 1083} 1084 1085bool X86FastISel::X86SelectFPTrunc(Instruction *I) { 1086 if (Subtarget->hasSSE2()) { 1087 if (I->getType()->isFloatTy()) { 1088 Value *V = I->getOperand(0); 1089 if (V->getType()->isDoubleTy()) { 1090 unsigned OpReg = getRegForValue(V); 1091 if (OpReg == 0) return false; 1092 unsigned ResultReg = createResultReg(X86::FR32RegisterClass); 1093 BuildMI(MBB, DL, TII.get(X86::CVTSD2SSrr), ResultReg).addReg(OpReg); 1094 UpdateValueMap(I, ResultReg); 1095 return true; 1096 } 1097 } 1098 } 1099 1100 return false; 1101} 1102 1103bool X86FastISel::X86SelectTrunc(Instruction *I) { 1104 if (Subtarget->is64Bit()) 1105 // All other cases should be handled by the tblgen generated code. 1106 return false; 1107 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType()); 1108 EVT DstVT = TLI.getValueType(I->getType()); 1109 1110 // This code only handles truncation to byte right now. 1111 if (DstVT != MVT::i8 && DstVT != MVT::i1) 1112 // All other cases should be handled by the tblgen generated code. 1113 return false; 1114 if (SrcVT != MVT::i16 && SrcVT != MVT::i32) 1115 // All other cases should be handled by the tblgen generated code. 1116 return false; 1117 1118 unsigned InputReg = getRegForValue(I->getOperand(0)); 1119 if (!InputReg) 1120 // Unhandled operand. Halt "fast" selection and bail. 1121 return false; 1122 1123 // First issue a copy to GR16_ABCD or GR32_ABCD. 1124 unsigned CopyOpc = (SrcVT == MVT::i16) ? X86::MOV16rr : X86::MOV32rr; 1125 const TargetRegisterClass *CopyRC = (SrcVT == MVT::i16) 1126 ? X86::GR16_ABCDRegisterClass : X86::GR32_ABCDRegisterClass; 1127 unsigned CopyReg = createResultReg(CopyRC); 1128 BuildMI(MBB, DL, TII.get(CopyOpc), CopyReg).addReg(InputReg); 1129 1130 // Then issue an extract_subreg. 1131 unsigned ResultReg = FastEmitInst_extractsubreg(MVT::i8, 1132 CopyReg, X86::SUBREG_8BIT); 1133 if (!ResultReg) 1134 return false; 1135 1136 UpdateValueMap(I, ResultReg); 1137 return true; 1138} 1139 1140bool X86FastISel::X86SelectExtractValue(Instruction *I) { 1141 ExtractValueInst *EI = cast<ExtractValueInst>(I); 1142 Value *Agg = EI->getAggregateOperand(); 1143 1144 if (IntrinsicInst *CI = dyn_cast<IntrinsicInst>(Agg)) { 1145 switch (CI->getIntrinsicID()) { 1146 default: break; 1147 case Intrinsic::sadd_with_overflow: 1148 case Intrinsic::uadd_with_overflow: 1149 // Cheat a little. We know that the registers for "add" and "seto" are 1150 // allocated sequentially. However, we only keep track of the register 1151 // for "add" in the value map. Use extractvalue's index to get the 1152 // correct register for "seto". 1153 UpdateValueMap(I, lookUpRegForValue(Agg) + *EI->idx_begin()); 1154 return true; 1155 } 1156 } 1157 1158 return false; 1159} 1160 1161bool X86FastISel::X86VisitIntrinsicCall(IntrinsicInst &I) { 1162 // FIXME: Handle more intrinsics. 1163 switch (I.getIntrinsicID()) { 1164 default: return false; 1165 case Intrinsic::dbg_declare: { 1166 DbgDeclareInst *DI = cast<DbgDeclareInst>(&I); 1167 X86AddressMode AM; 1168 assert(DI->getAddress() && "Null address should be checked earlier!"); 1169 if (!X86SelectAddress(DI->getAddress(), AM)) 1170 return false; 1171 const TargetInstrDesc &II = TII.get(TargetOpcode::DBG_VALUE); 1172 // FIXME may need to add RegState::Debug to any registers produced, 1173 // although ESP/EBP should be the only ones at the moment. 1174 addFullAddress(BuildMI(MBB, DL, II), AM).addImm(0). 1175 addMetadata(DI->getVariable()); 1176 return true; 1177 } 1178 case Intrinsic::trap: { 1179 BuildMI(MBB, DL, TII.get(X86::TRAP)); 1180 return true; 1181 } 1182 case Intrinsic::sadd_with_overflow: 1183 case Intrinsic::uadd_with_overflow: { 1184 // Replace "add with overflow" intrinsics with an "add" instruction followed 1185 // by a seto/setc instruction. Later on, when the "extractvalue" 1186 // instructions are encountered, we use the fact that two registers were 1187 // created sequentially to get the correct registers for the "sum" and the 1188 // "overflow bit". 1189 const Function *Callee = I.getCalledFunction(); 1190 const Type *RetTy = 1191 cast<StructType>(Callee->getReturnType())->getTypeAtIndex(unsigned(0)); 1192 1193 EVT VT; 1194 if (!isTypeLegal(RetTy, VT)) 1195 return false; 1196 1197 Value *Op1 = I.getOperand(1); 1198 Value *Op2 = I.getOperand(2); 1199 unsigned Reg1 = getRegForValue(Op1); 1200 unsigned Reg2 = getRegForValue(Op2); 1201 1202 if (Reg1 == 0 || Reg2 == 0) 1203 // FIXME: Handle values *not* in registers. 1204 return false; 1205 1206 unsigned OpC = 0; 1207 if (VT == MVT::i32) 1208 OpC = X86::ADD32rr; 1209 else if (VT == MVT::i64) 1210 OpC = X86::ADD64rr; 1211 else 1212 return false; 1213 1214 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT)); 1215 BuildMI(MBB, DL, TII.get(OpC), ResultReg).addReg(Reg1).addReg(Reg2); 1216 unsigned DestReg1 = UpdateValueMap(&I, ResultReg); 1217 1218 // If the add with overflow is an intra-block value then we just want to 1219 // create temporaries for it like normal. If it is a cross-block value then 1220 // UpdateValueMap will return the cross-block register used. Since we 1221 // *really* want the value to be live in the register pair known by 1222 // UpdateValueMap, we have to use DestReg1+1 as the destination register in 1223 // the cross block case. In the non-cross-block case, we should just make 1224 // another register for the value. 1225 if (DestReg1 != ResultReg) 1226 ResultReg = DestReg1+1; 1227 else 1228 ResultReg = createResultReg(TLI.getRegClassFor(MVT::i8)); 1229 1230 unsigned Opc = X86::SETBr; 1231 if (I.getIntrinsicID() == Intrinsic::sadd_with_overflow) 1232 Opc = X86::SETOr; 1233 BuildMI(MBB, DL, TII.get(Opc), ResultReg); 1234 return true; 1235 } 1236 } 1237} 1238 1239bool X86FastISel::X86SelectCall(Instruction *I) { 1240 CallInst *CI = cast<CallInst>(I); 1241 Value *Callee = I->getOperand(0); 1242 1243 // Can't handle inline asm yet. 1244 if (isa<InlineAsm>(Callee)) 1245 return false; 1246 1247 // Handle intrinsic calls. 1248 if (IntrinsicInst *II = dyn_cast<IntrinsicInst>(CI)) 1249 return X86VisitIntrinsicCall(*II); 1250 1251 // Handle only C and fastcc calling conventions for now. 1252 CallSite CS(CI); 1253 CallingConv::ID CC = CS.getCallingConv(); 1254 if (CC != CallingConv::C && 1255 CC != CallingConv::Fast && 1256 CC != CallingConv::X86_FastCall) 1257 return false; 1258 1259 // fastcc with -tailcallopt is intended to provide a guaranteed 1260 // tail call optimization. Fastisel doesn't know how to do that. 1261 if (CC == CallingConv::Fast && GuaranteedTailCallOpt) 1262 return false; 1263 1264 // Let SDISel handle vararg functions. 1265 const PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType()); 1266 const FunctionType *FTy = cast<FunctionType>(PT->getElementType()); 1267 if (FTy->isVarArg()) 1268 return false; 1269 1270 // Handle *simple* calls for now. 1271 const Type *RetTy = CS.getType(); 1272 EVT RetVT; 1273 if (RetTy->isVoidTy()) 1274 RetVT = MVT::isVoid; 1275 else if (!isTypeLegal(RetTy, RetVT, true)) 1276 return false; 1277 1278 // Materialize callee address in a register. FIXME: GV address can be 1279 // handled with a CALLpcrel32 instead. 1280 X86AddressMode CalleeAM; 1281 if (!X86SelectCallAddress(Callee, CalleeAM)) 1282 return false; 1283 unsigned CalleeOp = 0; 1284 GlobalValue *GV = 0; 1285 if (CalleeAM.GV != 0) { 1286 GV = CalleeAM.GV; 1287 } else if (CalleeAM.Base.Reg != 0) { 1288 CalleeOp = CalleeAM.Base.Reg; 1289 } else 1290 return false; 1291 1292 // Allow calls which produce i1 results. 1293 bool AndToI1 = false; 1294 if (RetVT == MVT::i1) { 1295 RetVT = MVT::i8; 1296 AndToI1 = true; 1297 } 1298 1299 // Deal with call operands first. 1300 SmallVector<Value*, 8> ArgVals; 1301 SmallVector<unsigned, 8> Args; 1302 SmallVector<EVT, 8> ArgVTs; 1303 SmallVector<ISD::ArgFlagsTy, 8> ArgFlags; 1304 Args.reserve(CS.arg_size()); 1305 ArgVals.reserve(CS.arg_size()); 1306 ArgVTs.reserve(CS.arg_size()); 1307 ArgFlags.reserve(CS.arg_size()); 1308 for (CallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end(); 1309 i != e; ++i) { 1310 unsigned Arg = getRegForValue(*i); 1311 if (Arg == 0) 1312 return false; 1313 ISD::ArgFlagsTy Flags; 1314 unsigned AttrInd = i - CS.arg_begin() + 1; 1315 if (CS.paramHasAttr(AttrInd, Attribute::SExt)) 1316 Flags.setSExt(); 1317 if (CS.paramHasAttr(AttrInd, Attribute::ZExt)) 1318 Flags.setZExt(); 1319 1320 // FIXME: Only handle *easy* calls for now. 1321 if (CS.paramHasAttr(AttrInd, Attribute::InReg) || 1322 CS.paramHasAttr(AttrInd, Attribute::StructRet) || 1323 CS.paramHasAttr(AttrInd, Attribute::Nest) || 1324 CS.paramHasAttr(AttrInd, Attribute::ByVal)) 1325 return false; 1326 1327 const Type *ArgTy = (*i)->getType(); 1328 EVT ArgVT; 1329 if (!isTypeLegal(ArgTy, ArgVT)) 1330 return false; 1331 unsigned OriginalAlignment = TD.getABITypeAlignment(ArgTy); 1332 Flags.setOrigAlign(OriginalAlignment); 1333 1334 Args.push_back(Arg); 1335 ArgVals.push_back(*i); 1336 ArgVTs.push_back(ArgVT); 1337 ArgFlags.push_back(Flags); 1338 } 1339 1340 // Analyze operands of the call, assigning locations to each operand. 1341 SmallVector<CCValAssign, 16> ArgLocs; 1342 CCState CCInfo(CC, false, TM, ArgLocs, I->getParent()->getContext()); 1343 CCInfo.AnalyzeCallOperands(ArgVTs, ArgFlags, CCAssignFnForCall(CC)); 1344 1345 // Get a count of how many bytes are to be pushed on the stack. 1346 unsigned NumBytes = CCInfo.getNextStackOffset(); 1347 1348 // Issue CALLSEQ_START 1349 unsigned AdjStackDown = TM.getRegisterInfo()->getCallFrameSetupOpcode(); 1350 BuildMI(MBB, DL, TII.get(AdjStackDown)).addImm(NumBytes); 1351 1352 // Process argument: walk the register/memloc assignments, inserting 1353 // copies / loads. 1354 SmallVector<unsigned, 4> RegArgs; 1355 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 1356 CCValAssign &VA = ArgLocs[i]; 1357 unsigned Arg = Args[VA.getValNo()]; 1358 EVT ArgVT = ArgVTs[VA.getValNo()]; 1359 1360 // Promote the value if needed. 1361 switch (VA.getLocInfo()) { 1362 default: llvm_unreachable("Unknown loc info!"); 1363 case CCValAssign::Full: break; 1364 case CCValAssign::SExt: { 1365 bool Emitted = X86FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(), 1366 Arg, ArgVT, Arg); 1367 assert(Emitted && "Failed to emit a sext!"); Emitted=Emitted; 1368 Emitted = true; 1369 ArgVT = VA.getLocVT(); 1370 break; 1371 } 1372 case CCValAssign::ZExt: { 1373 bool Emitted = X86FastEmitExtend(ISD::ZERO_EXTEND, VA.getLocVT(), 1374 Arg, ArgVT, Arg); 1375 assert(Emitted && "Failed to emit a zext!"); Emitted=Emitted; 1376 Emitted = true; 1377 ArgVT = VA.getLocVT(); 1378 break; 1379 } 1380 case CCValAssign::AExt: { 1381 bool Emitted = X86FastEmitExtend(ISD::ANY_EXTEND, VA.getLocVT(), 1382 Arg, ArgVT, Arg); 1383 if (!Emitted) 1384 Emitted = X86FastEmitExtend(ISD::ZERO_EXTEND, VA.getLocVT(), 1385 Arg, ArgVT, Arg); 1386 if (!Emitted) 1387 Emitted = X86FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(), 1388 Arg, ArgVT, Arg); 1389 1390 assert(Emitted && "Failed to emit a aext!"); Emitted=Emitted; 1391 ArgVT = VA.getLocVT(); 1392 break; 1393 } 1394 case CCValAssign::BCvt: { 1395 unsigned BC = FastEmit_r(ArgVT.getSimpleVT(), VA.getLocVT().getSimpleVT(), 1396 ISD::BIT_CONVERT, Arg); 1397 assert(BC != 0 && "Failed to emit a bitcast!"); 1398 Arg = BC; 1399 ArgVT = VA.getLocVT(); 1400 break; 1401 } 1402 } 1403 1404 if (VA.isRegLoc()) { 1405 TargetRegisterClass* RC = TLI.getRegClassFor(ArgVT); 1406 bool Emitted = TII.copyRegToReg(*MBB, MBB->end(), VA.getLocReg(), 1407 Arg, RC, RC); 1408 assert(Emitted && "Failed to emit a copy instruction!"); Emitted=Emitted; 1409 Emitted = true; 1410 RegArgs.push_back(VA.getLocReg()); 1411 } else { 1412 unsigned LocMemOffset = VA.getLocMemOffset(); 1413 X86AddressMode AM; 1414 AM.Base.Reg = StackPtr; 1415 AM.Disp = LocMemOffset; 1416 Value *ArgVal = ArgVals[VA.getValNo()]; 1417 1418 // If this is a really simple value, emit this with the Value* version of 1419 // X86FastEmitStore. If it isn't simple, we don't want to do this, as it 1420 // can cause us to reevaluate the argument. 1421 if (isa<ConstantInt>(ArgVal) || isa<ConstantPointerNull>(ArgVal)) 1422 X86FastEmitStore(ArgVT, ArgVal, AM); 1423 else 1424 X86FastEmitStore(ArgVT, Arg, AM); 1425 } 1426 } 1427 1428 // ELF / PIC requires GOT in the EBX register before function calls via PLT 1429 // GOT pointer. 1430 if (Subtarget->isPICStyleGOT()) { 1431 TargetRegisterClass *RC = X86::GR32RegisterClass; 1432 unsigned Base = getInstrInfo()->getGlobalBaseReg(&MF); 1433 bool Emitted = TII.copyRegToReg(*MBB, MBB->end(), X86::EBX, Base, RC, RC); 1434 assert(Emitted && "Failed to emit a copy instruction!"); Emitted=Emitted; 1435 Emitted = true; 1436 } 1437 1438 // Issue the call. 1439 MachineInstrBuilder MIB; 1440 if (CalleeOp) { 1441 // Register-indirect call. 1442 unsigned CallOpc = Subtarget->is64Bit() ? X86::CALL64r : X86::CALL32r; 1443 MIB = BuildMI(MBB, DL, TII.get(CallOpc)).addReg(CalleeOp); 1444 1445 } else { 1446 // Direct call. 1447 assert(GV && "Not a direct call"); 1448 unsigned CallOpc = 1449 Subtarget->is64Bit() ? X86::CALL64pcrel32 : X86::CALLpcrel32; 1450 1451 // See if we need any target-specific flags on the GV operand. 1452 unsigned char OpFlags = 0; 1453 1454 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to 1455 // external symbols most go through the PLT in PIC mode. If the symbol 1456 // has hidden or protected visibility, or if it is static or local, then 1457 // we don't need to use the PLT - we can directly call it. 1458 if (Subtarget->isTargetELF() && 1459 TM.getRelocationModel() == Reloc::PIC_ && 1460 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) { 1461 OpFlags = X86II::MO_PLT; 1462 } else if (Subtarget->isPICStyleStubAny() && 1463 (GV->isDeclaration() || GV->isWeakForLinker()) && 1464 Subtarget->getDarwinVers() < 9) { 1465 // PC-relative references to external symbols should go through $stub, 1466 // unless we're building with the leopard linker or later, which 1467 // automatically synthesizes these stubs. 1468 OpFlags = X86II::MO_DARWIN_STUB; 1469 } 1470 1471 1472 MIB = BuildMI(MBB, DL, TII.get(CallOpc)).addGlobalAddress(GV, 0, OpFlags); 1473 } 1474 1475 // Add an implicit use GOT pointer in EBX. 1476 if (Subtarget->isPICStyleGOT()) 1477 MIB.addReg(X86::EBX); 1478 1479 // Add implicit physical register uses to the call. 1480 for (unsigned i = 0, e = RegArgs.size(); i != e; ++i) 1481 MIB.addReg(RegArgs[i]); 1482 1483 // Issue CALLSEQ_END 1484 unsigned AdjStackUp = TM.getRegisterInfo()->getCallFrameDestroyOpcode(); 1485 BuildMI(MBB, DL, TII.get(AdjStackUp)).addImm(NumBytes).addImm(0); 1486 1487 // Now handle call return value (if any). 1488 if (RetVT.getSimpleVT().SimpleTy != MVT::isVoid) { 1489 SmallVector<CCValAssign, 16> RVLocs; 1490 CCState CCInfo(CC, false, TM, RVLocs, I->getParent()->getContext()); 1491 CCInfo.AnalyzeCallResult(RetVT, RetCC_X86); 1492 1493 // Copy all of the result registers out of their specified physreg. 1494 assert(RVLocs.size() == 1 && "Can't handle multi-value calls!"); 1495 EVT CopyVT = RVLocs[0].getValVT(); 1496 TargetRegisterClass* DstRC = TLI.getRegClassFor(CopyVT); 1497 TargetRegisterClass *SrcRC = DstRC; 1498 1499 // If this is a call to a function that returns an fp value on the x87 fp 1500 // stack, but where we prefer to use the value in xmm registers, copy it 1501 // out as F80 and use a truncate to move it from fp stack reg to xmm reg. 1502 if ((RVLocs[0].getLocReg() == X86::ST0 || 1503 RVLocs[0].getLocReg() == X86::ST1) && 1504 isScalarFPTypeInSSEReg(RVLocs[0].getValVT())) { 1505 CopyVT = MVT::f80; 1506 SrcRC = X86::RSTRegisterClass; 1507 DstRC = X86::RFP80RegisterClass; 1508 } 1509 1510 unsigned ResultReg = createResultReg(DstRC); 1511 bool Emitted = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 1512 RVLocs[0].getLocReg(), DstRC, SrcRC); 1513 assert(Emitted && "Failed to emit a copy instruction!"); Emitted=Emitted; 1514 Emitted = true; 1515 if (CopyVT != RVLocs[0].getValVT()) { 1516 // Round the F80 the right size, which also moves to the appropriate xmm 1517 // register. This is accomplished by storing the F80 value in memory and 1518 // then loading it back. Ewww... 1519 EVT ResVT = RVLocs[0].getValVT(); 1520 unsigned Opc = ResVT == MVT::f32 ? X86::ST_Fp80m32 : X86::ST_Fp80m64; 1521 unsigned MemSize = ResVT.getSizeInBits()/8; 1522 int FI = MFI.CreateStackObject(MemSize, MemSize, false); 1523 addFrameReference(BuildMI(MBB, DL, TII.get(Opc)), FI).addReg(ResultReg); 1524 DstRC = ResVT == MVT::f32 1525 ? X86::FR32RegisterClass : X86::FR64RegisterClass; 1526 Opc = ResVT == MVT::f32 ? X86::MOVSSrm : X86::MOVSDrm; 1527 ResultReg = createResultReg(DstRC); 1528 addFrameReference(BuildMI(MBB, DL, TII.get(Opc), ResultReg), FI); 1529 } 1530 1531 if (AndToI1) { 1532 // Mask out all but lowest bit for some call which produces an i1. 1533 unsigned AndResult = createResultReg(X86::GR8RegisterClass); 1534 BuildMI(MBB, DL, 1535 TII.get(X86::AND8ri), AndResult).addReg(ResultReg).addImm(1); 1536 ResultReg = AndResult; 1537 } 1538 1539 UpdateValueMap(I, ResultReg); 1540 } 1541 1542 return true; 1543} 1544 1545 1546bool 1547X86FastISel::TargetSelectInstruction(Instruction *I) { 1548 switch (I->getOpcode()) { 1549 default: break; 1550 case Instruction::Load: 1551 return X86SelectLoad(I); 1552 case Instruction::Store: 1553 return X86SelectStore(I); 1554 case Instruction::ICmp: 1555 case Instruction::FCmp: 1556 return X86SelectCmp(I); 1557 case Instruction::ZExt: 1558 return X86SelectZExt(I); 1559 case Instruction::Br: 1560 return X86SelectBranch(I); 1561 case Instruction::Call: 1562 return X86SelectCall(I); 1563 case Instruction::LShr: 1564 case Instruction::AShr: 1565 case Instruction::Shl: 1566 return X86SelectShift(I); 1567 case Instruction::Select: 1568 return X86SelectSelect(I); 1569 case Instruction::Trunc: 1570 return X86SelectTrunc(I); 1571 case Instruction::FPExt: 1572 return X86SelectFPExt(I); 1573 case Instruction::FPTrunc: 1574 return X86SelectFPTrunc(I); 1575 case Instruction::ExtractValue: 1576 return X86SelectExtractValue(I); 1577 case Instruction::IntToPtr: // Deliberate fall-through. 1578 case Instruction::PtrToInt: { 1579 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType()); 1580 EVT DstVT = TLI.getValueType(I->getType()); 1581 if (DstVT.bitsGT(SrcVT)) 1582 return X86SelectZExt(I); 1583 if (DstVT.bitsLT(SrcVT)) 1584 return X86SelectTrunc(I); 1585 unsigned Reg = getRegForValue(I->getOperand(0)); 1586 if (Reg == 0) return false; 1587 UpdateValueMap(I, Reg); 1588 return true; 1589 } 1590 } 1591 1592 return false; 1593} 1594 1595unsigned X86FastISel::TargetMaterializeConstant(Constant *C) { 1596 EVT VT; 1597 if (!isTypeLegal(C->getType(), VT)) 1598 return false; 1599 1600 // Get opcode and regclass of the output for the given load instruction. 1601 unsigned Opc = 0; 1602 const TargetRegisterClass *RC = NULL; 1603 switch (VT.getSimpleVT().SimpleTy) { 1604 default: return false; 1605 case MVT::i8: 1606 Opc = X86::MOV8rm; 1607 RC = X86::GR8RegisterClass; 1608 break; 1609 case MVT::i16: 1610 Opc = X86::MOV16rm; 1611 RC = X86::GR16RegisterClass; 1612 break; 1613 case MVT::i32: 1614 Opc = X86::MOV32rm; 1615 RC = X86::GR32RegisterClass; 1616 break; 1617 case MVT::i64: 1618 // Must be in x86-64 mode. 1619 Opc = X86::MOV64rm; 1620 RC = X86::GR64RegisterClass; 1621 break; 1622 case MVT::f32: 1623 if (Subtarget->hasSSE1()) { 1624 Opc = X86::MOVSSrm; 1625 RC = X86::FR32RegisterClass; 1626 } else { 1627 Opc = X86::LD_Fp32m; 1628 RC = X86::RFP32RegisterClass; 1629 } 1630 break; 1631 case MVT::f64: 1632 if (Subtarget->hasSSE2()) { 1633 Opc = X86::MOVSDrm; 1634 RC = X86::FR64RegisterClass; 1635 } else { 1636 Opc = X86::LD_Fp64m; 1637 RC = X86::RFP64RegisterClass; 1638 } 1639 break; 1640 case MVT::f80: 1641 // No f80 support yet. 1642 return false; 1643 } 1644 1645 // Materialize addresses with LEA instructions. 1646 if (isa<GlobalValue>(C)) { 1647 X86AddressMode AM; 1648 if (X86SelectAddress(C, AM)) { 1649 if (TLI.getPointerTy() == MVT::i32) 1650 Opc = X86::LEA32r; 1651 else 1652 Opc = X86::LEA64r; 1653 unsigned ResultReg = createResultReg(RC); 1654 addLeaAddress(BuildMI(MBB, DL, TII.get(Opc), ResultReg), AM); 1655 return ResultReg; 1656 } 1657 return 0; 1658 } 1659 1660 // MachineConstantPool wants an explicit alignment. 1661 unsigned Align = TD.getPrefTypeAlignment(C->getType()); 1662 if (Align == 0) { 1663 // Alignment of vector types. FIXME! 1664 Align = TD.getTypeAllocSize(C->getType()); 1665 } 1666 1667 // x86-32 PIC requires a PIC base register for constant pools. 1668 unsigned PICBase = 0; 1669 unsigned char OpFlag = 0; 1670 if (Subtarget->isPICStyleStubPIC()) { // Not dynamic-no-pic 1671 OpFlag = X86II::MO_PIC_BASE_OFFSET; 1672 PICBase = getInstrInfo()->getGlobalBaseReg(&MF); 1673 } else if (Subtarget->isPICStyleGOT()) { 1674 OpFlag = X86II::MO_GOTOFF; 1675 PICBase = getInstrInfo()->getGlobalBaseReg(&MF); 1676 } else if (Subtarget->isPICStyleRIPRel() && 1677 TM.getCodeModel() == CodeModel::Small) { 1678 PICBase = X86::RIP; 1679 } 1680 1681 // Create the load from the constant pool. 1682 unsigned MCPOffset = MCP.getConstantPoolIndex(C, Align); 1683 unsigned ResultReg = createResultReg(RC); 1684 addConstantPoolReference(BuildMI(MBB, DL, TII.get(Opc), ResultReg), 1685 MCPOffset, PICBase, OpFlag); 1686 1687 return ResultReg; 1688} 1689 1690unsigned X86FastISel::TargetMaterializeAlloca(AllocaInst *C) { 1691 // Fail on dynamic allocas. At this point, getRegForValue has already 1692 // checked its CSE maps, so if we're here trying to handle a dynamic 1693 // alloca, we're not going to succeed. X86SelectAddress has a 1694 // check for dynamic allocas, because it's called directly from 1695 // various places, but TargetMaterializeAlloca also needs a check 1696 // in order to avoid recursion between getRegForValue, 1697 // X86SelectAddrss, and TargetMaterializeAlloca. 1698 if (!StaticAllocaMap.count(C)) 1699 return 0; 1700 1701 X86AddressMode AM; 1702 if (!X86SelectAddress(C, AM)) 1703 return 0; 1704 unsigned Opc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r; 1705 TargetRegisterClass* RC = TLI.getRegClassFor(TLI.getPointerTy()); 1706 unsigned ResultReg = createResultReg(RC); 1707 addLeaAddress(BuildMI(MBB, DL, TII.get(Opc), ResultReg), AM); 1708 return ResultReg; 1709} 1710 1711namespace llvm { 1712 llvm::FastISel *X86::createFastISel(MachineFunction &mf, 1713 MachineModuleInfo *mmi, 1714 DwarfWriter *dw, 1715 DenseMap<const Value *, unsigned> &vm, 1716 DenseMap<const BasicBlock *, MachineBasicBlock *> &bm, 1717 DenseMap<const AllocaInst *, int> &am 1718#ifndef NDEBUG 1719 , SmallSet<Instruction*, 8> &cil 1720#endif 1721 ) { 1722 return new X86FastISel(mf, mmi, dw, vm, bm, am 1723#ifndef NDEBUG 1724 , cil 1725#endif 1726 ); 1727 } 1728} 1729