X86MCTargetDesc.h revision 239462
1109001Sbenno//===-- X86MCTargetDesc.h - X86 Target Descriptions -------------*- C++ -*-===// 2109001Sbenno// 3109001Sbenno// The LLVM Compiler Infrastructure 4109001Sbenno// 5109001Sbenno// This file is distributed under the University of Illinois Open Source 6109001Sbenno// License. See LICENSE.TXT for details. 7109001Sbenno// 8109001Sbenno//===----------------------------------------------------------------------===// 9109001Sbenno// 10109001Sbenno// This file provides X86 specific target descriptions. 11109001Sbenno// 12109001Sbenno//===----------------------------------------------------------------------===// 13109001Sbenno 14109001Sbenno#ifndef X86MCTARGETDESC_H 15109001Sbenno#define X86MCTARGETDESC_H 16109001Sbenno 17109001Sbenno#include "llvm/Support/DataTypes.h" 18109001Sbenno#include <string> 19109001Sbenno 20109001Sbennonamespace llvm { 21109001Sbennoclass MCAsmBackend; 22109001Sbennoclass MCCodeEmitter; 23109001Sbennoclass MCContext; 24109001Sbennoclass MCInstrInfo; 25109001Sbennoclass MCObjectWriter; 26109001Sbennoclass MCRegisterInfo; 27109001Sbennoclass MCSubtargetInfo; 28227843Smariusclass Target; 29227843Smariusclass StringRef; 30227843Smariusclass raw_ostream; 31109001Sbenno 32256816Snwhitehornextern Target TheX86_32Target, TheX86_64Target; 33131102Sgrehan 34109001Sbenno/// DWARFFlavour - Flavour of dwarf regnumbers 35109001Sbenno/// 36109001Sbennonamespace DWARFFlavour { 37109001Sbenno enum { 38109001Sbenno X86_64 = 0, X86_32_DarwinEH = 1, X86_32_Generic = 2 39109001Sbenno }; 40183882Snwhitehorn} 41186128Snwhitehorn 42109001Sbenno/// N86 namespace - Native X86 register numbers 43119291Simp/// 44119291Simpnamespace N86 { 45119291Simp enum { 46109001Sbenno EAX = 0, ECX = 1, EDX = 2, EBX = 3, ESP = 4, EBP = 5, ESI = 6, EDI = 7 47209298Snwhitehorn }; 48209298Snwhitehorn} 49109001Sbenno 50109001Sbennonamespace X86_MC { 51109001Sbenno std::string ParseX86Triple(StringRef TT); 52109001Sbenno 53183882Snwhitehorn /// GetCpuIDAndInfo - Execute the specified cpuid and return the 4 values in 54186128Snwhitehorn /// the specified arguments. If we can't run cpuid on the host, return true. 55186128Snwhitehorn bool GetCpuIDAndInfo(unsigned value, unsigned *rEAX, 56109001Sbenno unsigned *rEBX, unsigned *rECX, unsigned *rEDX); 57109001Sbenno /// GetCpuIDAndInfoEx - Execute the specified cpuid with subleaf and return 58109001Sbenno /// the 4 values in the specified arguments. If we can't run cpuid on the 59109001Sbenno /// host, return true. 60231046Snwhitehorn bool GetCpuIDAndInfoEx(unsigned value, unsigned subleaf, unsigned *rEAX, 61109001Sbenno unsigned *rEBX, unsigned *rECX, unsigned *rEDX); 62109001Sbenno 63186128Snwhitehorn void DetectFamilyModel(unsigned EAX, unsigned &Family, unsigned &Model); 64109001Sbenno 65183882Snwhitehorn unsigned getDwarfRegFlavour(StringRef TT, bool isEH); 66227843Smarius 67183882Snwhitehorn unsigned getX86RegNum(unsigned RegNo); 68227843Smarius 69109001Sbenno void InitLLVM2SEHRegisterMapping(MCRegisterInfo *MRI); 70109001Sbenno 71154079Sjhb /// createX86MCSubtargetInfo - Create a X86 MCSubtargetInfo instance. 72109001Sbenno /// This is exposed so Asm parser, etc. do not need to go through 73186128Snwhitehorn /// TargetRegistry. 74186128Snwhitehorn MCSubtargetInfo *createX86MCSubtargetInfo(StringRef TT, StringRef CPU, 75186128Snwhitehorn StringRef FS); 76186128Snwhitehorn} 77186128Snwhitehorn 78186128SnwhitehornMCCodeEmitter *createX86MCCodeEmitter(const MCInstrInfo &MCII, 79186128Snwhitehorn const MCRegisterInfo &MRI, 80186128Snwhitehorn const MCSubtargetInfo &STI, 81186128Snwhitehorn MCContext &Ctx); 82186128Snwhitehorn 83186128SnwhitehornMCAsmBackend *createX86_32AsmBackend(const Target &T, StringRef TT); 84231046SnwhitehornMCAsmBackend *createX86_64AsmBackend(const Target &T, StringRef TT); 85231046Snwhitehorn 86109001Sbenno/// createX86MachObjectWriter - Construct an X86 Mach-O object writer. 87109001SbennoMCObjectWriter *createX86MachObjectWriter(raw_ostream &OS, 88109001Sbenno bool Is64Bit, 89109001Sbenno uint32_t CPUType, 90109001Sbenno uint32_t CPUSubtype); 91109001Sbenno 92109001Sbenno/// createX86ELFObjectWriter - Construct an X86 ELF object writer. 93109001SbennoMCObjectWriter *createX86ELFObjectWriter(raw_ostream &OS, 94109001Sbenno bool Is64Bit, 95109001Sbenno uint8_t OSABI); 96183882Snwhitehorn/// createX86WinCOFFObjectWriter - Construct an X86 Win COFF object writer. 97233018SnwhitehornMCObjectWriter *createX86WinCOFFObjectWriter(raw_ostream &OS, bool Is64Bit); 98109001Sbenno} // End llvm namespace 99109001Sbenno 100183882Snwhitehorn 101183882Snwhitehorn// Defines symbolic names for X86 registers. This defines a mapping from 102109001Sbenno// register name to register number. 103109001Sbenno// 104109001Sbenno#define GET_REGINFO_ENUM 105109001Sbenno#include "X86GenRegisterInfo.inc" 106109001Sbenno 107186128Snwhitehorn// Defines symbolic names for the X86 instructions. 108186128Snwhitehorn// 109186128Snwhitehorn#define GET_INSTRINFO_ENUM 110186128Snwhitehorn#include "X86GenInstrInfo.inc" 111186128Snwhitehorn 112186128Snwhitehorn#define GET_SUBTARGETINFO_ENUM 113186128Snwhitehorn#include "X86GenSubtargetInfo.inc" 114186128Snwhitehorn 115186128Snwhitehorn#endif 116109001Sbenno