X86MCTargetDesc.h revision 234353
1224133Sdim//===-- X86MCTargetDesc.h - X86 Target Descriptions -------------*- C++ -*-===// 2224133Sdim// 3224133Sdim// The LLVM Compiler Infrastructure 4224133Sdim// 5224133Sdim// This file is distributed under the University of Illinois Open Source 6224133Sdim// License. See LICENSE.TXT for details. 7224133Sdim// 8224133Sdim//===----------------------------------------------------------------------===// 9224133Sdim// 10224133Sdim// This file provides X86 specific target descriptions. 11224133Sdim// 12224133Sdim//===----------------------------------------------------------------------===// 13224133Sdim 14224133Sdim#ifndef X86MCTARGETDESC_H 15224133Sdim#define X86MCTARGETDESC_H 16224133Sdim 17226633Sdim#include "llvm/Support/DataTypes.h" 18224133Sdim#include <string> 19224133Sdim 20224133Sdimnamespace llvm { 21226633Sdimclass MCAsmBackend; 22226633Sdimclass MCCodeEmitter; 23226633Sdimclass MCContext; 24226633Sdimclass MCInstrInfo; 25226633Sdimclass MCObjectWriter; 26226633Sdimclass MCRegisterInfo; 27224133Sdimclass MCSubtargetInfo; 28224133Sdimclass Target; 29224133Sdimclass StringRef; 30226633Sdimclass raw_ostream; 31224133Sdim 32224133Sdimextern Target TheX86_32Target, TheX86_64Target; 33224133Sdim 34226633Sdim/// DWARFFlavour - Flavour of dwarf regnumbers 35226633Sdim/// 36226633Sdimnamespace DWARFFlavour { 37226633Sdim enum { 38226633Sdim X86_64 = 0, X86_32_DarwinEH = 1, X86_32_Generic = 2 39226633Sdim }; 40226633Sdim} 41226633Sdim 42226633Sdim/// N86 namespace - Native X86 register numbers 43226633Sdim/// 44226633Sdimnamespace N86 { 45226633Sdim enum { 46226633Sdim EAX = 0, ECX = 1, EDX = 2, EBX = 3, ESP = 4, EBP = 5, ESI = 6, EDI = 7 47226633Sdim }; 48226633Sdim} 49226633Sdim 50224133Sdimnamespace X86_MC { 51224133Sdim std::string ParseX86Triple(StringRef TT); 52224133Sdim 53224133Sdim /// GetCpuIDAndInfo - Execute the specified cpuid and return the 4 values in 54224133Sdim /// the specified arguments. If we can't run cpuid on the host, return true. 55224133Sdim bool GetCpuIDAndInfo(unsigned value, unsigned *rEAX, 56224133Sdim unsigned *rEBX, unsigned *rECX, unsigned *rEDX); 57234353Sdim /// GetCpuIDAndInfoEx - Execute the specified cpuid with subleaf and return 58234353Sdim /// the 4 values in the specified arguments. If we can't run cpuid on the 59234353Sdim /// host, return true. 60234353Sdim bool GetCpuIDAndInfoEx(unsigned value, unsigned subleaf, unsigned *rEAX, 61234353Sdim unsigned *rEBX, unsigned *rECX, unsigned *rEDX); 62224133Sdim 63224133Sdim void DetectFamilyModel(unsigned EAX, unsigned &Family, unsigned &Model); 64224133Sdim 65226633Sdim unsigned getDwarfRegFlavour(StringRef TT, bool isEH); 66226633Sdim 67226633Sdim unsigned getX86RegNum(unsigned RegNo); 68226633Sdim 69226633Sdim void InitLLVM2SEHRegisterMapping(MCRegisterInfo *MRI); 70226633Sdim 71226633Sdim /// createX86MCSubtargetInfo - Create a X86 MCSubtargetInfo instance. 72224133Sdim /// This is exposed so Asm parser, etc. do not need to go through 73224133Sdim /// TargetRegistry. 74224133Sdim MCSubtargetInfo *createX86MCSubtargetInfo(StringRef TT, StringRef CPU, 75224133Sdim StringRef FS); 76224133Sdim} 77224133Sdim 78226633SdimMCCodeEmitter *createX86MCCodeEmitter(const MCInstrInfo &MCII, 79226633Sdim const MCSubtargetInfo &STI, 80226633Sdim MCContext &Ctx); 81226633Sdim 82226633SdimMCAsmBackend *createX86_32AsmBackend(const Target &T, StringRef TT); 83226633SdimMCAsmBackend *createX86_64AsmBackend(const Target &T, StringRef TT); 84226633Sdim 85226633Sdim/// createX86MachObjectWriter - Construct an X86 Mach-O object writer. 86226633SdimMCObjectWriter *createX86MachObjectWriter(raw_ostream &OS, 87226633Sdim bool Is64Bit, 88226633Sdim uint32_t CPUType, 89226633Sdim uint32_t CPUSubtype); 90226633Sdim 91234353Sdim/// createX86ELFObjectWriter - Construct an X86 ELF object writer. 92234353SdimMCObjectWriter *createX86ELFObjectWriter(raw_ostream &OS, 93234353Sdim bool Is64Bit, 94234353Sdim uint8_t OSABI); 95234353Sdim/// createX86WinCOFFObjectWriter - Construct an X86 Win COFF object writer. 96234353SdimMCObjectWriter *createX86WinCOFFObjectWriter(raw_ostream &OS, bool Is64Bit); 97224133Sdim} // End llvm namespace 98224133Sdim 99224133Sdim 100224133Sdim// Defines symbolic names for X86 registers. This defines a mapping from 101224133Sdim// register name to register number. 102224133Sdim// 103224133Sdim#define GET_REGINFO_ENUM 104224133Sdim#include "X86GenRegisterInfo.inc" 105224133Sdim 106224133Sdim// Defines symbolic names for the X86 instructions. 107224133Sdim// 108224133Sdim#define GET_INSTRINFO_ENUM 109224133Sdim#include "X86GenInstrInfo.inc" 110224133Sdim 111224133Sdim#define GET_SUBTARGETINFO_ENUM 112224133Sdim#include "X86GenSubtargetInfo.inc" 113224133Sdim 114224133Sdim#endif 115