SystemZInstrInfo.h revision 251607 
1//===-- SystemZInstrInfo.h - SystemZ instruction information ----*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the SystemZ implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_TARGET_SYSTEMZINSTRINFO_H
15#define LLVM_TARGET_SYSTEMZINSTRINFO_H
16
17#include "SystemZ.h"
18#include "SystemZRegisterInfo.h"
19#include "llvm/Target/TargetInstrInfo.h"
20
21#define GET_INSTRINFO_HEADER
22#include "SystemZGenInstrInfo.inc"
23
24namespace llvm {
25
26class SystemZTargetMachine;
27
28namespace SystemZII {
29  enum {
30    // See comments in SystemZInstrFormats.td.
31    SimpleBDXLoad  = (1 << 0),
32    SimpleBDXStore = (1 << 1),
33    Has20BitOffset = (1 << 2),
34    HasIndex       = (1 << 3),
35    Is128Bit       = (1 << 4)
36  };
37  // SystemZ MachineOperand target flags.
38  enum {
39    // Masks out the bits for the access model.
40    MO_SYMBOL_MODIFIER = (1 << 0),
41
42    // @GOT (aka @GOTENT)
43    MO_GOT = (1 << 0)
44  };
45}
46
47class SystemZInstrInfo : public SystemZGenInstrInfo {
48  const SystemZRegisterInfo RI;
49
50  void splitMove(MachineBasicBlock::iterator MI, unsigned NewOpcode) const;
51  void splitAdjDynAlloc(MachineBasicBlock::iterator MI) const;
52
53public:
54  explicit SystemZInstrInfo(SystemZTargetMachine &TM);
55
56  // Override TargetInstrInfo.
57  virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
58                                       int &FrameIndex) const LLVM_OVERRIDE;
59  virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
60                                      int &FrameIndex) const LLVM_OVERRIDE;
61  virtual bool AnalyzeBranch(MachineBasicBlock &MBB,
62                             MachineBasicBlock *&TBB,
63                             MachineBasicBlock *&FBB,
64                             SmallVectorImpl<MachineOperand> &Cond,
65                             bool AllowModify) const LLVM_OVERRIDE;
66  virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const LLVM_OVERRIDE;
67  virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
68                                MachineBasicBlock *FBB,
69                                const SmallVectorImpl<MachineOperand> &Cond,
70                                DebugLoc DL) const LLVM_OVERRIDE;
71  virtual void copyPhysReg(MachineBasicBlock &MBB,
72                           MachineBasicBlock::iterator MBBI, DebugLoc DL,
73                           unsigned DestReg, unsigned SrcReg,
74                           bool KillSrc) const LLVM_OVERRIDE;
75  virtual void
76    storeRegToStackSlot(MachineBasicBlock &MBB,
77                        MachineBasicBlock::iterator MBBI,
78                        unsigned SrcReg, bool isKill, int FrameIndex,
79                        const TargetRegisterClass *RC,
80                        const TargetRegisterInfo *TRI) const LLVM_OVERRIDE;
81  virtual void
82    loadRegFromStackSlot(MachineBasicBlock &MBB,
83                         MachineBasicBlock::iterator MBBI,
84                         unsigned DestReg, int FrameIdx,
85                         const TargetRegisterClass *RC,
86                         const TargetRegisterInfo *TRI) const LLVM_OVERRIDE;
87  virtual bool
88    expandPostRAPseudo(MachineBasicBlock::iterator MBBI) const LLVM_OVERRIDE;
89  virtual bool
90    ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const
91    LLVM_OVERRIDE;
92
93  // Return the SystemZRegisterInfo, which this class owns.
94  const SystemZRegisterInfo &getRegisterInfo() const { return RI; }
95
96  // Return true if MI is a conditional or unconditional branch.
97  // When returning true, set Cond to the mask of condition-code
98  // values on which the instruction will branch, and set Target
99  // to the operand that contains the branch target.  This target
100  // can be a register or a basic block.
101  bool isBranch(const MachineInstr *MI, unsigned &Cond,
102                const MachineOperand *&Target) const;
103
104  // Get the load and store opcodes for a given register class.
105  void getLoadStoreOpcodes(const TargetRegisterClass *RC,
106                           unsigned &LoadOpcode, unsigned &StoreOpcode) const;
107
108  // Opcode is the opcode of an instruction that has an address operand,
109  // and the caller wants to perform that instruction's operation on an
110  // address that has displacement Offset.  Return the opcode of a suitable
111  // instruction (which might be Opcode itself) or 0 if no such instruction
112  // exists.
113  unsigned getOpcodeForOffset(unsigned Opcode, int64_t Offset) const;
114
115  // Emit code before MBBI in MI to move immediate value Value into
116  // physical register Reg.
117  void loadImmediate(MachineBasicBlock &MBB,
118                     MachineBasicBlock::iterator MBBI,
119                     unsigned Reg, uint64_t Value) const;
120};
121} // end namespace llvm
122
123#endif
124