R600RegisterInfo.h revision 249259 
1//===-- R600RegisterInfo.h - R600 Register Info Interface ------*- C++ -*--===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10/// \file
11/// \brief Interface definition for R600RegisterInfo
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef R600REGISTERINFO_H_
16#define R600REGISTERINFO_H_
17
18#include "AMDGPURegisterInfo.h"
19#include "AMDGPUTargetMachine.h"
20
21namespace llvm {
22
23class R600TargetMachine;
24class TargetInstrInfo;
25
26struct R600RegisterInfo : public AMDGPURegisterInfo {
27  AMDGPUTargetMachine &TM;
28  const TargetInstrInfo &TII;
29
30  R600RegisterInfo(AMDGPUTargetMachine &tm, const TargetInstrInfo &tii);
31
32  virtual BitVector getReservedRegs(const MachineFunction &MF) const;
33
34  /// \param RC is an AMDIL reg class.
35  ///
36  /// \returns the R600 reg class that is equivalent to \p RC.
37  virtual const TargetRegisterClass *getISARegClass(
38    const TargetRegisterClass *RC) const;
39
40  /// \brief get the HW encoding for a register's channel.
41  unsigned getHWRegChan(unsigned reg) const;
42
43  /// \brief get the register class of the specified type to use in the
44  /// CFGStructurizer
45  virtual const TargetRegisterClass * getCFGStructurizerRegClass(MVT VT) const;
46
47  /// \returns the sub reg enum value for the given \p Channel
48  /// (e.g. getSubRegFromChannel(0) -> AMDGPU::sel_x)
49  unsigned getSubRegFromChannel(unsigned Channel) const;
50
51};
52
53} // End namespace llvm
54
55#endif // AMDIDSAREGISTERINFO_H_
56