1249259Sdim//===-- R600RegisterInfo.h - R600 Register Info Interface ------*- C++ -*--===// 2249259Sdim// 3249259Sdim// The LLVM Compiler Infrastructure 4249259Sdim// 5249259Sdim// This file is distributed under the University of Illinois Open Source 6249259Sdim// License. See LICENSE.TXT for details. 7249259Sdim// 8249259Sdim//===----------------------------------------------------------------------===// 9249259Sdim// 10249259Sdim/// \file 11249259Sdim/// \brief Interface definition for R600RegisterInfo 12249259Sdim// 13249259Sdim//===----------------------------------------------------------------------===// 14249259Sdim 15249259Sdim#ifndef R600REGISTERINFO_H_ 16249259Sdim#define R600REGISTERINFO_H_ 17249259Sdim 18249259Sdim#include "AMDGPURegisterInfo.h" 19249259Sdim#include "AMDGPUTargetMachine.h" 20249259Sdim 21249259Sdimnamespace llvm { 22249259Sdim 23249259Sdimclass R600TargetMachine; 24249259Sdimclass TargetInstrInfo; 25249259Sdim 26249259Sdimstruct R600RegisterInfo : public AMDGPURegisterInfo { 27249259Sdim AMDGPUTargetMachine &TM; 28249259Sdim const TargetInstrInfo &TII; 29249259Sdim 30249259Sdim R600RegisterInfo(AMDGPUTargetMachine &tm, const TargetInstrInfo &tii); 31249259Sdim 32249259Sdim virtual BitVector getReservedRegs(const MachineFunction &MF) const; 33249259Sdim 34249259Sdim /// \param RC is an AMDIL reg class. 35249259Sdim /// 36249259Sdim /// \returns the R600 reg class that is equivalent to \p RC. 37249259Sdim virtual const TargetRegisterClass *getISARegClass( 38249259Sdim const TargetRegisterClass *RC) const; 39249259Sdim 40249259Sdim /// \brief get the HW encoding for a register's channel. 41249259Sdim unsigned getHWRegChan(unsigned reg) const; 42249259Sdim 43249259Sdim /// \brief get the register class of the specified type to use in the 44249259Sdim /// CFGStructurizer 45249259Sdim virtual const TargetRegisterClass * getCFGStructurizerRegClass(MVT VT) const; 46249259Sdim 47249259Sdim /// \returns the sub reg enum value for the given \p Channel 48249259Sdim /// (e.g. getSubRegFromChannel(0) -> AMDGPU::sel_x) 49249259Sdim unsigned getSubRegFromChannel(unsigned Channel) const; 50249259Sdim 51249259Sdim}; 52249259Sdim 53249259Sdim} // End namespace llvm 54249259Sdim 55249259Sdim#endif // AMDIDSAREGISTERINFO_H_ 56