AMDGPUMCTargetDesc.cpp revision 259065
129415Sjmg//===-- AMDGPUMCTargetDesc.cpp - AMDGPU Target Descriptions ---------------===// 250723Scg// 339899Sluigi// The LLVM Compiler Infrastructure 429415Sjmg// 529415Sjmg// This file is distributed under the University of Illinois Open Source 629415Sjmg// License. See LICENSE.TXT for details. 729415Sjmg// 850723Scg//===----------------------------------------------------------------------===// 950723Scg// 1029415Sjmg/// \file 1129415Sjmg/// \brief This file provides AMDGPU specific target descriptions. 1230869Sjmg// 1330869Sjmg//===----------------------------------------------------------------------===// 1430869Sjmg 1530869Sjmg#include "AMDGPUMCTargetDesc.h" 1650723Scg#include "AMDGPUMCAsmInfo.h" 1750723Scg#include "InstPrinter/AMDGPUInstPrinter.h" 1830869Sjmg#include "llvm/MC/MCCodeGenInfo.h" 1950723Scg#include "llvm/MC/MCInstrInfo.h" 2050723Scg#include "llvm/MC/MCRegisterInfo.h" 2150723Scg#include "llvm/MC/MCStreamer.h" 2250723Scg#include "llvm/MC/MCSubtargetInfo.h" 2350723Scg#include "llvm/MC/MachineLocation.h" 2450723Scg#include "llvm/Support/ErrorHandling.h" 2550723Scg#include "llvm/Support/TargetRegistry.h" 2650723Scg 2750723Scg#define GET_INSTRINFO_MC_DESC 2850723Scg#include "AMDGPUGenInstrInfo.inc" 2950723Scg 3050723Scg#define GET_SUBTARGETINFO_MC_DESC 3150959Speter#include "AMDGPUGenSubtargetInfo.inc" 3229415Sjmg 3329415Sjmg#define GET_REGINFO_MC_DESC 3453465Scg#include "AMDGPUGenRegisterInfo.inc" 3529415Sjmg 3629415Sjmgusing namespace llvm; 3753465Scg 3853553Stanimurastatic MCInstrInfo *createAMDGPUMCInstrInfo() { 3929415Sjmg MCInstrInfo *X = new MCInstrInfo(); 4055706Scg InitAMDGPUMCInstrInfo(X); 4155254Scg return X; 4250723Scg} 4350723Scg 4450723Scgstatic MCRegisterInfo *createAMDGPUMCRegisterInfo(StringRef TT) { 4550723Scg MCRegisterInfo *X = new MCRegisterInfo(); 4650723Scg InitAMDGPUMCRegisterInfo(X, 0); 4750723Scg return X; 4850723Scg} 4950723Scg 5050723Scgstatic MCSubtargetInfo *createAMDGPUMCSubtargetInfo(StringRef TT, StringRef CPU, 5129415Sjmg StringRef FS) { 5264881Scg MCSubtargetInfo * X = new MCSubtargetInfo(); 5350723Scg InitAMDGPUMCSubtargetInfo(X, TT, CPU, FS); 5464881Scg return X; 5550723Scg} 5664881Scg 5729415Sjmgstatic MCCodeGenInfo *createAMDGPUMCCodeGenInfo(StringRef TT, Reloc::Model RM, 5864881Scg CodeModel::Model CM, 5950723Scg CodeGenOpt::Level OL) { 6064881Scg MCCodeGenInfo *X = new MCCodeGenInfo(); 6150723Scg X->InitMCCodeGenInfo(RM, CM, OL); 6264881Scg return X; 6329415Sjmg} 6464881Scg 6564881Scgstatic MCInstPrinter *createAMDGPUMCInstPrinter(const Target &T, 6650723Scg unsigned SyntaxVariant, 6764881Scg const MCAsmInfo &MAI, 6850723Scg const MCInstrInfo &MII, 6964881Scg const MCRegisterInfo &MRI, 7029415Sjmg const MCSubtargetInfo &STI) { 7164881Scg return new AMDGPUInstPrinter(MAI, MII, MRI); 7264881Scg} 7350723Scg 7464881Scgstatic MCCodeEmitter *createAMDGPUMCCodeEmitter(const MCInstrInfo &MCII, 7550723Scg const MCRegisterInfo &MRI, 7664881Scg const MCSubtargetInfo &STI, 7729415Sjmg MCContext &Ctx) { 7864881Scg if (STI.getFeatureBits() & AMDGPU::Feature64BitPtr) { 7964881Scg return createSIMCCodeEmitter(MCII, MRI, STI, Ctx); 8050723Scg } else { 8164881Scg return createR600MCCodeEmitter(MCII, MRI, STI); 8250723Scg } 8364881Scg} 8429415Sjmg 8564881Scgstatic MCStreamer *createMCStreamer(const Target &T, StringRef TT, 8664881Scg MCContext &Ctx, MCAsmBackend &MAB, 8750723Scg raw_ostream &_OS, 8864881Scg MCCodeEmitter *_Emitter, 8950723Scg bool RelaxAll, 9064881Scg bool NoExecStack) { 9129415Sjmg return createELFStreamer(Ctx, MAB, _OS, _Emitter, false, false); 9264881Scg} 9364881Scg 9464881Scgextern "C" void LLVMInitializeR600TargetMC() { 9564881Scg 9664881Scg RegisterMCAsmInfo<AMDGPUMCAsmInfo> Y(TheAMDGPUTarget); 9764881Scg 9854462Scg TargetRegistry::RegisterMCCodeGenInfo(TheAMDGPUTarget, createAMDGPUMCCodeGenInfo); 9964881Scg 10054462Scg TargetRegistry::RegisterMCInstrInfo(TheAMDGPUTarget, createAMDGPUMCInstrInfo); 10150723Scg 10250723Scg TargetRegistry::RegisterMCRegInfo(TheAMDGPUTarget, createAMDGPUMCRegisterInfo); 10350723Scg 10450723Scg TargetRegistry::RegisterMCSubtargetInfo(TheAMDGPUTarget, createAMDGPUMCSubtargetInfo); 10550723Scg 10650723Scg TargetRegistry::RegisterMCInstPrinter(TheAMDGPUTarget, createAMDGPUMCInstPrinter); 10750723Scg 10850723Scg TargetRegistry::RegisterMCCodeEmitter(TheAMDGPUTarget, createAMDGPUMCCodeEmitter); 10950723Scg 11065340Scg TargetRegistry::RegisterMCAsmBackend(TheAMDGPUTarget, createAMDGPUAsmBackend); 11165340Scg 11265340Scg TargetRegistry::RegisterMCObjectStreamer(TheAMDGPUTarget, createMCStreamer); 11365340Scg} 11465340Scg