AMDGPURegisterInfo.cpp revision 256281
1193323Sed//===-- AMDGPURegisterInfo.cpp - AMDGPU Register Information -------------===// 2193323Sed// 3193323Sed// The LLVM Compiler Infrastructure 4193323Sed// 5193323Sed// This file is distributed under the University of Illinois Open Source 6193323Sed// License. See LICENSE.TXT for details. 7193323Sed// 8193323Sed//===----------------------------------------------------------------------===// 9193323Sed// 10193323Sed/// \file 11193323Sed/// \brief Parent TargetRegisterInfo class common to all hw codegen targets. 12193323Sed// 13193323Sed//===----------------------------------------------------------------------===// 14193323Sed 15193323Sed#include "AMDGPURegisterInfo.h" 16193323Sed#include "AMDGPUTargetMachine.h" 17193323Sed 18193323Sedusing namespace llvm; 19193323Sed 20193323SedAMDGPURegisterInfo::AMDGPURegisterInfo(TargetMachine &tm, 21193323Sed const TargetInstrInfo &tii) 22193323Sed: AMDGPUGenRegisterInfo(0), 23193323Sed TM(tm), 24193323Sed TII(tii) 25193323Sed { } 26193323Sed 27193323Sed//===----------------------------------------------------------------------===// 28193323Sed// Function handling callbacks - Functions are a seldom used feature of GPUS, so 29193323Sed// they are not supported at this time. 30193323Sed//===----------------------------------------------------------------------===// 31193323Sed 32198090Srdivackyconst uint16_t AMDGPURegisterInfo::CalleeSavedReg = AMDGPU::NoRegister; 33193323Sed 34198090Srdivackyconst uint16_t* AMDGPURegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) 35193323Sed const { 36193323Sed return &CalleeSavedReg; 37198090Srdivacky} 38193323Sed 39193323Sedvoid AMDGPURegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI, 40193323Sed int SPAdj, 41193323Sed unsigned FIOperandNum, 42193323Sed RegScavenger *RS) const { 43193323Sed assert(!"Subroutines not supported yet"); 44193323Sed} 45193323Sed 46193323Sedunsigned AMDGPURegisterInfo::getFrameRegister(const MachineFunction &MF) const { 47193323Sed assert(!"Subroutines not supported yet"); 48193323Sed return 0; 49193323Sed} 50193323Sed 51193323Sedunsigned AMDGPURegisterInfo::getIndirectSubReg(unsigned IndirectIndex) const { 52193323Sed 53193323Sed switch(IndirectIndex) { 54193323Sed case 0: return AMDGPU::sub0; 55193323Sed case 1: return AMDGPU::sub1; 56193323Sed case 2: return AMDGPU::sub2; 57193323Sed case 3: return AMDGPU::sub3; 58193323Sed case 4: return AMDGPU::sub4; 59193323Sed case 5: return AMDGPU::sub5; 60193323Sed case 6: return AMDGPU::sub6; 61193323Sed case 7: return AMDGPU::sub7; 62193323Sed case 8: return AMDGPU::sub8; 63193323Sed case 9: return AMDGPU::sub9; 64193323Sed case 10: return AMDGPU::sub10; 65193323Sed case 11: return AMDGPU::sub11; 66193323Sed case 12: return AMDGPU::sub12; 67193323Sed case 13: return AMDGPU::sub13; 68193323Sed case 14: return AMDGPU::sub14; 69193323Sed case 15: return AMDGPU::sub15; 70193323Sed default: llvm_unreachable("indirect index out of range"); 71193323Sed } 72193323Sed} 73193323Sed 74193323Sed#define GET_REGINFO_TARGET_DESC 75193323Sed#include "AMDGPUGenRegisterInfo.inc" 76193323Sed