PPCInstrInfo.td revision 223017
155714Skris//===- PPCInstrInfo.td - The PowerPC Instruction Set -------*- tablegen -*-===// 255714Skris// 355714Skris// The LLVM Compiler Infrastructure 455714Skris// 555714Skris// This file is distributed under the University of Illinois Open Source 655714Skris// License. See LICENSE.TXT for details. 755714Skris// 855714Skris//===----------------------------------------------------------------------===// 955714Skris// 1055714Skris// This file describes the subset of the 32-bit PowerPC instruction set, as used 1155714Skris// by the PowerPC instruction selector. 1255714Skris// 1355714Skris//===----------------------------------------------------------------------===// 1455714Skris 1555714Skrisinclude "PPCInstrFormats.td" 1655714Skris 1755714Skris//===----------------------------------------------------------------------===// 1855714Skris// PowerPC specific type constraints. 1955714Skris// 2055714Skrisdef SDT_PPCstfiwx : SDTypeProfile<0, 2, [ // stfiwx 2155714Skris SDTCisVT<0, f64>, SDTCisPtrTy<1> 2255714Skris]>; 2355714Skrisdef SDT_PPCCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>; 2455714Skrisdef SDT_PPCCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, 2555714Skris SDTCisVT<1, i32> ]>; 2655714Skrisdef SDT_PPCvperm : SDTypeProfile<1, 3, [ 2755714Skris SDTCisVT<3, v16i8>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2> 2855714Skris]>; 2955714Skris 3055714Skrisdef SDT_PPCvcmp : SDTypeProfile<1, 3, [ 3155714Skris SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32> 3255714Skris]>; 3355714Skris 3455714Skrisdef SDT_PPCcondbr : SDTypeProfile<0, 3, [ 3555714Skris SDTCisVT<0, i32>, SDTCisVT<2, OtherVT> 36]>; 37 38def SDT_PPClbrx : SDTypeProfile<1, 2, [ 39 SDTCisVT<0, i32>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT> 40]>; 41def SDT_PPCstbrx : SDTypeProfile<0, 3, [ 42 SDTCisVT<0, i32>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT> 43]>; 44 45def SDT_PPClarx : SDTypeProfile<1, 1, [ 46 SDTCisInt<0>, SDTCisPtrTy<1> 47]>; 48def SDT_PPCstcx : SDTypeProfile<0, 2, [ 49 SDTCisInt<0>, SDTCisPtrTy<1> 50]>; 51 52def SDT_PPCTC_ret : SDTypeProfile<0, 2, [ 53 SDTCisPtrTy<0>, SDTCisVT<1, i32> 54]>; 55 56def SDT_PPCnop : SDTypeProfile<0, 0, []>; 57 58//===----------------------------------------------------------------------===// 59// PowerPC specific DAG Nodes. 60// 61 62def PPCfcfid : SDNode<"PPCISD::FCFID" , SDTFPUnaryOp, []>; 63def PPCfctidz : SDNode<"PPCISD::FCTIDZ", SDTFPUnaryOp, []>; 64def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>; 65def PPCstfiwx : SDNode<"PPCISD::STFIWX", SDT_PPCstfiwx, 66 [SDNPHasChain, SDNPMayStore]>; 67 68// This sequence is used for long double->int conversions. It changes the 69// bits in the FPSCR which is not modelled. 70def PPCmffs : SDNode<"PPCISD::MFFS", SDTypeProfile<1, 0, [SDTCisVT<0, f64>]>, 71 [SDNPOutGlue]>; 72def PPCmtfsb0 : SDNode<"PPCISD::MTFSB0", SDTypeProfile<0, 1, [SDTCisInt<0>]>, 73 [SDNPInGlue, SDNPOutGlue]>; 74def PPCmtfsb1 : SDNode<"PPCISD::MTFSB1", SDTypeProfile<0, 1, [SDTCisInt<0>]>, 75 [SDNPInGlue, SDNPOutGlue]>; 76def PPCfaddrtz: SDNode<"PPCISD::FADDRTZ", SDTFPBinOp, 77 [SDNPInGlue, SDNPOutGlue]>; 78def PPCmtfsf : SDNode<"PPCISD::MTFSF", SDTypeProfile<1, 3, 79 [SDTCisVT<0, f64>, SDTCisInt<1>, SDTCisVT<2, f64>, 80 SDTCisVT<3, f64>]>, 81 [SDNPInGlue]>; 82 83def PPCfsel : SDNode<"PPCISD::FSEL", 84 // Type constraint for fsel. 85 SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, 86 SDTCisFP<0>, SDTCisVT<1, f64>]>, []>; 87 88def PPChi : SDNode<"PPCISD::Hi", SDTIntBinOp, []>; 89def PPClo : SDNode<"PPCISD::Lo", SDTIntBinOp, []>; 90def PPCtoc_entry: SDNode<"PPCISD::TOC_ENTRY", SDTIntBinOp, [SDNPMayLoad]>; 91def PPCvmaddfp : SDNode<"PPCISD::VMADDFP", SDTFPTernaryOp, []>; 92def PPCvnmsubfp : SDNode<"PPCISD::VNMSUBFP", SDTFPTernaryOp, []>; 93 94def PPCvperm : SDNode<"PPCISD::VPERM", SDT_PPCvperm, []>; 95 96// These nodes represent the 32-bit PPC shifts that operate on 6-bit shift 97// amounts. These nodes are generated by the multi-precision shift code. 98def PPCsrl : SDNode<"PPCISD::SRL" , SDTIntShiftOp>; 99def PPCsra : SDNode<"PPCISD::SRA" , SDTIntShiftOp>; 100def PPCshl : SDNode<"PPCISD::SHL" , SDTIntShiftOp>; 101 102def PPCextsw_32 : SDNode<"PPCISD::EXTSW_32" , SDTIntUnaryOp>; 103def PPCstd_32 : SDNode<"PPCISD::STD_32" , SDTStore, 104 [SDNPHasChain, SDNPMayStore]>; 105 106// These are target-independent nodes, but have target-specific formats. 107def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeqStart, 108 [SDNPHasChain, SDNPOutGlue]>; 109def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_PPCCallSeqEnd, 110 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 111 112def SDT_PPCCall : SDTypeProfile<0, -1, [SDTCisInt<0>]>; 113def PPCcall_Darwin : SDNode<"PPCISD::CALL_Darwin", SDT_PPCCall, 114 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 115 SDNPVariadic]>; 116def PPCcall_SVR4 : SDNode<"PPCISD::CALL_SVR4", SDT_PPCCall, 117 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 118 SDNPVariadic]>; 119def PPCnop : SDNode<"PPCISD::NOP", SDT_PPCnop, [SDNPInGlue, SDNPOutGlue]>; 120def PPCload : SDNode<"PPCISD::LOAD", SDTypeProfile<1, 1, []>, 121 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 122def PPCload_toc : SDNode<"PPCISD::LOAD_TOC", SDTypeProfile<0, 1, []>, 123 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>; 124def PPCtoc_restore : SDNode<"PPCISD::TOC_RESTORE", SDTypeProfile<0, 0, []>, 125 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>; 126def PPCmtctr : SDNode<"PPCISD::MTCTR", SDT_PPCCall, 127 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 128def PPCbctrl_Darwin : SDNode<"PPCISD::BCTRL_Darwin", SDTNone, 129 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 130 SDNPVariadic]>; 131 132def PPCbctrl_SVR4 : SDNode<"PPCISD::BCTRL_SVR4", SDTNone, 133 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 134 SDNPVariadic]>; 135 136def retflag : SDNode<"PPCISD::RET_FLAG", SDTNone, 137 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 138 139def PPCtc_return : SDNode<"PPCISD::TC_RETURN", SDT_PPCTC_ret, 140 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 141 142def PPCvcmp : SDNode<"PPCISD::VCMP" , SDT_PPCvcmp, []>; 143def PPCvcmp_o : SDNode<"PPCISD::VCMPo", SDT_PPCvcmp, [SDNPOutGlue]>; 144 145def PPCcondbranch : SDNode<"PPCISD::COND_BRANCH", SDT_PPCcondbr, 146 [SDNPHasChain, SDNPOptInGlue]>; 147 148def PPClbrx : SDNode<"PPCISD::LBRX", SDT_PPClbrx, 149 [SDNPHasChain, SDNPMayLoad]>; 150def PPCstbrx : SDNode<"PPCISD::STBRX", SDT_PPCstbrx, 151 [SDNPHasChain, SDNPMayStore]>; 152 153// Instructions to support atomic operations 154def PPClarx : SDNode<"PPCISD::LARX", SDT_PPClarx, 155 [SDNPHasChain, SDNPMayLoad]>; 156def PPCstcx : SDNode<"PPCISD::STCX", SDT_PPCstcx, 157 [SDNPHasChain, SDNPMayStore]>; 158 159// Instructions to support dynamic alloca. 160def SDTDynOp : SDTypeProfile<1, 2, []>; 161def PPCdynalloc : SDNode<"PPCISD::DYNALLOC", SDTDynOp, [SDNPHasChain]>; 162 163//===----------------------------------------------------------------------===// 164// PowerPC specific transformation functions and pattern fragments. 165// 166 167def SHL32 : SDNodeXForm<imm, [{ 168 // Transformation function: 31 - imm 169 return getI32Imm(31 - N->getZExtValue()); 170}]>; 171 172def SRL32 : SDNodeXForm<imm, [{ 173 // Transformation function: 32 - imm 174 return N->getZExtValue() ? getI32Imm(32 - N->getZExtValue()) : getI32Imm(0); 175}]>; 176 177def LO16 : SDNodeXForm<imm, [{ 178 // Transformation function: get the low 16 bits. 179 return getI32Imm((unsigned short)N->getZExtValue()); 180}]>; 181 182def HI16 : SDNodeXForm<imm, [{ 183 // Transformation function: shift the immediate value down into the low bits. 184 return getI32Imm((unsigned)N->getZExtValue() >> 16); 185}]>; 186 187def HA16 : SDNodeXForm<imm, [{ 188 // Transformation function: shift the immediate value down into the low bits. 189 signed int Val = N->getZExtValue(); 190 return getI32Imm((Val - (signed short)Val) >> 16); 191}]>; 192def MB : SDNodeXForm<imm, [{ 193 // Transformation function: get the start bit of a mask 194 unsigned mb = 0, me; 195 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me); 196 return getI32Imm(mb); 197}]>; 198 199def ME : SDNodeXForm<imm, [{ 200 // Transformation function: get the end bit of a mask 201 unsigned mb, me = 0; 202 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me); 203 return getI32Imm(me); 204}]>; 205def maskimm32 : PatLeaf<(imm), [{ 206 // maskImm predicate - True if immediate is a run of ones. 207 unsigned mb, me; 208 if (N->getValueType(0) == MVT::i32) 209 return isRunOfOnes((unsigned)N->getZExtValue(), mb, me); 210 else 211 return false; 212}]>; 213 214def immSExt16 : PatLeaf<(imm), [{ 215 // immSExt16 predicate - True if the immediate fits in a 16-bit sign extended 216 // field. Used by instructions like 'addi'. 217 if (N->getValueType(0) == MVT::i32) 218 return (int32_t)N->getZExtValue() == (short)N->getZExtValue(); 219 else 220 return (int64_t)N->getZExtValue() == (short)N->getZExtValue(); 221}]>; 222def immZExt16 : PatLeaf<(imm), [{ 223 // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended 224 // field. Used by instructions like 'ori'. 225 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue(); 226}], LO16>; 227 228// imm16Shifted* - These match immediates where the low 16-bits are zero. There 229// are two forms: imm16ShiftedSExt and imm16ShiftedZExt. These two forms are 230// identical in 32-bit mode, but in 64-bit mode, they return true if the 231// immediate fits into a sign/zero extended 32-bit immediate (with the low bits 232// clear). 233def imm16ShiftedZExt : PatLeaf<(imm), [{ 234 // imm16ShiftedZExt predicate - True if only bits in the top 16-bits of the 235 // immediate are set. Used by instructions like 'xoris'. 236 return (N->getZExtValue() & ~uint64_t(0xFFFF0000)) == 0; 237}], HI16>; 238 239def imm16ShiftedSExt : PatLeaf<(imm), [{ 240 // imm16ShiftedSExt predicate - True if only bits in the top 16-bits of the 241 // immediate are set. Used by instructions like 'addis'. Identical to 242 // imm16ShiftedZExt in 32-bit mode. 243 if (N->getZExtValue() & 0xFFFF) return false; 244 if (N->getValueType(0) == MVT::i32) 245 return true; 246 // For 64-bit, make sure it is sext right. 247 return N->getZExtValue() == (uint64_t)(int)N->getZExtValue(); 248}], HI16>; 249 250 251//===----------------------------------------------------------------------===// 252// PowerPC Flag Definitions. 253 254class isPPC64 { bit PPC64 = 1; } 255class isDOT { 256 list<Register> Defs = [CR0]; 257 bit RC = 1; 258} 259 260class RegConstraint<string C> { 261 string Constraints = C; 262} 263class NoEncode<string E> { 264 string DisableEncoding = E; 265} 266 267 268//===----------------------------------------------------------------------===// 269// PowerPC Operand Definitions. 270 271def s5imm : Operand<i32> { 272 let PrintMethod = "printS5ImmOperand"; 273} 274def u5imm : Operand<i32> { 275 let PrintMethod = "printU5ImmOperand"; 276} 277def u6imm : Operand<i32> { 278 let PrintMethod = "printU6ImmOperand"; 279} 280def s16imm : Operand<i32> { 281 let PrintMethod = "printS16ImmOperand"; 282} 283def u16imm : Operand<i32> { 284 let PrintMethod = "printU16ImmOperand"; 285} 286def s16immX4 : Operand<i32> { // Multiply imm by 4 before printing. 287 let PrintMethod = "printS16X4ImmOperand"; 288} 289def directbrtarget : Operand<OtherVT> { 290 let PrintMethod = "printBranchOperand"; 291 let EncoderMethod = "getDirectBrEncoding"; 292} 293def condbrtarget : Operand<OtherVT> { 294 let PrintMethod = "printBranchOperand"; 295 let EncoderMethod = "getCondBrEncoding"; 296} 297def calltarget : Operand<iPTR> { 298 let EncoderMethod = "getDirectBrEncoding"; 299} 300def aaddr : Operand<iPTR> { 301 let PrintMethod = "printAbsAddrOperand"; 302} 303def symbolHi: Operand<i32> { 304 let PrintMethod = "printSymbolHi"; 305 let EncoderMethod = "getHA16Encoding"; 306} 307def symbolLo: Operand<i32> { 308 let PrintMethod = "printSymbolLo"; 309 let EncoderMethod = "getLO16Encoding"; 310} 311def crbitm: Operand<i8> { 312 let PrintMethod = "printcrbitm"; 313 let EncoderMethod = "get_crbitm_encoding"; 314} 315// Address operands 316def memri : Operand<iPTR> { 317 let PrintMethod = "printMemRegImm"; 318 let MIOperandInfo = (ops i32imm:$imm, ptr_rc:$reg); 319 let EncoderMethod = "getMemRIEncoding"; 320} 321def memrr : Operand<iPTR> { 322 let PrintMethod = "printMemRegReg"; 323 let MIOperandInfo = (ops ptr_rc, ptr_rc); 324} 325def memrix : Operand<iPTR> { // memri where the imm is shifted 2 bits. 326 let PrintMethod = "printMemRegImmShifted"; 327 let MIOperandInfo = (ops i32imm:$imm, ptr_rc:$reg); 328 let EncoderMethod = "getMemRIXEncoding"; 329} 330def tocentry : Operand<iPTR> { 331 let MIOperandInfo = (ops i32imm:$imm); 332} 333 334// PowerPC Predicate operand. 20 = (0<<5)|20 = always, CR0 is a dummy reg 335// that doesn't matter. 336def pred : PredicateOperand<OtherVT, (ops imm, CRRC), 337 (ops (i32 20), (i32 zero_reg))> { 338 let PrintMethod = "printPredicateOperand"; 339} 340 341// Define PowerPC specific addressing mode. 342def iaddr : ComplexPattern<iPTR, 2, "SelectAddrImm", [], []>; 343def xaddr : ComplexPattern<iPTR, 2, "SelectAddrIdx", [], []>; 344def xoaddr : ComplexPattern<iPTR, 2, "SelectAddrIdxOnly",[], []>; 345def ixaddr : ComplexPattern<iPTR, 2, "SelectAddrImmShift", [], []>; // "std" 346 347/// This is just the offset part of iaddr, used for preinc. 348def iaddroff : ComplexPattern<iPTR, 1, "SelectAddrImmOffs", [], []>; 349 350//===----------------------------------------------------------------------===// 351// PowerPC Instruction Predicate Definitions. 352def FPContractions : Predicate<"!NoExcessFPPrecision">; 353def In32BitMode : Predicate<"!PPCSubTarget.isPPC64()">; 354def In64BitMode : Predicate<"PPCSubTarget.isPPC64()">; 355 356 357//===----------------------------------------------------------------------===// 358// PowerPC Instruction Definitions. 359 360// Pseudo-instructions: 361 362let hasCtrlDep = 1 in { 363let Defs = [R1], Uses = [R1] in { 364def ADJCALLSTACKDOWN : Pseudo<(outs), (ins u16imm:$amt), "", 365 [(callseq_start timm:$amt)]>; 366def ADJCALLSTACKUP : Pseudo<(outs), (ins u16imm:$amt1, u16imm:$amt2), "", 367 [(callseq_end timm:$amt1, timm:$amt2)]>; 368} 369 370def UPDATE_VRSAVE : Pseudo<(outs GPRC:$rD), (ins GPRC:$rS), 371 "UPDATE_VRSAVE $rD, $rS", []>; 372} 373 374let Defs = [R1], Uses = [R1] in 375def DYNALLOC : Pseudo<(outs GPRC:$result), (ins GPRC:$negsize, memri:$fpsi), "", 376 [(set GPRC:$result, 377 (PPCdynalloc GPRC:$negsize, iaddr:$fpsi))]>; 378 379// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after 380// instruction selection into a branch sequence. 381let usesCustomInserter = 1, // Expanded after instruction selection. 382 PPC970_Single = 1 in { 383 def SELECT_CC_I4 : Pseudo<(outs GPRC:$dst), (ins CRRC:$cond, GPRC:$T, GPRC:$F, 384 i32imm:$BROPC), "", 385 []>; 386 def SELECT_CC_I8 : Pseudo<(outs G8RC:$dst), (ins CRRC:$cond, G8RC:$T, G8RC:$F, 387 i32imm:$BROPC), "", 388 []>; 389 def SELECT_CC_F4 : Pseudo<(outs F4RC:$dst), (ins CRRC:$cond, F4RC:$T, F4RC:$F, 390 i32imm:$BROPC), "", 391 []>; 392 def SELECT_CC_F8 : Pseudo<(outs F8RC:$dst), (ins CRRC:$cond, F8RC:$T, F8RC:$F, 393 i32imm:$BROPC), "", 394 []>; 395 def SELECT_CC_VRRC: Pseudo<(outs VRRC:$dst), (ins CRRC:$cond, VRRC:$T, VRRC:$F, 396 i32imm:$BROPC), "", 397 []>; 398} 399 400// SPILL_CR - Indicate that we're dumping the CR register, so we'll need to 401// scavenge a register for it. 402def SPILL_CR : Pseudo<(outs), (ins GPRC:$cond, memri:$F), 403 "", []>; 404 405let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in { 406 let isReturn = 1, Uses = [LR, RM] in 407 def BLR : XLForm_2_br<19, 16, 0, (outs), (ins pred:$p), 408 "b${p:cc}lr ${p:reg}", BrB, 409 [(retflag)]>; 410 let isBranch = 1, isIndirectBranch = 1, Uses = [CTR] in 411 def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>; 412} 413 414let Defs = [LR] in 415 def MovePCtoLR : Pseudo<(outs), (ins), "", []>, 416 PPC970_Unit_BRU; 417 418let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in { 419 let isBarrier = 1 in { 420 def B : IForm<18, 0, 0, (outs), (ins directbrtarget:$dst), 421 "b $dst", BrB, 422 [(br bb:$dst)]>; 423 } 424 425 // BCC represents an arbitrary conditional branch on a predicate. 426 // FIXME: should be able to write a pattern for PPCcondbranch, but can't use 427 // a two-value operand where a dag node expects two operands. :( 428 def BCC : BForm<16, 0, 0, (outs), (ins pred:$cond, condbrtarget:$dst), 429 "b${cond:cc} ${cond:reg}, $dst" 430 /*[(PPCcondbranch CRRC:$crS, imm:$opc, bb:$dst)]*/>; 431} 432 433// Darwin ABI Calls. 434let isCall = 1, PPC970_Unit = 7, 435 // All calls clobber the non-callee saved registers... 436 Defs = [R0,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12, 437 F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13, 438 V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16,V17,V18,V19, 439 LR,CTR, 440 CR0,CR1,CR5,CR6,CR7,CARRY] in { 441 // Convenient aliases for call instructions 442 let Uses = [RM] in { 443 def BL_Darwin : IForm<18, 0, 1, 444 (outs), (ins calltarget:$func, variable_ops), 445 "bl $func", BrB, []>; // See Pat patterns below. 446 def BLA_Darwin : IForm<18, 1, 1, 447 (outs), (ins aaddr:$func, variable_ops), 448 "bla $func", BrB, [(PPCcall_Darwin (i32 imm:$func))]>; 449 } 450 let Uses = [CTR, RM] in { 451 def BCTRL_Darwin : XLForm_2_ext<19, 528, 20, 0, 1, 452 (outs), (ins variable_ops), 453 "bctrl", BrB, 454 [(PPCbctrl_Darwin)]>, Requires<[In32BitMode]>; 455 } 456} 457 458// SVR4 ABI Calls. 459let isCall = 1, PPC970_Unit = 7, 460 // All calls clobber the non-callee saved registers... 461 Defs = [R0,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12, 462 F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13, 463 V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16,V17,V18,V19, 464 LR,CTR, 465 CR0,CR1,CR5,CR6,CR7,CARRY] in { 466 // Convenient aliases for call instructions 467 let Uses = [RM] in { 468 def BL_SVR4 : IForm<18, 0, 1, 469 (outs), (ins calltarget:$func, variable_ops), 470 "bl $func", BrB, []>; // See Pat patterns below. 471 def BLA_SVR4 : IForm<18, 1, 1, 472 (outs), (ins aaddr:$func, variable_ops), 473 "bla $func", BrB, 474 [(PPCcall_SVR4 (i32 imm:$func))]>; 475 } 476 let Uses = [CTR, RM] in { 477 def BCTRL_SVR4 : XLForm_2_ext<19, 528, 20, 0, 1, 478 (outs), (ins variable_ops), 479 "bctrl", BrB, 480 [(PPCbctrl_SVR4)]>, Requires<[In32BitMode]>; 481 } 482} 483 484 485let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 486def TCRETURNdi :Pseudo< (outs), 487 (ins calltarget:$dst, i32imm:$offset, variable_ops), 488 "#TC_RETURNd $dst $offset", 489 []>; 490 491 492let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 493def TCRETURNai :Pseudo<(outs), (ins aaddr:$func, i32imm:$offset, variable_ops), 494 "#TC_RETURNa $func $offset", 495 [(PPCtc_return (i32 imm:$func), imm:$offset)]>; 496 497let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 498def TCRETURNri : Pseudo<(outs), (ins CTRRC:$dst, i32imm:$offset, variable_ops), 499 "#TC_RETURNr $dst $offset", 500 []>; 501 502 503let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1, 504 isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR, RM] in 505def TAILBCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>, 506 Requires<[In32BitMode]>; 507 508 509 510let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 511 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 512def TAILB : IForm<18, 0, 0, (outs), (ins calltarget:$dst), 513 "b $dst", BrB, 514 []>; 515 516 517let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 518 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 519def TAILBA : IForm<18, 0, 0, (outs), (ins aaddr:$dst), 520 "ba $dst", BrB, 521 []>; 522 523 524// DCB* instructions. 525def DCBA : DCB_Form<758, 0, (outs), (ins memrr:$dst), 526 "dcba $dst", LdStDCBF, [(int_ppc_dcba xoaddr:$dst)]>, 527 PPC970_DGroup_Single; 528def DCBF : DCB_Form<86, 0, (outs), (ins memrr:$dst), 529 "dcbf $dst", LdStDCBF, [(int_ppc_dcbf xoaddr:$dst)]>, 530 PPC970_DGroup_Single; 531def DCBI : DCB_Form<470, 0, (outs), (ins memrr:$dst), 532 "dcbi $dst", LdStDCBF, [(int_ppc_dcbi xoaddr:$dst)]>, 533 PPC970_DGroup_Single; 534def DCBST : DCB_Form<54, 0, (outs), (ins memrr:$dst), 535 "dcbst $dst", LdStDCBF, [(int_ppc_dcbst xoaddr:$dst)]>, 536 PPC970_DGroup_Single; 537def DCBT : DCB_Form<278, 0, (outs), (ins memrr:$dst), 538 "dcbt $dst", LdStDCBF, [(int_ppc_dcbt xoaddr:$dst)]>, 539 PPC970_DGroup_Single; 540def DCBTST : DCB_Form<246, 0, (outs), (ins memrr:$dst), 541 "dcbtst $dst", LdStDCBF, [(int_ppc_dcbtst xoaddr:$dst)]>, 542 PPC970_DGroup_Single; 543def DCBZ : DCB_Form<1014, 0, (outs), (ins memrr:$dst), 544 "dcbz $dst", LdStDCBF, [(int_ppc_dcbz xoaddr:$dst)]>, 545 PPC970_DGroup_Single; 546def DCBZL : DCB_Form<1014, 1, (outs), (ins memrr:$dst), 547 "dcbzl $dst", LdStDCBF, [(int_ppc_dcbzl xoaddr:$dst)]>, 548 PPC970_DGroup_Single; 549 550// Atomic operations 551let usesCustomInserter = 1 in { 552 let Defs = [CR0] in { 553 def ATOMIC_LOAD_ADD_I8 : Pseudo< 554 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "", 555 [(set GPRC:$dst, (atomic_load_add_8 xoaddr:$ptr, GPRC:$incr))]>; 556 def ATOMIC_LOAD_SUB_I8 : Pseudo< 557 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "", 558 [(set GPRC:$dst, (atomic_load_sub_8 xoaddr:$ptr, GPRC:$incr))]>; 559 def ATOMIC_LOAD_AND_I8 : Pseudo< 560 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "", 561 [(set GPRC:$dst, (atomic_load_and_8 xoaddr:$ptr, GPRC:$incr))]>; 562 def ATOMIC_LOAD_OR_I8 : Pseudo< 563 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "", 564 [(set GPRC:$dst, (atomic_load_or_8 xoaddr:$ptr, GPRC:$incr))]>; 565 def ATOMIC_LOAD_XOR_I8 : Pseudo< 566 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "", 567 [(set GPRC:$dst, (atomic_load_xor_8 xoaddr:$ptr, GPRC:$incr))]>; 568 def ATOMIC_LOAD_NAND_I8 : Pseudo< 569 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "", 570 [(set GPRC:$dst, (atomic_load_nand_8 xoaddr:$ptr, GPRC:$incr))]>; 571 def ATOMIC_LOAD_ADD_I16 : Pseudo< 572 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "", 573 [(set GPRC:$dst, (atomic_load_add_16 xoaddr:$ptr, GPRC:$incr))]>; 574 def ATOMIC_LOAD_SUB_I16 : Pseudo< 575 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "", 576 [(set GPRC:$dst, (atomic_load_sub_16 xoaddr:$ptr, GPRC:$incr))]>; 577 def ATOMIC_LOAD_AND_I16 : Pseudo< 578 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "", 579 [(set GPRC:$dst, (atomic_load_and_16 xoaddr:$ptr, GPRC:$incr))]>; 580 def ATOMIC_LOAD_OR_I16 : Pseudo< 581 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "", 582 [(set GPRC:$dst, (atomic_load_or_16 xoaddr:$ptr, GPRC:$incr))]>; 583 def ATOMIC_LOAD_XOR_I16 : Pseudo< 584 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "", 585 [(set GPRC:$dst, (atomic_load_xor_16 xoaddr:$ptr, GPRC:$incr))]>; 586 def ATOMIC_LOAD_NAND_I16 : Pseudo< 587 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "", 588 [(set GPRC:$dst, (atomic_load_nand_16 xoaddr:$ptr, GPRC:$incr))]>; 589 def ATOMIC_LOAD_ADD_I32 : Pseudo< 590 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "", 591 [(set GPRC:$dst, (atomic_load_add_32 xoaddr:$ptr, GPRC:$incr))]>; 592 def ATOMIC_LOAD_SUB_I32 : Pseudo< 593 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "", 594 [(set GPRC:$dst, (atomic_load_sub_32 xoaddr:$ptr, GPRC:$incr))]>; 595 def ATOMIC_LOAD_AND_I32 : Pseudo< 596 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "", 597 [(set GPRC:$dst, (atomic_load_and_32 xoaddr:$ptr, GPRC:$incr))]>; 598 def ATOMIC_LOAD_OR_I32 : Pseudo< 599 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "", 600 [(set GPRC:$dst, (atomic_load_or_32 xoaddr:$ptr, GPRC:$incr))]>; 601 def ATOMIC_LOAD_XOR_I32 : Pseudo< 602 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "", 603 [(set GPRC:$dst, (atomic_load_xor_32 xoaddr:$ptr, GPRC:$incr))]>; 604 def ATOMIC_LOAD_NAND_I32 : Pseudo< 605 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "", 606 [(set GPRC:$dst, (atomic_load_nand_32 xoaddr:$ptr, GPRC:$incr))]>; 607 608 def ATOMIC_CMP_SWAP_I8 : Pseudo< 609 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$old, GPRC:$new), "", 610 [(set GPRC:$dst, 611 (atomic_cmp_swap_8 xoaddr:$ptr, GPRC:$old, GPRC:$new))]>; 612 def ATOMIC_CMP_SWAP_I16 : Pseudo< 613 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$old, GPRC:$new), "", 614 [(set GPRC:$dst, 615 (atomic_cmp_swap_16 xoaddr:$ptr, GPRC:$old, GPRC:$new))]>; 616 def ATOMIC_CMP_SWAP_I32 : Pseudo< 617 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$old, GPRC:$new), "", 618 [(set GPRC:$dst, 619 (atomic_cmp_swap_32 xoaddr:$ptr, GPRC:$old, GPRC:$new))]>; 620 621 def ATOMIC_SWAP_I8 : Pseudo< 622 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$new), "", 623 [(set GPRC:$dst, (atomic_swap_8 xoaddr:$ptr, GPRC:$new))]>; 624 def ATOMIC_SWAP_I16 : Pseudo< 625 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$new), "", 626 [(set GPRC:$dst, (atomic_swap_16 xoaddr:$ptr, GPRC:$new))]>; 627 def ATOMIC_SWAP_I32 : Pseudo< 628 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$new), "", 629 [(set GPRC:$dst, (atomic_swap_32 xoaddr:$ptr, GPRC:$new))]>; 630 } 631} 632 633// Instructions to support atomic operations 634def LWARX : XForm_1<31, 20, (outs GPRC:$rD), (ins memrr:$src), 635 "lwarx $rD, $src", LdStLWARX, 636 [(set GPRC:$rD, (PPClarx xoaddr:$src))]>; 637 638let Defs = [CR0] in 639def STWCX : XForm_1<31, 150, (outs), (ins GPRC:$rS, memrr:$dst), 640 "stwcx. $rS, $dst", LdStSTWCX, 641 [(PPCstcx GPRC:$rS, xoaddr:$dst)]>, 642 isDOT; 643 644let isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in 645def TRAP : XForm_24<31, 4, (outs), (ins), "trap", LdStGeneral, [(trap)]>; 646 647//===----------------------------------------------------------------------===// 648// PPC32 Load Instructions. 649// 650 651// Unindexed (r+i) Loads. 652let canFoldAsLoad = 1, PPC970_Unit = 2 in { 653def LBZ : DForm_1<34, (outs GPRC:$rD), (ins memri:$src), 654 "lbz $rD, $src", LdStGeneral, 655 [(set GPRC:$rD, (zextloadi8 iaddr:$src))]>; 656def LHA : DForm_1<42, (outs GPRC:$rD), (ins memri:$src), 657 "lha $rD, $src", LdStLHA, 658 [(set GPRC:$rD, (sextloadi16 iaddr:$src))]>, 659 PPC970_DGroup_Cracked; 660def LHZ : DForm_1<40, (outs GPRC:$rD), (ins memri:$src), 661 "lhz $rD, $src", LdStGeneral, 662 [(set GPRC:$rD, (zextloadi16 iaddr:$src))]>; 663def LWZ : DForm_1<32, (outs GPRC:$rD), (ins memri:$src), 664 "lwz $rD, $src", LdStGeneral, 665 [(set GPRC:$rD, (load iaddr:$src))]>; 666 667def LFS : DForm_1<48, (outs F4RC:$rD), (ins memri:$src), 668 "lfs $rD, $src", LdStLFDU, 669 [(set F4RC:$rD, (load iaddr:$src))]>; 670def LFD : DForm_1<50, (outs F8RC:$rD), (ins memri:$src), 671 "lfd $rD, $src", LdStLFD, 672 [(set F8RC:$rD, (load iaddr:$src))]>; 673 674 675// Unindexed (r+i) Loads with Update (preinc). 676let mayLoad = 1 in { 677def LBZU : DForm_1<35, (outs GPRC:$rD, ptr_rc:$ea_result), (ins memri:$addr), 678 "lbzu $rD, $addr", LdStGeneral, 679 []>, RegConstraint<"$addr.reg = $ea_result">, 680 NoEncode<"$ea_result">; 681 682def LHAU : DForm_1<43, (outs GPRC:$rD, ptr_rc:$ea_result), (ins memri:$addr), 683 "lhau $rD, $addr", LdStGeneral, 684 []>, RegConstraint<"$addr.reg = $ea_result">, 685 NoEncode<"$ea_result">; 686 687def LHZU : DForm_1<41, (outs GPRC:$rD, ptr_rc:$ea_result), (ins memri:$addr), 688 "lhzu $rD, $addr", LdStGeneral, 689 []>, RegConstraint<"$addr.reg = $ea_result">, 690 NoEncode<"$ea_result">; 691 692def LWZU : DForm_1<33, (outs GPRC:$rD, ptr_rc:$ea_result), (ins memri:$addr), 693 "lwzu $rD, $addr", LdStGeneral, 694 []>, RegConstraint<"$addr.reg = $ea_result">, 695 NoEncode<"$ea_result">; 696 697def LFSU : DForm_1<49, (outs F4RC:$rD, ptr_rc:$ea_result), (ins memri:$addr), 698 "lfs $rD, $addr", LdStLFDU, 699 []>, RegConstraint<"$addr.reg = $ea_result">, 700 NoEncode<"$ea_result">; 701 702def LFDU : DForm_1<51, (outs F8RC:$rD, ptr_rc:$ea_result), (ins memri:$addr), 703 "lfd $rD, $addr", LdStLFD, 704 []>, RegConstraint<"$addr.reg = $ea_result">, 705 NoEncode<"$ea_result">; 706} 707} 708 709// Indexed (r+r) Loads. 710// 711let canFoldAsLoad = 1, PPC970_Unit = 2 in { 712def LBZX : XForm_1<31, 87, (outs GPRC:$rD), (ins memrr:$src), 713 "lbzx $rD, $src", LdStGeneral, 714 [(set GPRC:$rD, (zextloadi8 xaddr:$src))]>; 715def LHAX : XForm_1<31, 343, (outs GPRC:$rD), (ins memrr:$src), 716 "lhax $rD, $src", LdStLHA, 717 [(set GPRC:$rD, (sextloadi16 xaddr:$src))]>, 718 PPC970_DGroup_Cracked; 719def LHZX : XForm_1<31, 279, (outs GPRC:$rD), (ins memrr:$src), 720 "lhzx $rD, $src", LdStGeneral, 721 [(set GPRC:$rD, (zextloadi16 xaddr:$src))]>; 722def LWZX : XForm_1<31, 23, (outs GPRC:$rD), (ins memrr:$src), 723 "lwzx $rD, $src", LdStGeneral, 724 [(set GPRC:$rD, (load xaddr:$src))]>; 725 726 727def LHBRX : XForm_1<31, 790, (outs GPRC:$rD), (ins memrr:$src), 728 "lhbrx $rD, $src", LdStGeneral, 729 [(set GPRC:$rD, (PPClbrx xoaddr:$src, i16))]>; 730def LWBRX : XForm_1<31, 534, (outs GPRC:$rD), (ins memrr:$src), 731 "lwbrx $rD, $src", LdStGeneral, 732 [(set GPRC:$rD, (PPClbrx xoaddr:$src, i32))]>; 733 734def LFSX : XForm_25<31, 535, (outs F4RC:$frD), (ins memrr:$src), 735 "lfsx $frD, $src", LdStLFDU, 736 [(set F4RC:$frD, (load xaddr:$src))]>; 737def LFDX : XForm_25<31, 599, (outs F8RC:$frD), (ins memrr:$src), 738 "lfdx $frD, $src", LdStLFDU, 739 [(set F8RC:$frD, (load xaddr:$src))]>; 740} 741 742//===----------------------------------------------------------------------===// 743// PPC32 Store Instructions. 744// 745 746// Unindexed (r+i) Stores. 747let PPC970_Unit = 2 in { 748def STB : DForm_1<38, (outs), (ins GPRC:$rS, memri:$src), 749 "stb $rS, $src", LdStGeneral, 750 [(truncstorei8 GPRC:$rS, iaddr:$src)]>; 751def STH : DForm_1<44, (outs), (ins GPRC:$rS, memri:$src), 752 "sth $rS, $src", LdStGeneral, 753 [(truncstorei16 GPRC:$rS, iaddr:$src)]>; 754def STW : DForm_1<36, (outs), (ins GPRC:$rS, memri:$src), 755 "stw $rS, $src", LdStGeneral, 756 [(store GPRC:$rS, iaddr:$src)]>; 757def STFS : DForm_1<52, (outs), (ins F4RC:$rS, memri:$dst), 758 "stfs $rS, $dst", LdStUX, 759 [(store F4RC:$rS, iaddr:$dst)]>; 760def STFD : DForm_1<54, (outs), (ins F8RC:$rS, memri:$dst), 761 "stfd $rS, $dst", LdStUX, 762 [(store F8RC:$rS, iaddr:$dst)]>; 763} 764 765// Unindexed (r+i) Stores with Update (preinc). 766let PPC970_Unit = 2 in { 767def STBU : DForm_1a<39, (outs ptr_rc:$ea_res), (ins GPRC:$rS, 768 symbolLo:$ptroff, ptr_rc:$ptrreg), 769 "stbu $rS, $ptroff($ptrreg)", LdStGeneral, 770 [(set ptr_rc:$ea_res, 771 (pre_truncsti8 GPRC:$rS, ptr_rc:$ptrreg, 772 iaddroff:$ptroff))]>, 773 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">; 774def STHU : DForm_1a<45, (outs ptr_rc:$ea_res), (ins GPRC:$rS, 775 symbolLo:$ptroff, ptr_rc:$ptrreg), 776 "sthu $rS, $ptroff($ptrreg)", LdStGeneral, 777 [(set ptr_rc:$ea_res, 778 (pre_truncsti16 GPRC:$rS, ptr_rc:$ptrreg, 779 iaddroff:$ptroff))]>, 780 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">; 781def STWU : DForm_1a<37, (outs ptr_rc:$ea_res), (ins GPRC:$rS, 782 symbolLo:$ptroff, ptr_rc:$ptrreg), 783 "stwu $rS, $ptroff($ptrreg)", LdStGeneral, 784 [(set ptr_rc:$ea_res, (pre_store GPRC:$rS, ptr_rc:$ptrreg, 785 iaddroff:$ptroff))]>, 786 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">; 787def STFSU : DForm_1a<37, (outs ptr_rc:$ea_res), (ins F4RC:$rS, 788 symbolLo:$ptroff, ptr_rc:$ptrreg), 789 "stfsu $rS, $ptroff($ptrreg)", LdStGeneral, 790 [(set ptr_rc:$ea_res, (pre_store F4RC:$rS, ptr_rc:$ptrreg, 791 iaddroff:$ptroff))]>, 792 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">; 793def STFDU : DForm_1a<37, (outs ptr_rc:$ea_res), (ins F8RC:$rS, 794 symbolLo:$ptroff, ptr_rc:$ptrreg), 795 "stfdu $rS, $ptroff($ptrreg)", LdStGeneral, 796 [(set ptr_rc:$ea_res, (pre_store F8RC:$rS, ptr_rc:$ptrreg, 797 iaddroff:$ptroff))]>, 798 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">; 799} 800 801 802// Indexed (r+r) Stores. 803// 804let PPC970_Unit = 2 in { 805def STBX : XForm_8<31, 215, (outs), (ins GPRC:$rS, memrr:$dst), 806 "stbx $rS, $dst", LdStGeneral, 807 [(truncstorei8 GPRC:$rS, xaddr:$dst)]>, 808 PPC970_DGroup_Cracked; 809def STHX : XForm_8<31, 407, (outs), (ins GPRC:$rS, memrr:$dst), 810 "sthx $rS, $dst", LdStGeneral, 811 [(truncstorei16 GPRC:$rS, xaddr:$dst)]>, 812 PPC970_DGroup_Cracked; 813def STWX : XForm_8<31, 151, (outs), (ins GPRC:$rS, memrr:$dst), 814 "stwx $rS, $dst", LdStGeneral, 815 [(store GPRC:$rS, xaddr:$dst)]>, 816 PPC970_DGroup_Cracked; 817 818let mayStore = 1 in { 819def STWUX : XForm_8<31, 183, (outs), (ins GPRC:$rS, GPRC:$rA, GPRC:$rB), 820 "stwux $rS, $rA, $rB", LdStGeneral, 821 []>; 822} 823def STHBRX: XForm_8<31, 918, (outs), (ins GPRC:$rS, memrr:$dst), 824 "sthbrx $rS, $dst", LdStGeneral, 825 [(PPCstbrx GPRC:$rS, xoaddr:$dst, i16)]>, 826 PPC970_DGroup_Cracked; 827def STWBRX: XForm_8<31, 662, (outs), (ins GPRC:$rS, memrr:$dst), 828 "stwbrx $rS, $dst", LdStGeneral, 829 [(PPCstbrx GPRC:$rS, xoaddr:$dst, i32)]>, 830 PPC970_DGroup_Cracked; 831 832def STFIWX: XForm_28<31, 983, (outs), (ins F8RC:$frS, memrr:$dst), 833 "stfiwx $frS, $dst", LdStUX, 834 [(PPCstfiwx F8RC:$frS, xoaddr:$dst)]>; 835 836def STFSX : XForm_28<31, 663, (outs), (ins F4RC:$frS, memrr:$dst), 837 "stfsx $frS, $dst", LdStUX, 838 [(store F4RC:$frS, xaddr:$dst)]>; 839def STFDX : XForm_28<31, 727, (outs), (ins F8RC:$frS, memrr:$dst), 840 "stfdx $frS, $dst", LdStUX, 841 [(store F8RC:$frS, xaddr:$dst)]>; 842} 843 844def SYNC : XForm_24_sync<31, 598, (outs), (ins), 845 "sync", LdStSync, 846 [(int_ppc_sync)]>; 847 848//===----------------------------------------------------------------------===// 849// PPC32 Arithmetic Instructions. 850// 851 852let PPC970_Unit = 1 in { // FXU Operations. 853def ADDI : DForm_2<14, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm), 854 "addi $rD, $rA, $imm", IntGeneral, 855 [(set GPRC:$rD, (add GPRC:$rA, immSExt16:$imm))]>; 856let Defs = [CARRY] in { 857def ADDIC : DForm_2<12, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm), 858 "addic $rD, $rA, $imm", IntGeneral, 859 [(set GPRC:$rD, (addc GPRC:$rA, immSExt16:$imm))]>, 860 PPC970_DGroup_Cracked; 861def ADDICo : DForm_2<13, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm), 862 "addic. $rD, $rA, $imm", IntGeneral, 863 []>; 864} 865def ADDIS : DForm_2<15, (outs GPRC:$rD), (ins GPRC:$rA, symbolHi:$imm), 866 "addis $rD, $rA, $imm", IntGeneral, 867 [(set GPRC:$rD, (add GPRC:$rA, imm16ShiftedSExt:$imm))]>; 868def LA : DForm_2<14, (outs GPRC:$rD), (ins GPRC:$rA, symbolLo:$sym), 869 "la $rD, $sym($rA)", IntGeneral, 870 [(set GPRC:$rD, (add GPRC:$rA, 871 (PPClo tglobaladdr:$sym, 0)))]>; 872def MULLI : DForm_2< 7, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm), 873 "mulli $rD, $rA, $imm", IntMulLI, 874 [(set GPRC:$rD, (mul GPRC:$rA, immSExt16:$imm))]>; 875let Defs = [CARRY] in { 876def SUBFIC : DForm_2< 8, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm), 877 "subfic $rD, $rA, $imm", IntGeneral, 878 [(set GPRC:$rD, (subc immSExt16:$imm, GPRC:$rA))]>; 879} 880 881let isReMaterializable = 1 in { 882 def LI : DForm_2_r0<14, (outs GPRC:$rD), (ins symbolLo:$imm), 883 "li $rD, $imm", IntGeneral, 884 [(set GPRC:$rD, immSExt16:$imm)]>; 885 def LIS : DForm_2_r0<15, (outs GPRC:$rD), (ins symbolHi:$imm), 886 "lis $rD, $imm", IntGeneral, 887 [(set GPRC:$rD, imm16ShiftedSExt:$imm)]>; 888} 889} 890 891let PPC970_Unit = 1 in { // FXU Operations. 892def ANDIo : DForm_4<28, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2), 893 "andi. $dst, $src1, $src2", IntGeneral, 894 [(set GPRC:$dst, (and GPRC:$src1, immZExt16:$src2))]>, 895 isDOT; 896def ANDISo : DForm_4<29, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2), 897 "andis. $dst, $src1, $src2", IntGeneral, 898 [(set GPRC:$dst, (and GPRC:$src1,imm16ShiftedZExt:$src2))]>, 899 isDOT; 900def ORI : DForm_4<24, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2), 901 "ori $dst, $src1, $src2", IntGeneral, 902 [(set GPRC:$dst, (or GPRC:$src1, immZExt16:$src2))]>; 903def ORIS : DForm_4<25, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2), 904 "oris $dst, $src1, $src2", IntGeneral, 905 [(set GPRC:$dst, (or GPRC:$src1, imm16ShiftedZExt:$src2))]>; 906def XORI : DForm_4<26, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2), 907 "xori $dst, $src1, $src2", IntGeneral, 908 [(set GPRC:$dst, (xor GPRC:$src1, immZExt16:$src2))]>; 909def XORIS : DForm_4<27, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2), 910 "xoris $dst, $src1, $src2", IntGeneral, 911 [(set GPRC:$dst, (xor GPRC:$src1,imm16ShiftedZExt:$src2))]>; 912def NOP : DForm_4_zero<24, (outs), (ins), "nop", IntGeneral, 913 []>; 914def CMPWI : DForm_5_ext<11, (outs CRRC:$crD), (ins GPRC:$rA, s16imm:$imm), 915 "cmpwi $crD, $rA, $imm", IntCompare>; 916def CMPLWI : DForm_6_ext<10, (outs CRRC:$dst), (ins GPRC:$src1, u16imm:$src2), 917 "cmplwi $dst, $src1, $src2", IntCompare>; 918} 919 920 921let PPC970_Unit = 1 in { // FXU Operations. 922def NAND : XForm_6<31, 476, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB), 923 "nand $rA, $rS, $rB", IntGeneral, 924 [(set GPRC:$rA, (not (and GPRC:$rS, GPRC:$rB)))]>; 925def AND : XForm_6<31, 28, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB), 926 "and $rA, $rS, $rB", IntGeneral, 927 [(set GPRC:$rA, (and GPRC:$rS, GPRC:$rB))]>; 928def ANDC : XForm_6<31, 60, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB), 929 "andc $rA, $rS, $rB", IntGeneral, 930 [(set GPRC:$rA, (and GPRC:$rS, (not GPRC:$rB)))]>; 931def OR : XForm_6<31, 444, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB), 932 "or $rA, $rS, $rB", IntGeneral, 933 [(set GPRC:$rA, (or GPRC:$rS, GPRC:$rB))]>; 934def NOR : XForm_6<31, 124, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB), 935 "nor $rA, $rS, $rB", IntGeneral, 936 [(set GPRC:$rA, (not (or GPRC:$rS, GPRC:$rB)))]>; 937def ORC : XForm_6<31, 412, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB), 938 "orc $rA, $rS, $rB", IntGeneral, 939 [(set GPRC:$rA, (or GPRC:$rS, (not GPRC:$rB)))]>; 940def EQV : XForm_6<31, 284, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB), 941 "eqv $rA, $rS, $rB", IntGeneral, 942 [(set GPRC:$rA, (not (xor GPRC:$rS, GPRC:$rB)))]>; 943def XOR : XForm_6<31, 316, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB), 944 "xor $rA, $rS, $rB", IntGeneral, 945 [(set GPRC:$rA, (xor GPRC:$rS, GPRC:$rB))]>; 946def SLW : XForm_6<31, 24, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB), 947 "slw $rA, $rS, $rB", IntGeneral, 948 [(set GPRC:$rA, (PPCshl GPRC:$rS, GPRC:$rB))]>; 949def SRW : XForm_6<31, 536, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB), 950 "srw $rA, $rS, $rB", IntGeneral, 951 [(set GPRC:$rA, (PPCsrl GPRC:$rS, GPRC:$rB))]>; 952let Defs = [CARRY] in { 953def SRAW : XForm_6<31, 792, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB), 954 "sraw $rA, $rS, $rB", IntShift, 955 [(set GPRC:$rA, (PPCsra GPRC:$rS, GPRC:$rB))]>; 956} 957} 958 959let PPC970_Unit = 1 in { // FXU Operations. 960let Defs = [CARRY] in { 961def SRAWI : XForm_10<31, 824, (outs GPRC:$rA), (ins GPRC:$rS, u5imm:$SH), 962 "srawi $rA, $rS, $SH", IntShift, 963 [(set GPRC:$rA, (sra GPRC:$rS, (i32 imm:$SH)))]>; 964} 965def CNTLZW : XForm_11<31, 26, (outs GPRC:$rA), (ins GPRC:$rS), 966 "cntlzw $rA, $rS", IntGeneral, 967 [(set GPRC:$rA, (ctlz GPRC:$rS))]>; 968def EXTSB : XForm_11<31, 954, (outs GPRC:$rA), (ins GPRC:$rS), 969 "extsb $rA, $rS", IntGeneral, 970 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i8))]>; 971def EXTSH : XForm_11<31, 922, (outs GPRC:$rA), (ins GPRC:$rS), 972 "extsh $rA, $rS", IntGeneral, 973 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i16))]>; 974 975def CMPW : XForm_16_ext<31, 0, (outs CRRC:$crD), (ins GPRC:$rA, GPRC:$rB), 976 "cmpw $crD, $rA, $rB", IntCompare>; 977def CMPLW : XForm_16_ext<31, 32, (outs CRRC:$crD), (ins GPRC:$rA, GPRC:$rB), 978 "cmplw $crD, $rA, $rB", IntCompare>; 979} 980let PPC970_Unit = 3 in { // FPU Operations. 981//def FCMPO : XForm_17<63, 32, (outs CRRC:$crD), (ins FPRC:$fA, FPRC:$fB), 982// "fcmpo $crD, $fA, $fB", FPCompare>; 983def FCMPUS : XForm_17<63, 0, (outs CRRC:$crD), (ins F4RC:$fA, F4RC:$fB), 984 "fcmpu $crD, $fA, $fB", FPCompare>; 985def FCMPUD : XForm_17<63, 0, (outs CRRC:$crD), (ins F8RC:$fA, F8RC:$fB), 986 "fcmpu $crD, $fA, $fB", FPCompare>; 987 988let Uses = [RM] in { 989 def FCTIWZ : XForm_26<63, 15, (outs F8RC:$frD), (ins F8RC:$frB), 990 "fctiwz $frD, $frB", FPGeneral, 991 [(set F8RC:$frD, (PPCfctiwz F8RC:$frB))]>; 992 def FRSP : XForm_26<63, 12, (outs F4RC:$frD), (ins F8RC:$frB), 993 "frsp $frD, $frB", FPGeneral, 994 [(set F4RC:$frD, (fround F8RC:$frB))]>; 995 def FSQRT : XForm_26<63, 22, (outs F8RC:$frD), (ins F8RC:$frB), 996 "fsqrt $frD, $frB", FPSqrt, 997 [(set F8RC:$frD, (fsqrt F8RC:$frB))]>; 998 def FSQRTS : XForm_26<59, 22, (outs F4RC:$frD), (ins F4RC:$frB), 999 "fsqrts $frD, $frB", FPSqrt, 1000 [(set F4RC:$frD, (fsqrt F4RC:$frB))]>; 1001 } 1002} 1003 1004/// Note that FMR is defined as pseudo-ops on the PPC970 because they are 1005/// often coalesced away and we don't want the dispatch group builder to think 1006/// that they will fill slots (which could cause the load of a LSU reject to 1007/// sneak into a d-group with a store). 1008def FMR : XForm_26<63, 72, (outs F4RC:$frD), (ins F4RC:$frB), 1009 "fmr $frD, $frB", FPGeneral, 1010 []>, // (set F4RC:$frD, F4RC:$frB) 1011 PPC970_Unit_Pseudo; 1012 1013let PPC970_Unit = 3 in { // FPU Operations. 1014// These are artificially split into two different forms, for 4/8 byte FP. 1015def FABSS : XForm_26<63, 264, (outs F4RC:$frD), (ins F4RC:$frB), 1016 "fabs $frD, $frB", FPGeneral, 1017 [(set F4RC:$frD, (fabs F4RC:$frB))]>; 1018def FABSD : XForm_26<63, 264, (outs F8RC:$frD), (ins F8RC:$frB), 1019 "fabs $frD, $frB", FPGeneral, 1020 [(set F8RC:$frD, (fabs F8RC:$frB))]>; 1021def FNABSS : XForm_26<63, 136, (outs F4RC:$frD), (ins F4RC:$frB), 1022 "fnabs $frD, $frB", FPGeneral, 1023 [(set F4RC:$frD, (fneg (fabs F4RC:$frB)))]>; 1024def FNABSD : XForm_26<63, 136, (outs F8RC:$frD), (ins F8RC:$frB), 1025 "fnabs $frD, $frB", FPGeneral, 1026 [(set F8RC:$frD, (fneg (fabs F8RC:$frB)))]>; 1027def FNEGS : XForm_26<63, 40, (outs F4RC:$frD), (ins F4RC:$frB), 1028 "fneg $frD, $frB", FPGeneral, 1029 [(set F4RC:$frD, (fneg F4RC:$frB))]>; 1030def FNEGD : XForm_26<63, 40, (outs F8RC:$frD), (ins F8RC:$frB), 1031 "fneg $frD, $frB", FPGeneral, 1032 [(set F8RC:$frD, (fneg F8RC:$frB))]>; 1033} 1034 1035 1036// XL-Form instructions. condition register logical ops. 1037// 1038def MCRF : XLForm_3<19, 0, (outs CRRC:$BF), (ins CRRC:$BFA), 1039 "mcrf $BF, $BFA", BrMCR>, 1040 PPC970_DGroup_First, PPC970_Unit_CRU; 1041 1042def CREQV : XLForm_1<19, 289, (outs CRBITRC:$CRD), 1043 (ins CRBITRC:$CRA, CRBITRC:$CRB), 1044 "creqv $CRD, $CRA, $CRB", BrCR, 1045 []>; 1046 1047def CROR : XLForm_1<19, 449, (outs CRBITRC:$CRD), 1048 (ins CRBITRC:$CRA, CRBITRC:$CRB), 1049 "cror $CRD, $CRA, $CRB", BrCR, 1050 []>; 1051 1052def CRSET : XLForm_1_ext<19, 289, (outs CRBITRC:$dst), (ins), 1053 "creqv $dst, $dst, $dst", BrCR, 1054 []>; 1055 1056// XFX-Form instructions. Instructions that deal with SPRs. 1057// 1058let Uses = [CTR] in { 1059def MFCTR : XFXForm_1_ext<31, 339, 9, (outs GPRC:$rT), (ins), 1060 "mfctr $rT", SprMFSPR>, 1061 PPC970_DGroup_First, PPC970_Unit_FXU; 1062} 1063let Defs = [CTR], Pattern = [(PPCmtctr GPRC:$rS)] in { 1064def MTCTR : XFXForm_7_ext<31, 467, 9, (outs), (ins GPRC:$rS), 1065 "mtctr $rS", SprMTSPR>, 1066 PPC970_DGroup_First, PPC970_Unit_FXU; 1067} 1068 1069let Defs = [LR] in { 1070def MTLR : XFXForm_7_ext<31, 467, 8, (outs), (ins GPRC:$rS), 1071 "mtlr $rS", SprMTSPR>, 1072 PPC970_DGroup_First, PPC970_Unit_FXU; 1073} 1074let Uses = [LR] in { 1075def MFLR : XFXForm_1_ext<31, 339, 8, (outs GPRC:$rT), (ins), 1076 "mflr $rT", SprMFSPR>, 1077 PPC970_DGroup_First, PPC970_Unit_FXU; 1078} 1079 1080// Move to/from VRSAVE: despite being a SPR, the VRSAVE register is renamed like 1081// a GPR on the PPC970. As such, copies in and out have the same performance 1082// characteristics as an OR instruction. 1083def MTVRSAVE : XFXForm_7_ext<31, 467, 256, (outs), (ins GPRC:$rS), 1084 "mtspr 256, $rS", IntGeneral>, 1085 PPC970_DGroup_Single, PPC970_Unit_FXU; 1086def MFVRSAVE : XFXForm_1_ext<31, 339, 256, (outs GPRC:$rT), (ins), 1087 "mfspr $rT, 256", IntGeneral>, 1088 PPC970_DGroup_First, PPC970_Unit_FXU; 1089 1090def MTCRF : XFXForm_5<31, 144, (outs), (ins crbitm:$FXM, GPRC:$rS), 1091 "mtcrf $FXM, $rS", BrMCRX>, 1092 PPC970_MicroCode, PPC970_Unit_CRU; 1093 1094// This is a pseudo for MFCR, which implicitly uses all 8 of its subregisters; 1095// declaring that here gives the local register allocator problems with this: 1096// vreg = MCRF CR0 1097// MFCR <kill of whatever preg got assigned to vreg> 1098// while not declaring it breaks DeadMachineInstructionElimination. 1099// As it turns out, in all cases where we currently use this, 1100// we're only interested in one subregister of it. Represent this in the 1101// instruction to keep the register allocator from becoming confused. 1102// 1103// FIXME: Make this a real Pseudo instruction when the JIT switches to MC. 1104def MFCRpseud: XFXForm_3<31, 19, (outs GPRC:$rT), (ins crbitm:$FXM), 1105 "", SprMFCR>, 1106 PPC970_MicroCode, PPC970_Unit_CRU; 1107 1108def MFCR : XFXForm_3<31, 19, (outs GPRC:$rT), (ins), 1109 "mfcr $rT", SprMFCR>, 1110 PPC970_MicroCode, PPC970_Unit_CRU; 1111 1112def MFOCRF: XFXForm_5a<31, 19, (outs GPRC:$rT), (ins crbitm:$FXM), 1113 "mfcr $rT, $FXM", SprMFCR>, 1114 PPC970_DGroup_First, PPC970_Unit_CRU; 1115 1116// Instructions to manipulate FPSCR. Only long double handling uses these. 1117// FPSCR is not modelled; we use the SDNode Flag to keep things in order. 1118 1119let Uses = [RM], Defs = [RM] in { 1120 def MTFSB0 : XForm_43<63, 70, (outs), (ins u5imm:$FM), 1121 "mtfsb0 $FM", IntMTFSB0, 1122 [(PPCmtfsb0 (i32 imm:$FM))]>, 1123 PPC970_DGroup_Single, PPC970_Unit_FPU; 1124 def MTFSB1 : XForm_43<63, 38, (outs), (ins u5imm:$FM), 1125 "mtfsb1 $FM", IntMTFSB0, 1126 [(PPCmtfsb1 (i32 imm:$FM))]>, 1127 PPC970_DGroup_Single, PPC970_Unit_FPU; 1128 // MTFSF does not actually produce an FP result. We pretend it copies 1129 // input reg B to the output. If we didn't do this it would look like the 1130 // instruction had no outputs (because we aren't modelling the FPSCR) and 1131 // it would be deleted. 1132 def MTFSF : XFLForm<63, 711, (outs F8RC:$FRA), 1133 (ins i32imm:$FM, F8RC:$rT, F8RC:$FRB), 1134 "mtfsf $FM, $rT", "$FRB = $FRA", IntMTFSB0, 1135 [(set F8RC:$FRA, (PPCmtfsf (i32 imm:$FM), 1136 F8RC:$rT, F8RC:$FRB))]>, 1137 PPC970_DGroup_Single, PPC970_Unit_FPU; 1138} 1139let Uses = [RM] in { 1140 def MFFS : XForm_42<63, 583, (outs F8RC:$rT), (ins), 1141 "mffs $rT", IntMFFS, 1142 [(set F8RC:$rT, (PPCmffs))]>, 1143 PPC970_DGroup_Single, PPC970_Unit_FPU; 1144 def FADDrtz: AForm_2<63, 21, 1145 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB), 1146 "fadd $FRT, $FRA, $FRB", FPGeneral, 1147 [(set F8RC:$FRT, (PPCfaddrtz F8RC:$FRA, F8RC:$FRB))]>, 1148 PPC970_DGroup_Single, PPC970_Unit_FPU; 1149} 1150 1151 1152let PPC970_Unit = 1 in { // FXU Operations. 1153 1154// XO-Form instructions. Arithmetic instructions that can set overflow bit 1155// 1156def ADD4 : XOForm_1<31, 266, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB), 1157 "add $rT, $rA, $rB", IntGeneral, 1158 [(set GPRC:$rT, (add GPRC:$rA, GPRC:$rB))]>; 1159let Defs = [CARRY] in { 1160def ADDC : XOForm_1<31, 10, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB), 1161 "addc $rT, $rA, $rB", IntGeneral, 1162 [(set GPRC:$rT, (addc GPRC:$rA, GPRC:$rB))]>, 1163 PPC970_DGroup_Cracked; 1164} 1165def DIVW : XOForm_1<31, 491, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB), 1166 "divw $rT, $rA, $rB", IntDivW, 1167 [(set GPRC:$rT, (sdiv GPRC:$rA, GPRC:$rB))]>, 1168 PPC970_DGroup_First, PPC970_DGroup_Cracked; 1169def DIVWU : XOForm_1<31, 459, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB), 1170 "divwu $rT, $rA, $rB", IntDivW, 1171 [(set GPRC:$rT, (udiv GPRC:$rA, GPRC:$rB))]>, 1172 PPC970_DGroup_First, PPC970_DGroup_Cracked; 1173def MULHW : XOForm_1<31, 75, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB), 1174 "mulhw $rT, $rA, $rB", IntMulHW, 1175 [(set GPRC:$rT, (mulhs GPRC:$rA, GPRC:$rB))]>; 1176def MULHWU : XOForm_1<31, 11, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB), 1177 "mulhwu $rT, $rA, $rB", IntMulHWU, 1178 [(set GPRC:$rT, (mulhu GPRC:$rA, GPRC:$rB))]>; 1179def MULLW : XOForm_1<31, 235, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB), 1180 "mullw $rT, $rA, $rB", IntMulHW, 1181 [(set GPRC:$rT, (mul GPRC:$rA, GPRC:$rB))]>; 1182def SUBF : XOForm_1<31, 40, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB), 1183 "subf $rT, $rA, $rB", IntGeneral, 1184 [(set GPRC:$rT, (sub GPRC:$rB, GPRC:$rA))]>; 1185let Defs = [CARRY] in { 1186def SUBFC : XOForm_1<31, 8, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB), 1187 "subfc $rT, $rA, $rB", IntGeneral, 1188 [(set GPRC:$rT, (subc GPRC:$rB, GPRC:$rA))]>, 1189 PPC970_DGroup_Cracked; 1190} 1191def NEG : XOForm_3<31, 104, 0, (outs GPRC:$rT), (ins GPRC:$rA), 1192 "neg $rT, $rA", IntGeneral, 1193 [(set GPRC:$rT, (ineg GPRC:$rA))]>; 1194let Uses = [CARRY], Defs = [CARRY] in { 1195def ADDE : XOForm_1<31, 138, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB), 1196 "adde $rT, $rA, $rB", IntGeneral, 1197 [(set GPRC:$rT, (adde GPRC:$rA, GPRC:$rB))]>; 1198def ADDME : XOForm_3<31, 234, 0, (outs GPRC:$rT), (ins GPRC:$rA), 1199 "addme $rT, $rA", IntGeneral, 1200 [(set GPRC:$rT, (adde GPRC:$rA, -1))]>; 1201def ADDZE : XOForm_3<31, 202, 0, (outs GPRC:$rT), (ins GPRC:$rA), 1202 "addze $rT, $rA", IntGeneral, 1203 [(set GPRC:$rT, (adde GPRC:$rA, 0))]>; 1204def SUBFE : XOForm_1<31, 136, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB), 1205 "subfe $rT, $rA, $rB", IntGeneral, 1206 [(set GPRC:$rT, (sube GPRC:$rB, GPRC:$rA))]>; 1207def SUBFME : XOForm_3<31, 232, 0, (outs GPRC:$rT), (ins GPRC:$rA), 1208 "subfme $rT, $rA", IntGeneral, 1209 [(set GPRC:$rT, (sube -1, GPRC:$rA))]>; 1210def SUBFZE : XOForm_3<31, 200, 0, (outs GPRC:$rT), (ins GPRC:$rA), 1211 "subfze $rT, $rA", IntGeneral, 1212 [(set GPRC:$rT, (sube 0, GPRC:$rA))]>; 1213} 1214} 1215 1216// A-Form instructions. Most of the instructions executed in the FPU are of 1217// this type. 1218// 1219let PPC970_Unit = 3 in { // FPU Operations. 1220let Uses = [RM] in { 1221 def FMADD : AForm_1<63, 29, 1222 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB), 1223 "fmadd $FRT, $FRA, $FRC, $FRB", FPFused, 1224 [(set F8RC:$FRT, (fadd (fmul F8RC:$FRA, F8RC:$FRC), 1225 F8RC:$FRB))]>, 1226 Requires<[FPContractions]>; 1227 def FMADDS : AForm_1<59, 29, 1228 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB), 1229 "fmadds $FRT, $FRA, $FRC, $FRB", FPGeneral, 1230 [(set F4RC:$FRT, (fadd (fmul F4RC:$FRA, F4RC:$FRC), 1231 F4RC:$FRB))]>, 1232 Requires<[FPContractions]>; 1233 def FMSUB : AForm_1<63, 28, 1234 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB), 1235 "fmsub $FRT, $FRA, $FRC, $FRB", FPFused, 1236 [(set F8RC:$FRT, (fsub (fmul F8RC:$FRA, F8RC:$FRC), 1237 F8RC:$FRB))]>, 1238 Requires<[FPContractions]>; 1239 def FMSUBS : AForm_1<59, 28, 1240 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB), 1241 "fmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral, 1242 [(set F4RC:$FRT, (fsub (fmul F4RC:$FRA, F4RC:$FRC), 1243 F4RC:$FRB))]>, 1244 Requires<[FPContractions]>; 1245 def FNMADD : AForm_1<63, 31, 1246 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB), 1247 "fnmadd $FRT, $FRA, $FRC, $FRB", FPFused, 1248 [(set F8RC:$FRT, (fneg (fadd (fmul F8RC:$FRA, F8RC:$FRC), 1249 F8RC:$FRB)))]>, 1250 Requires<[FPContractions]>; 1251 def FNMADDS : AForm_1<59, 31, 1252 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB), 1253 "fnmadds $FRT, $FRA, $FRC, $FRB", FPGeneral, 1254 [(set F4RC:$FRT, (fneg (fadd (fmul F4RC:$FRA, F4RC:$FRC), 1255 F4RC:$FRB)))]>, 1256 Requires<[FPContractions]>; 1257 def FNMSUB : AForm_1<63, 30, 1258 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB), 1259 "fnmsub $FRT, $FRA, $FRC, $FRB", FPFused, 1260 [(set F8RC:$FRT, (fneg (fsub (fmul F8RC:$FRA, F8RC:$FRC), 1261 F8RC:$FRB)))]>, 1262 Requires<[FPContractions]>; 1263 def FNMSUBS : AForm_1<59, 30, 1264 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB), 1265 "fnmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral, 1266 [(set F4RC:$FRT, (fneg (fsub (fmul F4RC:$FRA, F4RC:$FRC), 1267 F4RC:$FRB)))]>, 1268 Requires<[FPContractions]>; 1269} 1270// FSEL is artificially split into 4 and 8-byte forms for the result. To avoid 1271// having 4 of these, force the comparison to always be an 8-byte double (code 1272// should use an FMRSD if the input comparison value really wants to be a float) 1273// and 4/8 byte forms for the result and operand type.. 1274def FSELD : AForm_1<63, 23, 1275 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB), 1276 "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral, 1277 [(set F8RC:$FRT, (PPCfsel F8RC:$FRA,F8RC:$FRC,F8RC:$FRB))]>; 1278def FSELS : AForm_1<63, 23, 1279 (outs F4RC:$FRT), (ins F8RC:$FRA, F4RC:$FRC, F4RC:$FRB), 1280 "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral, 1281 [(set F4RC:$FRT, (PPCfsel F8RC:$FRA,F4RC:$FRC,F4RC:$FRB))]>; 1282let Uses = [RM] in { 1283 def FADD : AForm_2<63, 21, 1284 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB), 1285 "fadd $FRT, $FRA, $FRB", FPGeneral, 1286 [(set F8RC:$FRT, (fadd F8RC:$FRA, F8RC:$FRB))]>; 1287 def FADDS : AForm_2<59, 21, 1288 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB), 1289 "fadds $FRT, $FRA, $FRB", FPGeneral, 1290 [(set F4RC:$FRT, (fadd F4RC:$FRA, F4RC:$FRB))]>; 1291 def FDIV : AForm_2<63, 18, 1292 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB), 1293 "fdiv $FRT, $FRA, $FRB", FPDivD, 1294 [(set F8RC:$FRT, (fdiv F8RC:$FRA, F8RC:$FRB))]>; 1295 def FDIVS : AForm_2<59, 18, 1296 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB), 1297 "fdivs $FRT, $FRA, $FRB", FPDivS, 1298 [(set F4RC:$FRT, (fdiv F4RC:$FRA, F4RC:$FRB))]>; 1299 def FMUL : AForm_3<63, 25, 1300 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB), 1301 "fmul $FRT, $FRA, $FRB", FPFused, 1302 [(set F8RC:$FRT, (fmul F8RC:$FRA, F8RC:$FRB))]>; 1303 def FMULS : AForm_3<59, 25, 1304 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB), 1305 "fmuls $FRT, $FRA, $FRB", FPGeneral, 1306 [(set F4RC:$FRT, (fmul F4RC:$FRA, F4RC:$FRB))]>; 1307 def FSUB : AForm_2<63, 20, 1308 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB), 1309 "fsub $FRT, $FRA, $FRB", FPGeneral, 1310 [(set F8RC:$FRT, (fsub F8RC:$FRA, F8RC:$FRB))]>; 1311 def FSUBS : AForm_2<59, 20, 1312 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB), 1313 "fsubs $FRT, $FRA, $FRB", FPGeneral, 1314 [(set F4RC:$FRT, (fsub F4RC:$FRA, F4RC:$FRB))]>; 1315 } 1316} 1317 1318let PPC970_Unit = 1 in { // FXU Operations. 1319// M-Form instructions. rotate and mask instructions. 1320// 1321let isCommutable = 1 in { 1322// RLWIMI can be commuted if the rotate amount is zero. 1323def RLWIMI : MForm_2<20, 1324 (outs GPRC:$rA), (ins GPRC:$rSi, GPRC:$rS, u5imm:$SH, u5imm:$MB, 1325 u5imm:$ME), "rlwimi $rA, $rS, $SH, $MB, $ME", IntRotate, 1326 []>, PPC970_DGroup_Cracked, RegConstraint<"$rSi = $rA">, 1327 NoEncode<"$rSi">; 1328} 1329def RLWINM : MForm_2<21, 1330 (outs GPRC:$rA), (ins GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME), 1331 "rlwinm $rA, $rS, $SH, $MB, $ME", IntGeneral, 1332 []>; 1333def RLWINMo : MForm_2<21, 1334 (outs GPRC:$rA), (ins GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME), 1335 "rlwinm. $rA, $rS, $SH, $MB, $ME", IntGeneral, 1336 []>, isDOT, PPC970_DGroup_Cracked; 1337def RLWNM : MForm_2<23, 1338 (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB, u5imm:$MB, u5imm:$ME), 1339 "rlwnm $rA, $rS, $rB, $MB, $ME", IntGeneral, 1340 []>; 1341} 1342 1343 1344//===----------------------------------------------------------------------===// 1345// PowerPC Instruction Patterns 1346// 1347 1348// Arbitrary immediate support. Implement in terms of LIS/ORI. 1349def : Pat<(i32 imm:$imm), 1350 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>; 1351 1352// Implement the 'not' operation with the NOR instruction. 1353def NOT : Pat<(not GPRC:$in), 1354 (NOR GPRC:$in, GPRC:$in)>; 1355 1356// ADD an arbitrary immediate. 1357def : Pat<(add GPRC:$in, imm:$imm), 1358 (ADDIS (ADDI GPRC:$in, (LO16 imm:$imm)), (HA16 imm:$imm))>; 1359// OR an arbitrary immediate. 1360def : Pat<(or GPRC:$in, imm:$imm), 1361 (ORIS (ORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>; 1362// XOR an arbitrary immediate. 1363def : Pat<(xor GPRC:$in, imm:$imm), 1364 (XORIS (XORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>; 1365// SUBFIC 1366def : Pat<(sub immSExt16:$imm, GPRC:$in), 1367 (SUBFIC GPRC:$in, imm:$imm)>; 1368 1369// SHL/SRL 1370def : Pat<(shl GPRC:$in, (i32 imm:$imm)), 1371 (RLWINM GPRC:$in, imm:$imm, 0, (SHL32 imm:$imm))>; 1372def : Pat<(srl GPRC:$in, (i32 imm:$imm)), 1373 (RLWINM GPRC:$in, (SRL32 imm:$imm), imm:$imm, 31)>; 1374 1375// ROTL 1376def : Pat<(rotl GPRC:$in, GPRC:$sh), 1377 (RLWNM GPRC:$in, GPRC:$sh, 0, 31)>; 1378def : Pat<(rotl GPRC:$in, (i32 imm:$imm)), 1379 (RLWINM GPRC:$in, imm:$imm, 0, 31)>; 1380 1381// RLWNM 1382def : Pat<(and (rotl GPRC:$in, GPRC:$sh), maskimm32:$imm), 1383 (RLWNM GPRC:$in, GPRC:$sh, (MB maskimm32:$imm), (ME maskimm32:$imm))>; 1384 1385// Calls 1386def : Pat<(PPCcall_Darwin (i32 tglobaladdr:$dst)), 1387 (BL_Darwin tglobaladdr:$dst)>; 1388def : Pat<(PPCcall_Darwin (i32 texternalsym:$dst)), 1389 (BL_Darwin texternalsym:$dst)>; 1390def : Pat<(PPCcall_SVR4 (i32 tglobaladdr:$dst)), 1391 (BL_SVR4 tglobaladdr:$dst)>; 1392def : Pat<(PPCcall_SVR4 (i32 texternalsym:$dst)), 1393 (BL_SVR4 texternalsym:$dst)>; 1394 1395 1396def : Pat<(PPCtc_return (i32 tglobaladdr:$dst), imm:$imm), 1397 (TCRETURNdi tglobaladdr:$dst, imm:$imm)>; 1398 1399def : Pat<(PPCtc_return (i32 texternalsym:$dst), imm:$imm), 1400 (TCRETURNdi texternalsym:$dst, imm:$imm)>; 1401 1402def : Pat<(PPCtc_return CTRRC:$dst, imm:$imm), 1403 (TCRETURNri CTRRC:$dst, imm:$imm)>; 1404 1405 1406 1407// Hi and Lo for Darwin Global Addresses. 1408def : Pat<(PPChi tglobaladdr:$in, 0), (LIS tglobaladdr:$in)>; 1409def : Pat<(PPClo tglobaladdr:$in, 0), (LI tglobaladdr:$in)>; 1410def : Pat<(PPChi tconstpool:$in, 0), (LIS tconstpool:$in)>; 1411def : Pat<(PPClo tconstpool:$in, 0), (LI tconstpool:$in)>; 1412def : Pat<(PPChi tjumptable:$in, 0), (LIS tjumptable:$in)>; 1413def : Pat<(PPClo tjumptable:$in, 0), (LI tjumptable:$in)>; 1414def : Pat<(PPChi tblockaddress:$in, 0), (LIS tblockaddress:$in)>; 1415def : Pat<(PPClo tblockaddress:$in, 0), (LI tblockaddress:$in)>; 1416def : Pat<(add GPRC:$in, (PPChi tglobaladdr:$g, 0)), 1417 (ADDIS GPRC:$in, tglobaladdr:$g)>; 1418def : Pat<(add GPRC:$in, (PPChi tconstpool:$g, 0)), 1419 (ADDIS GPRC:$in, tconstpool:$g)>; 1420def : Pat<(add GPRC:$in, (PPChi tjumptable:$g, 0)), 1421 (ADDIS GPRC:$in, tjumptable:$g)>; 1422def : Pat<(add GPRC:$in, (PPChi tblockaddress:$g, 0)), 1423 (ADDIS GPRC:$in, tblockaddress:$g)>; 1424 1425// Fused negative multiply subtract, alternate pattern 1426def : Pat<(fsub F8RC:$B, (fmul F8RC:$A, F8RC:$C)), 1427 (FNMSUB F8RC:$A, F8RC:$C, F8RC:$B)>, 1428 Requires<[FPContractions]>; 1429def : Pat<(fsub F4RC:$B, (fmul F4RC:$A, F4RC:$C)), 1430 (FNMSUBS F4RC:$A, F4RC:$C, F4RC:$B)>, 1431 Requires<[FPContractions]>; 1432 1433// Standard shifts. These are represented separately from the real shifts above 1434// so that we can distinguish between shifts that allow 5-bit and 6-bit shift 1435// amounts. 1436def : Pat<(sra GPRC:$rS, GPRC:$rB), 1437 (SRAW GPRC:$rS, GPRC:$rB)>; 1438def : Pat<(srl GPRC:$rS, GPRC:$rB), 1439 (SRW GPRC:$rS, GPRC:$rB)>; 1440def : Pat<(shl GPRC:$rS, GPRC:$rB), 1441 (SLW GPRC:$rS, GPRC:$rB)>; 1442 1443def : Pat<(zextloadi1 iaddr:$src), 1444 (LBZ iaddr:$src)>; 1445def : Pat<(zextloadi1 xaddr:$src), 1446 (LBZX xaddr:$src)>; 1447def : Pat<(extloadi1 iaddr:$src), 1448 (LBZ iaddr:$src)>; 1449def : Pat<(extloadi1 xaddr:$src), 1450 (LBZX xaddr:$src)>; 1451def : Pat<(extloadi8 iaddr:$src), 1452 (LBZ iaddr:$src)>; 1453def : Pat<(extloadi8 xaddr:$src), 1454 (LBZX xaddr:$src)>; 1455def : Pat<(extloadi16 iaddr:$src), 1456 (LHZ iaddr:$src)>; 1457def : Pat<(extloadi16 xaddr:$src), 1458 (LHZX xaddr:$src)>; 1459def : Pat<(f64 (extloadf32 iaddr:$src)), 1460 (COPY_TO_REGCLASS (LFS iaddr:$src), F8RC)>; 1461def : Pat<(f64 (extloadf32 xaddr:$src)), 1462 (COPY_TO_REGCLASS (LFSX xaddr:$src), F8RC)>; 1463 1464def : Pat<(f64 (fextend F4RC:$src)), 1465 (COPY_TO_REGCLASS F4RC:$src, F8RC)>; 1466 1467// Memory barriers 1468def : Pat<(membarrier (i32 imm /*ll*/), 1469 (i32 imm /*ls*/), 1470 (i32 imm /*sl*/), 1471 (i32 imm /*ss*/), 1472 (i32 imm /*device*/)), 1473 (SYNC)>; 1474 1475include "PPCInstrAltivec.td" 1476include "PPCInstr64Bit.td" 1477