PPCInstrInfo.td revision 221345
1//===- PPCInstrInfo.td - The PowerPC Instruction Set -------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the subset of the 32-bit PowerPC instruction set, as used 11// by the PowerPC instruction selector. 12// 13//===----------------------------------------------------------------------===// 14 15include "PPCInstrFormats.td" 16 17//===----------------------------------------------------------------------===// 18// PowerPC specific type constraints. 19// 20def SDT_PPCstfiwx : SDTypeProfile<0, 2, [ // stfiwx 21 SDTCisVT<0, f64>, SDTCisPtrTy<1> 22]>; 23def SDT_PPCCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>; 24def SDT_PPCCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, 25 SDTCisVT<1, i32> ]>; 26def SDT_PPCvperm : SDTypeProfile<1, 3, [ 27 SDTCisVT<3, v16i8>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2> 28]>; 29 30def SDT_PPCvcmp : SDTypeProfile<1, 3, [ 31 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32> 32]>; 33 34def SDT_PPCcondbr : SDTypeProfile<0, 3, [ 35 SDTCisVT<0, i32>, SDTCisVT<2, OtherVT> 36]>; 37 38def SDT_PPClbrx : SDTypeProfile<1, 2, [ 39 SDTCisVT<0, i32>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT> 40]>; 41def SDT_PPCstbrx : SDTypeProfile<0, 3, [ 42 SDTCisVT<0, i32>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT> 43]>; 44 45def SDT_PPClarx : SDTypeProfile<1, 1, [ 46 SDTCisInt<0>, SDTCisPtrTy<1> 47]>; 48def SDT_PPCstcx : SDTypeProfile<0, 2, [ 49 SDTCisInt<0>, SDTCisPtrTy<1> 50]>; 51 52def SDT_PPCTC_ret : SDTypeProfile<0, 2, [ 53 SDTCisPtrTy<0>, SDTCisVT<1, i32> 54]>; 55 56def SDT_PPCnop : SDTypeProfile<0, 0, []>; 57 58//===----------------------------------------------------------------------===// 59// PowerPC specific DAG Nodes. 60// 61 62def PPCfcfid : SDNode<"PPCISD::FCFID" , SDTFPUnaryOp, []>; 63def PPCfctidz : SDNode<"PPCISD::FCTIDZ", SDTFPUnaryOp, []>; 64def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>; 65def PPCstfiwx : SDNode<"PPCISD::STFIWX", SDT_PPCstfiwx, 66 [SDNPHasChain, SDNPMayStore]>; 67 68// This sequence is used for long double->int conversions. It changes the 69// bits in the FPSCR which is not modelled. 70def PPCmffs : SDNode<"PPCISD::MFFS", SDTypeProfile<1, 0, [SDTCisVT<0, f64>]>, 71 [SDNPOutGlue]>; 72def PPCmtfsb0 : SDNode<"PPCISD::MTFSB0", SDTypeProfile<0, 1, [SDTCisInt<0>]>, 73 [SDNPInGlue, SDNPOutGlue]>; 74def PPCmtfsb1 : SDNode<"PPCISD::MTFSB1", SDTypeProfile<0, 1, [SDTCisInt<0>]>, 75 [SDNPInGlue, SDNPOutGlue]>; 76def PPCfaddrtz: SDNode<"PPCISD::FADDRTZ", SDTFPBinOp, 77 [SDNPInGlue, SDNPOutGlue]>; 78def PPCmtfsf : SDNode<"PPCISD::MTFSF", SDTypeProfile<1, 3, 79 [SDTCisVT<0, f64>, SDTCisInt<1>, SDTCisVT<2, f64>, 80 SDTCisVT<3, f64>]>, 81 [SDNPInGlue]>; 82 83def PPCfsel : SDNode<"PPCISD::FSEL", 84 // Type constraint for fsel. 85 SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, 86 SDTCisFP<0>, SDTCisVT<1, f64>]>, []>; 87 88def PPChi : SDNode<"PPCISD::Hi", SDTIntBinOp, []>; 89def PPClo : SDNode<"PPCISD::Lo", SDTIntBinOp, []>; 90def PPCtoc_entry: SDNode<"PPCISD::TOC_ENTRY", SDTIntBinOp, [SDNPMayLoad]>; 91def PPCvmaddfp : SDNode<"PPCISD::VMADDFP", SDTFPTernaryOp, []>; 92def PPCvnmsubfp : SDNode<"PPCISD::VNMSUBFP", SDTFPTernaryOp, []>; 93 94def PPCvperm : SDNode<"PPCISD::VPERM", SDT_PPCvperm, []>; 95 96// These nodes represent the 32-bit PPC shifts that operate on 6-bit shift 97// amounts. These nodes are generated by the multi-precision shift code. 98def PPCsrl : SDNode<"PPCISD::SRL" , SDTIntShiftOp>; 99def PPCsra : SDNode<"PPCISD::SRA" , SDTIntShiftOp>; 100def PPCshl : SDNode<"PPCISD::SHL" , SDTIntShiftOp>; 101 102def PPCextsw_32 : SDNode<"PPCISD::EXTSW_32" , SDTIntUnaryOp>; 103def PPCstd_32 : SDNode<"PPCISD::STD_32" , SDTStore, 104 [SDNPHasChain, SDNPMayStore]>; 105 106// These are target-independent nodes, but have target-specific formats. 107def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeqStart, 108 [SDNPHasChain, SDNPOutGlue]>; 109def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_PPCCallSeqEnd, 110 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 111 112def SDT_PPCCall : SDTypeProfile<0, -1, [SDTCisInt<0>]>; 113def PPCcall_Darwin : SDNode<"PPCISD::CALL_Darwin", SDT_PPCCall, 114 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 115 SDNPVariadic]>; 116def PPCcall_SVR4 : SDNode<"PPCISD::CALL_SVR4", SDT_PPCCall, 117 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 118 SDNPVariadic]>; 119def PPCnop : SDNode<"PPCISD::NOP", SDT_PPCnop, [SDNPInGlue, SDNPOutGlue]>; 120def PPCload : SDNode<"PPCISD::LOAD", SDTypeProfile<1, 1, []>, 121 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 122def PPCload_toc : SDNode<"PPCISD::LOAD_TOC", SDTypeProfile<0, 1, []>, 123 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>; 124def PPCtoc_restore : SDNode<"PPCISD::TOC_RESTORE", SDTypeProfile<0, 0, []>, 125 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>; 126def PPCmtctr : SDNode<"PPCISD::MTCTR", SDT_PPCCall, 127 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 128def PPCbctrl_Darwin : SDNode<"PPCISD::BCTRL_Darwin", SDTNone, 129 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 130 SDNPVariadic]>; 131 132def PPCbctrl_SVR4 : SDNode<"PPCISD::BCTRL_SVR4", SDTNone, 133 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 134 SDNPVariadic]>; 135 136def retflag : SDNode<"PPCISD::RET_FLAG", SDTNone, 137 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 138 139def PPCtc_return : SDNode<"PPCISD::TC_RETURN", SDT_PPCTC_ret, 140 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 141 142def PPCvcmp : SDNode<"PPCISD::VCMP" , SDT_PPCvcmp, []>; 143def PPCvcmp_o : SDNode<"PPCISD::VCMPo", SDT_PPCvcmp, [SDNPOutGlue]>; 144 145def PPCcondbranch : SDNode<"PPCISD::COND_BRANCH", SDT_PPCcondbr, 146 [SDNPHasChain, SDNPOptInGlue]>; 147 148def PPClbrx : SDNode<"PPCISD::LBRX", SDT_PPClbrx, 149 [SDNPHasChain, SDNPMayLoad]>; 150def PPCstbrx : SDNode<"PPCISD::STBRX", SDT_PPCstbrx, 151 [SDNPHasChain, SDNPMayStore]>; 152 153// Instructions to support atomic operations 154def PPClarx : SDNode<"PPCISD::LARX", SDT_PPClarx, 155 [SDNPHasChain, SDNPMayLoad]>; 156def PPCstcx : SDNode<"PPCISD::STCX", SDT_PPCstcx, 157 [SDNPHasChain, SDNPMayStore]>; 158 159// Instructions to support dynamic alloca. 160def SDTDynOp : SDTypeProfile<1, 2, []>; 161def PPCdynalloc : SDNode<"PPCISD::DYNALLOC", SDTDynOp, [SDNPHasChain]>; 162 163//===----------------------------------------------------------------------===// 164// PowerPC specific transformation functions and pattern fragments. 165// 166 167def SHL32 : SDNodeXForm<imm, [{ 168 // Transformation function: 31 - imm 169 return getI32Imm(31 - N->getZExtValue()); 170}]>; 171 172def SRL32 : SDNodeXForm<imm, [{ 173 // Transformation function: 32 - imm 174 return N->getZExtValue() ? getI32Imm(32 - N->getZExtValue()) : getI32Imm(0); 175}]>; 176 177def LO16 : SDNodeXForm<imm, [{ 178 // Transformation function: get the low 16 bits. 179 return getI32Imm((unsigned short)N->getZExtValue()); 180}]>; 181 182def HI16 : SDNodeXForm<imm, [{ 183 // Transformation function: shift the immediate value down into the low bits. 184 return getI32Imm((unsigned)N->getZExtValue() >> 16); 185}]>; 186 187def HA16 : SDNodeXForm<imm, [{ 188 // Transformation function: shift the immediate value down into the low bits. 189 signed int Val = N->getZExtValue(); 190 return getI32Imm((Val - (signed short)Val) >> 16); 191}]>; 192def MB : SDNodeXForm<imm, [{ 193 // Transformation function: get the start bit of a mask 194 unsigned mb = 0, me; 195 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me); 196 return getI32Imm(mb); 197}]>; 198 199def ME : SDNodeXForm<imm, [{ 200 // Transformation function: get the end bit of a mask 201 unsigned mb, me = 0; 202 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me); 203 return getI32Imm(me); 204}]>; 205def maskimm32 : PatLeaf<(imm), [{ 206 // maskImm predicate - True if immediate is a run of ones. 207 unsigned mb, me; 208 if (N->getValueType(0) == MVT::i32) 209 return isRunOfOnes((unsigned)N->getZExtValue(), mb, me); 210 else 211 return false; 212}]>; 213 214def immSExt16 : PatLeaf<(imm), [{ 215 // immSExt16 predicate - True if the immediate fits in a 16-bit sign extended 216 // field. Used by instructions like 'addi'. 217 if (N->getValueType(0) == MVT::i32) 218 return (int32_t)N->getZExtValue() == (short)N->getZExtValue(); 219 else 220 return (int64_t)N->getZExtValue() == (short)N->getZExtValue(); 221}]>; 222def immZExt16 : PatLeaf<(imm), [{ 223 // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended 224 // field. Used by instructions like 'ori'. 225 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue(); 226}], LO16>; 227 228// imm16Shifted* - These match immediates where the low 16-bits are zero. There 229// are two forms: imm16ShiftedSExt and imm16ShiftedZExt. These two forms are 230// identical in 32-bit mode, but in 64-bit mode, they return true if the 231// immediate fits into a sign/zero extended 32-bit immediate (with the low bits 232// clear). 233def imm16ShiftedZExt : PatLeaf<(imm), [{ 234 // imm16ShiftedZExt predicate - True if only bits in the top 16-bits of the 235 // immediate are set. Used by instructions like 'xoris'. 236 return (N->getZExtValue() & ~uint64_t(0xFFFF0000)) == 0; 237}], HI16>; 238 239def imm16ShiftedSExt : PatLeaf<(imm), [{ 240 // imm16ShiftedSExt predicate - True if only bits in the top 16-bits of the 241 // immediate are set. Used by instructions like 'addis'. Identical to 242 // imm16ShiftedZExt in 32-bit mode. 243 if (N->getZExtValue() & 0xFFFF) return false; 244 if (N->getValueType(0) == MVT::i32) 245 return true; 246 // For 64-bit, make sure it is sext right. 247 return N->getZExtValue() == (uint64_t)(int)N->getZExtValue(); 248}], HI16>; 249 250 251//===----------------------------------------------------------------------===// 252// PowerPC Flag Definitions. 253 254class isPPC64 { bit PPC64 = 1; } 255class isDOT { 256 list<Register> Defs = [CR0]; 257 bit RC = 1; 258} 259 260class RegConstraint<string C> { 261 string Constraints = C; 262} 263class NoEncode<string E> { 264 string DisableEncoding = E; 265} 266 267 268//===----------------------------------------------------------------------===// 269// PowerPC Operand Definitions. 270 271def s5imm : Operand<i32> { 272 let PrintMethod = "printS5ImmOperand"; 273} 274def u5imm : Operand<i32> { 275 let PrintMethod = "printU5ImmOperand"; 276} 277def u6imm : Operand<i32> { 278 let PrintMethod = "printU6ImmOperand"; 279} 280def s16imm : Operand<i32> { 281 let PrintMethod = "printS16ImmOperand"; 282} 283def u16imm : Operand<i32> { 284 let PrintMethod = "printU16ImmOperand"; 285} 286def s16immX4 : Operand<i32> { // Multiply imm by 4 before printing. 287 let PrintMethod = "printS16X4ImmOperand"; 288} 289def directbrtarget : Operand<OtherVT> { 290 let PrintMethod = "printBranchOperand"; 291 let EncoderMethod = "getDirectBrEncoding"; 292} 293def condbrtarget : Operand<OtherVT> { 294 let PrintMethod = "printBranchOperand"; 295 let EncoderMethod = "getCondBrEncoding"; 296} 297def calltarget : Operand<iPTR> { 298 let EncoderMethod = "getDirectBrEncoding"; 299} 300def aaddr : Operand<iPTR> { 301 let PrintMethod = "printAbsAddrOperand"; 302} 303def piclabel: Operand<iPTR> {} 304def symbolHi: Operand<i32> { 305 let PrintMethod = "printSymbolHi"; 306 let EncoderMethod = "getHA16Encoding"; 307} 308def symbolLo: Operand<i32> { 309 let PrintMethod = "printSymbolLo"; 310 let EncoderMethod = "getLO16Encoding"; 311} 312def crbitm: Operand<i8> { 313 let PrintMethod = "printcrbitm"; 314 let EncoderMethod = "get_crbitm_encoding"; 315} 316// Address operands 317def memri : Operand<iPTR> { 318 let PrintMethod = "printMemRegImm"; 319 let MIOperandInfo = (ops i32imm:$imm, ptr_rc:$reg); 320 let EncoderMethod = "getMemRIEncoding"; 321} 322def memrr : Operand<iPTR> { 323 let PrintMethod = "printMemRegReg"; 324 let MIOperandInfo = (ops ptr_rc, ptr_rc); 325} 326def memrix : Operand<iPTR> { // memri where the imm is shifted 2 bits. 327 let PrintMethod = "printMemRegImmShifted"; 328 let MIOperandInfo = (ops i32imm:$imm, ptr_rc:$reg); 329 let EncoderMethod = "getMemRIXEncoding"; 330} 331def tocentry : Operand<iPTR> { 332 let MIOperandInfo = (ops i32imm:$imm); 333} 334 335// PowerPC Predicate operand. 20 = (0<<5)|20 = always, CR0 is a dummy reg 336// that doesn't matter. 337def pred : PredicateOperand<OtherVT, (ops imm, CRRC), 338 (ops (i32 20), (i32 zero_reg))> { 339 let PrintMethod = "printPredicateOperand"; 340} 341 342// Define PowerPC specific addressing mode. 343def iaddr : ComplexPattern<iPTR, 2, "SelectAddrImm", [], []>; 344def xaddr : ComplexPattern<iPTR, 2, "SelectAddrIdx", [], []>; 345def xoaddr : ComplexPattern<iPTR, 2, "SelectAddrIdxOnly",[], []>; 346def ixaddr : ComplexPattern<iPTR, 2, "SelectAddrImmShift", [], []>; // "std" 347 348/// This is just the offset part of iaddr, used for preinc. 349def iaddroff : ComplexPattern<iPTR, 1, "SelectAddrImmOffs", [], []>; 350 351//===----------------------------------------------------------------------===// 352// PowerPC Instruction Predicate Definitions. 353def FPContractions : Predicate<"!NoExcessFPPrecision">; 354def In32BitMode : Predicate<"!PPCSubTarget.isPPC64()">; 355def In64BitMode : Predicate<"PPCSubTarget.isPPC64()">; 356 357 358//===----------------------------------------------------------------------===// 359// PowerPC Instruction Definitions. 360 361// Pseudo-instructions: 362 363let hasCtrlDep = 1 in { 364let Defs = [R1], Uses = [R1] in { 365def ADJCALLSTACKDOWN : Pseudo<(outs), (ins u16imm:$amt), "", 366 [(callseq_start timm:$amt)]>; 367def ADJCALLSTACKUP : Pseudo<(outs), (ins u16imm:$amt1, u16imm:$amt2), "", 368 [(callseq_end timm:$amt1, timm:$amt2)]>; 369} 370 371def UPDATE_VRSAVE : Pseudo<(outs GPRC:$rD), (ins GPRC:$rS), 372 "UPDATE_VRSAVE $rD, $rS", []>; 373} 374 375let Defs = [R1], Uses = [R1] in 376def DYNALLOC : Pseudo<(outs GPRC:$result), (ins GPRC:$negsize, memri:$fpsi), "", 377 [(set GPRC:$result, 378 (PPCdynalloc GPRC:$negsize, iaddr:$fpsi))]>; 379 380// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after 381// instruction selection into a branch sequence. 382let usesCustomInserter = 1, // Expanded after instruction selection. 383 PPC970_Single = 1 in { 384 def SELECT_CC_I4 : Pseudo<(outs GPRC:$dst), (ins CRRC:$cond, GPRC:$T, GPRC:$F, 385 i32imm:$BROPC), "", 386 []>; 387 def SELECT_CC_I8 : Pseudo<(outs G8RC:$dst), (ins CRRC:$cond, G8RC:$T, G8RC:$F, 388 i32imm:$BROPC), "", 389 []>; 390 def SELECT_CC_F4 : Pseudo<(outs F4RC:$dst), (ins CRRC:$cond, F4RC:$T, F4RC:$F, 391 i32imm:$BROPC), "", 392 []>; 393 def SELECT_CC_F8 : Pseudo<(outs F8RC:$dst), (ins CRRC:$cond, F8RC:$T, F8RC:$F, 394 i32imm:$BROPC), "", 395 []>; 396 def SELECT_CC_VRRC: Pseudo<(outs VRRC:$dst), (ins CRRC:$cond, VRRC:$T, VRRC:$F, 397 i32imm:$BROPC), "", 398 []>; 399} 400 401// SPILL_CR - Indicate that we're dumping the CR register, so we'll need to 402// scavenge a register for it. 403def SPILL_CR : Pseudo<(outs), (ins GPRC:$cond, memri:$F), 404 "", []>; 405 406let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in { 407 let isReturn = 1, Uses = [LR, RM] in 408 def BLR : XLForm_2_br<19, 16, 0, (outs), (ins pred:$p), 409 "b${p:cc}lr ${p:reg}", BrB, 410 [(retflag)]>; 411 let isBranch = 1, isIndirectBranch = 1, Uses = [CTR] in 412 def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>; 413} 414 415let Defs = [LR] in 416 def MovePCtoLR : Pseudo<(outs), (ins piclabel:$label), "", []>, 417 PPC970_Unit_BRU; 418 419let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in { 420 let isBarrier = 1 in { 421 def B : IForm<18, 0, 0, (outs), (ins directbrtarget:$dst), 422 "b $dst", BrB, 423 [(br bb:$dst)]>; 424 } 425 426 // BCC represents an arbitrary conditional branch on a predicate. 427 // FIXME: should be able to write a pattern for PPCcondbranch, but can't use 428 // a two-value operand where a dag node expects two operands. :( 429 def BCC : BForm<16, 0, 0, (outs), (ins pred:$cond, condbrtarget:$dst), 430 "b${cond:cc} ${cond:reg}, $dst" 431 /*[(PPCcondbranch CRRC:$crS, imm:$opc, bb:$dst)]*/>; 432} 433 434// Darwin ABI Calls. 435let isCall = 1, PPC970_Unit = 7, 436 // All calls clobber the non-callee saved registers... 437 Defs = [R0,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12, 438 F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13, 439 V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16,V17,V18,V19, 440 LR,CTR, 441 CR0,CR1,CR5,CR6,CR7,CARRY] in { 442 // Convenient aliases for call instructions 443 let Uses = [RM] in { 444 def BL_Darwin : IForm<18, 0, 1, 445 (outs), (ins calltarget:$func, variable_ops), 446 "bl $func", BrB, []>; // See Pat patterns below. 447 def BLA_Darwin : IForm<18, 1, 1, 448 (outs), (ins aaddr:$func, variable_ops), 449 "bla $func", BrB, [(PPCcall_Darwin (i32 imm:$func))]>; 450 } 451 let Uses = [CTR, RM] in { 452 def BCTRL_Darwin : XLForm_2_ext<19, 528, 20, 0, 1, 453 (outs), (ins variable_ops), 454 "bctrl", BrB, 455 [(PPCbctrl_Darwin)]>, Requires<[In32BitMode]>; 456 } 457} 458 459// SVR4 ABI Calls. 460let isCall = 1, PPC970_Unit = 7, 461 // All calls clobber the non-callee saved registers... 462 Defs = [R0,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12, 463 F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13, 464 V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16,V17,V18,V19, 465 LR,CTR, 466 CR0,CR1,CR5,CR6,CR7,CARRY] in { 467 // Convenient aliases for call instructions 468 let Uses = [RM] in { 469 def BL_SVR4 : IForm<18, 0, 1, 470 (outs), (ins calltarget:$func, variable_ops), 471 "bl $func", BrB, []>; // See Pat patterns below. 472 def BLA_SVR4 : IForm<18, 1, 1, 473 (outs), (ins aaddr:$func, variable_ops), 474 "bla $func", BrB, 475 [(PPCcall_SVR4 (i32 imm:$func))]>; 476 } 477 let Uses = [CTR, RM] in { 478 def BCTRL_SVR4 : XLForm_2_ext<19, 528, 20, 0, 1, 479 (outs), (ins variable_ops), 480 "bctrl", BrB, 481 [(PPCbctrl_SVR4)]>, Requires<[In32BitMode]>; 482 } 483} 484 485 486let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 487def TCRETURNdi :Pseudo< (outs), 488 (ins calltarget:$dst, i32imm:$offset, variable_ops), 489 "#TC_RETURNd $dst $offset", 490 []>; 491 492 493let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 494def TCRETURNai :Pseudo<(outs), (ins aaddr:$func, i32imm:$offset, variable_ops), 495 "#TC_RETURNa $func $offset", 496 [(PPCtc_return (i32 imm:$func), imm:$offset)]>; 497 498let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 499def TCRETURNri : Pseudo<(outs), (ins CTRRC:$dst, i32imm:$offset, variable_ops), 500 "#TC_RETURNr $dst $offset", 501 []>; 502 503 504let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1, 505 isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR, RM] in 506def TAILBCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>, 507 Requires<[In32BitMode]>; 508 509 510 511let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 512 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 513def TAILB : IForm<18, 0, 0, (outs), (ins calltarget:$dst), 514 "b $dst", BrB, 515 []>; 516 517 518let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 519 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 520def TAILBA : IForm<18, 0, 0, (outs), (ins aaddr:$dst), 521 "ba $dst", BrB, 522 []>; 523 524 525// DCB* instructions. 526def DCBA : DCB_Form<758, 0, (outs), (ins memrr:$dst), 527 "dcba $dst", LdStDCBF, [(int_ppc_dcba xoaddr:$dst)]>, 528 PPC970_DGroup_Single; 529def DCBF : DCB_Form<86, 0, (outs), (ins memrr:$dst), 530 "dcbf $dst", LdStDCBF, [(int_ppc_dcbf xoaddr:$dst)]>, 531 PPC970_DGroup_Single; 532def DCBI : DCB_Form<470, 0, (outs), (ins memrr:$dst), 533 "dcbi $dst", LdStDCBF, [(int_ppc_dcbi xoaddr:$dst)]>, 534 PPC970_DGroup_Single; 535def DCBST : DCB_Form<54, 0, (outs), (ins memrr:$dst), 536 "dcbst $dst", LdStDCBF, [(int_ppc_dcbst xoaddr:$dst)]>, 537 PPC970_DGroup_Single; 538def DCBT : DCB_Form<278, 0, (outs), (ins memrr:$dst), 539 "dcbt $dst", LdStDCBF, [(int_ppc_dcbt xoaddr:$dst)]>, 540 PPC970_DGroup_Single; 541def DCBTST : DCB_Form<246, 0, (outs), (ins memrr:$dst), 542 "dcbtst $dst", LdStDCBF, [(int_ppc_dcbtst xoaddr:$dst)]>, 543 PPC970_DGroup_Single; 544def DCBZ : DCB_Form<1014, 0, (outs), (ins memrr:$dst), 545 "dcbz $dst", LdStDCBF, [(int_ppc_dcbz xoaddr:$dst)]>, 546 PPC970_DGroup_Single; 547def DCBZL : DCB_Form<1014, 1, (outs), (ins memrr:$dst), 548 "dcbzl $dst", LdStDCBF, [(int_ppc_dcbzl xoaddr:$dst)]>, 549 PPC970_DGroup_Single; 550 551// Atomic operations 552let usesCustomInserter = 1 in { 553 let Defs = [CR0] in { 554 def ATOMIC_LOAD_ADD_I8 : Pseudo< 555 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "", 556 [(set GPRC:$dst, (atomic_load_add_8 xoaddr:$ptr, GPRC:$incr))]>; 557 def ATOMIC_LOAD_SUB_I8 : Pseudo< 558 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "", 559 [(set GPRC:$dst, (atomic_load_sub_8 xoaddr:$ptr, GPRC:$incr))]>; 560 def ATOMIC_LOAD_AND_I8 : Pseudo< 561 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "", 562 [(set GPRC:$dst, (atomic_load_and_8 xoaddr:$ptr, GPRC:$incr))]>; 563 def ATOMIC_LOAD_OR_I8 : Pseudo< 564 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "", 565 [(set GPRC:$dst, (atomic_load_or_8 xoaddr:$ptr, GPRC:$incr))]>; 566 def ATOMIC_LOAD_XOR_I8 : Pseudo< 567 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "", 568 [(set GPRC:$dst, (atomic_load_xor_8 xoaddr:$ptr, GPRC:$incr))]>; 569 def ATOMIC_LOAD_NAND_I8 : Pseudo< 570 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "", 571 [(set GPRC:$dst, (atomic_load_nand_8 xoaddr:$ptr, GPRC:$incr))]>; 572 def ATOMIC_LOAD_ADD_I16 : Pseudo< 573 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "", 574 [(set GPRC:$dst, (atomic_load_add_16 xoaddr:$ptr, GPRC:$incr))]>; 575 def ATOMIC_LOAD_SUB_I16 : Pseudo< 576 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "", 577 [(set GPRC:$dst, (atomic_load_sub_16 xoaddr:$ptr, GPRC:$incr))]>; 578 def ATOMIC_LOAD_AND_I16 : Pseudo< 579 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "", 580 [(set GPRC:$dst, (atomic_load_and_16 xoaddr:$ptr, GPRC:$incr))]>; 581 def ATOMIC_LOAD_OR_I16 : Pseudo< 582 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "", 583 [(set GPRC:$dst, (atomic_load_or_16 xoaddr:$ptr, GPRC:$incr))]>; 584 def ATOMIC_LOAD_XOR_I16 : Pseudo< 585 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "", 586 [(set GPRC:$dst, (atomic_load_xor_16 xoaddr:$ptr, GPRC:$incr))]>; 587 def ATOMIC_LOAD_NAND_I16 : Pseudo< 588 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "", 589 [(set GPRC:$dst, (atomic_load_nand_16 xoaddr:$ptr, GPRC:$incr))]>; 590 def ATOMIC_LOAD_ADD_I32 : Pseudo< 591 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "", 592 [(set GPRC:$dst, (atomic_load_add_32 xoaddr:$ptr, GPRC:$incr))]>; 593 def ATOMIC_LOAD_SUB_I32 : Pseudo< 594 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "", 595 [(set GPRC:$dst, (atomic_load_sub_32 xoaddr:$ptr, GPRC:$incr))]>; 596 def ATOMIC_LOAD_AND_I32 : Pseudo< 597 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "", 598 [(set GPRC:$dst, (atomic_load_and_32 xoaddr:$ptr, GPRC:$incr))]>; 599 def ATOMIC_LOAD_OR_I32 : Pseudo< 600 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "", 601 [(set GPRC:$dst, (atomic_load_or_32 xoaddr:$ptr, GPRC:$incr))]>; 602 def ATOMIC_LOAD_XOR_I32 : Pseudo< 603 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "", 604 [(set GPRC:$dst, (atomic_load_xor_32 xoaddr:$ptr, GPRC:$incr))]>; 605 def ATOMIC_LOAD_NAND_I32 : Pseudo< 606 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "", 607 [(set GPRC:$dst, (atomic_load_nand_32 xoaddr:$ptr, GPRC:$incr))]>; 608 609 def ATOMIC_CMP_SWAP_I8 : Pseudo< 610 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$old, GPRC:$new), "", 611 [(set GPRC:$dst, 612 (atomic_cmp_swap_8 xoaddr:$ptr, GPRC:$old, GPRC:$new))]>; 613 def ATOMIC_CMP_SWAP_I16 : Pseudo< 614 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$old, GPRC:$new), "", 615 [(set GPRC:$dst, 616 (atomic_cmp_swap_16 xoaddr:$ptr, GPRC:$old, GPRC:$new))]>; 617 def ATOMIC_CMP_SWAP_I32 : Pseudo< 618 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$old, GPRC:$new), "", 619 [(set GPRC:$dst, 620 (atomic_cmp_swap_32 xoaddr:$ptr, GPRC:$old, GPRC:$new))]>; 621 622 def ATOMIC_SWAP_I8 : Pseudo< 623 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$new), "", 624 [(set GPRC:$dst, (atomic_swap_8 xoaddr:$ptr, GPRC:$new))]>; 625 def ATOMIC_SWAP_I16 : Pseudo< 626 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$new), "", 627 [(set GPRC:$dst, (atomic_swap_16 xoaddr:$ptr, GPRC:$new))]>; 628 def ATOMIC_SWAP_I32 : Pseudo< 629 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$new), "", 630 [(set GPRC:$dst, (atomic_swap_32 xoaddr:$ptr, GPRC:$new))]>; 631 } 632} 633 634// Instructions to support atomic operations 635def LWARX : XForm_1<31, 20, (outs GPRC:$rD), (ins memrr:$src), 636 "lwarx $rD, $src", LdStLWARX, 637 [(set GPRC:$rD, (PPClarx xoaddr:$src))]>; 638 639let Defs = [CR0] in 640def STWCX : XForm_1<31, 150, (outs), (ins GPRC:$rS, memrr:$dst), 641 "stwcx. $rS, $dst", LdStSTWCX, 642 [(PPCstcx GPRC:$rS, xoaddr:$dst)]>, 643 isDOT; 644 645let isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in 646def TRAP : XForm_24<31, 4, (outs), (ins), "trap", LdStGeneral, [(trap)]>; 647 648//===----------------------------------------------------------------------===// 649// PPC32 Load Instructions. 650// 651 652// Unindexed (r+i) Loads. 653let canFoldAsLoad = 1, PPC970_Unit = 2 in { 654def LBZ : DForm_1<34, (outs GPRC:$rD), (ins memri:$src), 655 "lbz $rD, $src", LdStGeneral, 656 [(set GPRC:$rD, (zextloadi8 iaddr:$src))]>; 657def LHA : DForm_1<42, (outs GPRC:$rD), (ins memri:$src), 658 "lha $rD, $src", LdStLHA, 659 [(set GPRC:$rD, (sextloadi16 iaddr:$src))]>, 660 PPC970_DGroup_Cracked; 661def LHZ : DForm_1<40, (outs GPRC:$rD), (ins memri:$src), 662 "lhz $rD, $src", LdStGeneral, 663 [(set GPRC:$rD, (zextloadi16 iaddr:$src))]>; 664def LWZ : DForm_1<32, (outs GPRC:$rD), (ins memri:$src), 665 "lwz $rD, $src", LdStGeneral, 666 [(set GPRC:$rD, (load iaddr:$src))]>; 667 668def LFS : DForm_1<48, (outs F4RC:$rD), (ins memri:$src), 669 "lfs $rD, $src", LdStLFDU, 670 [(set F4RC:$rD, (load iaddr:$src))]>; 671def LFD : DForm_1<50, (outs F8RC:$rD), (ins memri:$src), 672 "lfd $rD, $src", LdStLFD, 673 [(set F8RC:$rD, (load iaddr:$src))]>; 674 675 676// Unindexed (r+i) Loads with Update (preinc). 677let mayLoad = 1 in { 678def LBZU : DForm_1<35, (outs GPRC:$rD, ptr_rc:$ea_result), (ins memri:$addr), 679 "lbzu $rD, $addr", LdStGeneral, 680 []>, RegConstraint<"$addr.reg = $ea_result">, 681 NoEncode<"$ea_result">; 682 683def LHAU : DForm_1<43, (outs GPRC:$rD, ptr_rc:$ea_result), (ins memri:$addr), 684 "lhau $rD, $addr", LdStGeneral, 685 []>, RegConstraint<"$addr.reg = $ea_result">, 686 NoEncode<"$ea_result">; 687 688def LHZU : DForm_1<41, (outs GPRC:$rD, ptr_rc:$ea_result), (ins memri:$addr), 689 "lhzu $rD, $addr", LdStGeneral, 690 []>, RegConstraint<"$addr.reg = $ea_result">, 691 NoEncode<"$ea_result">; 692 693def LWZU : DForm_1<33, (outs GPRC:$rD, ptr_rc:$ea_result), (ins memri:$addr), 694 "lwzu $rD, $addr", LdStGeneral, 695 []>, RegConstraint<"$addr.reg = $ea_result">, 696 NoEncode<"$ea_result">; 697 698def LFSU : DForm_1<49, (outs F4RC:$rD, ptr_rc:$ea_result), (ins memri:$addr), 699 "lfs $rD, $addr", LdStLFDU, 700 []>, RegConstraint<"$addr.reg = $ea_result">, 701 NoEncode<"$ea_result">; 702 703def LFDU : DForm_1<51, (outs F8RC:$rD, ptr_rc:$ea_result), (ins memri:$addr), 704 "lfd $rD, $addr", LdStLFD, 705 []>, RegConstraint<"$addr.reg = $ea_result">, 706 NoEncode<"$ea_result">; 707} 708} 709 710// Indexed (r+r) Loads. 711// 712let canFoldAsLoad = 1, PPC970_Unit = 2 in { 713def LBZX : XForm_1<31, 87, (outs GPRC:$rD), (ins memrr:$src), 714 "lbzx $rD, $src", LdStGeneral, 715 [(set GPRC:$rD, (zextloadi8 xaddr:$src))]>; 716def LHAX : XForm_1<31, 343, (outs GPRC:$rD), (ins memrr:$src), 717 "lhax $rD, $src", LdStLHA, 718 [(set GPRC:$rD, (sextloadi16 xaddr:$src))]>, 719 PPC970_DGroup_Cracked; 720def LHZX : XForm_1<31, 279, (outs GPRC:$rD), (ins memrr:$src), 721 "lhzx $rD, $src", LdStGeneral, 722 [(set GPRC:$rD, (zextloadi16 xaddr:$src))]>; 723def LWZX : XForm_1<31, 23, (outs GPRC:$rD), (ins memrr:$src), 724 "lwzx $rD, $src", LdStGeneral, 725 [(set GPRC:$rD, (load xaddr:$src))]>; 726 727 728def LHBRX : XForm_1<31, 790, (outs GPRC:$rD), (ins memrr:$src), 729 "lhbrx $rD, $src", LdStGeneral, 730 [(set GPRC:$rD, (PPClbrx xoaddr:$src, i16))]>; 731def LWBRX : XForm_1<31, 534, (outs GPRC:$rD), (ins memrr:$src), 732 "lwbrx $rD, $src", LdStGeneral, 733 [(set GPRC:$rD, (PPClbrx xoaddr:$src, i32))]>; 734 735def LFSX : XForm_25<31, 535, (outs F4RC:$frD), (ins memrr:$src), 736 "lfsx $frD, $src", LdStLFDU, 737 [(set F4RC:$frD, (load xaddr:$src))]>; 738def LFDX : XForm_25<31, 599, (outs F8RC:$frD), (ins memrr:$src), 739 "lfdx $frD, $src", LdStLFDU, 740 [(set F8RC:$frD, (load xaddr:$src))]>; 741} 742 743//===----------------------------------------------------------------------===// 744// PPC32 Store Instructions. 745// 746 747// Unindexed (r+i) Stores. 748let PPC970_Unit = 2 in { 749def STB : DForm_1<38, (outs), (ins GPRC:$rS, memri:$src), 750 "stb $rS, $src", LdStGeneral, 751 [(truncstorei8 GPRC:$rS, iaddr:$src)]>; 752def STH : DForm_1<44, (outs), (ins GPRC:$rS, memri:$src), 753 "sth $rS, $src", LdStGeneral, 754 [(truncstorei16 GPRC:$rS, iaddr:$src)]>; 755def STW : DForm_1<36, (outs), (ins GPRC:$rS, memri:$src), 756 "stw $rS, $src", LdStGeneral, 757 [(store GPRC:$rS, iaddr:$src)]>; 758def STFS : DForm_1<52, (outs), (ins F4RC:$rS, memri:$dst), 759 "stfs $rS, $dst", LdStUX, 760 [(store F4RC:$rS, iaddr:$dst)]>; 761def STFD : DForm_1<54, (outs), (ins F8RC:$rS, memri:$dst), 762 "stfd $rS, $dst", LdStUX, 763 [(store F8RC:$rS, iaddr:$dst)]>; 764} 765 766// Unindexed (r+i) Stores with Update (preinc). 767let PPC970_Unit = 2 in { 768def STBU : DForm_1a<39, (outs ptr_rc:$ea_res), (ins GPRC:$rS, 769 symbolLo:$ptroff, ptr_rc:$ptrreg), 770 "stbu $rS, $ptroff($ptrreg)", LdStGeneral, 771 [(set ptr_rc:$ea_res, 772 (pre_truncsti8 GPRC:$rS, ptr_rc:$ptrreg, 773 iaddroff:$ptroff))]>, 774 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">; 775def STHU : DForm_1a<45, (outs ptr_rc:$ea_res), (ins GPRC:$rS, 776 symbolLo:$ptroff, ptr_rc:$ptrreg), 777 "sthu $rS, $ptroff($ptrreg)", LdStGeneral, 778 [(set ptr_rc:$ea_res, 779 (pre_truncsti16 GPRC:$rS, ptr_rc:$ptrreg, 780 iaddroff:$ptroff))]>, 781 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">; 782def STWU : DForm_1a<37, (outs ptr_rc:$ea_res), (ins GPRC:$rS, 783 symbolLo:$ptroff, ptr_rc:$ptrreg), 784 "stwu $rS, $ptroff($ptrreg)", LdStGeneral, 785 [(set ptr_rc:$ea_res, (pre_store GPRC:$rS, ptr_rc:$ptrreg, 786 iaddroff:$ptroff))]>, 787 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">; 788def STFSU : DForm_1a<37, (outs ptr_rc:$ea_res), (ins F4RC:$rS, 789 symbolLo:$ptroff, ptr_rc:$ptrreg), 790 "stfsu $rS, $ptroff($ptrreg)", LdStGeneral, 791 [(set ptr_rc:$ea_res, (pre_store F4RC:$rS, ptr_rc:$ptrreg, 792 iaddroff:$ptroff))]>, 793 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">; 794def STFDU : DForm_1a<37, (outs ptr_rc:$ea_res), (ins F8RC:$rS, 795 symbolLo:$ptroff, ptr_rc:$ptrreg), 796 "stfdu $rS, $ptroff($ptrreg)", LdStGeneral, 797 [(set ptr_rc:$ea_res, (pre_store F8RC:$rS, ptr_rc:$ptrreg, 798 iaddroff:$ptroff))]>, 799 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">; 800} 801 802 803// Indexed (r+r) Stores. 804// 805let PPC970_Unit = 2 in { 806def STBX : XForm_8<31, 215, (outs), (ins GPRC:$rS, memrr:$dst), 807 "stbx $rS, $dst", LdStGeneral, 808 [(truncstorei8 GPRC:$rS, xaddr:$dst)]>, 809 PPC970_DGroup_Cracked; 810def STHX : XForm_8<31, 407, (outs), (ins GPRC:$rS, memrr:$dst), 811 "sthx $rS, $dst", LdStGeneral, 812 [(truncstorei16 GPRC:$rS, xaddr:$dst)]>, 813 PPC970_DGroup_Cracked; 814def STWX : XForm_8<31, 151, (outs), (ins GPRC:$rS, memrr:$dst), 815 "stwx $rS, $dst", LdStGeneral, 816 [(store GPRC:$rS, xaddr:$dst)]>, 817 PPC970_DGroup_Cracked; 818 819let mayStore = 1 in { 820def STWUX : XForm_8<31, 183, (outs), (ins GPRC:$rS, GPRC:$rA, GPRC:$rB), 821 "stwux $rS, $rA, $rB", LdStGeneral, 822 []>; 823} 824def STHBRX: XForm_8<31, 918, (outs), (ins GPRC:$rS, memrr:$dst), 825 "sthbrx $rS, $dst", LdStGeneral, 826 [(PPCstbrx GPRC:$rS, xoaddr:$dst, i16)]>, 827 PPC970_DGroup_Cracked; 828def STWBRX: XForm_8<31, 662, (outs), (ins GPRC:$rS, memrr:$dst), 829 "stwbrx $rS, $dst", LdStGeneral, 830 [(PPCstbrx GPRC:$rS, xoaddr:$dst, i32)]>, 831 PPC970_DGroup_Cracked; 832 833def STFIWX: XForm_28<31, 983, (outs), (ins F8RC:$frS, memrr:$dst), 834 "stfiwx $frS, $dst", LdStUX, 835 [(PPCstfiwx F8RC:$frS, xoaddr:$dst)]>; 836 837def STFSX : XForm_28<31, 663, (outs), (ins F4RC:$frS, memrr:$dst), 838 "stfsx $frS, $dst", LdStUX, 839 [(store F4RC:$frS, xaddr:$dst)]>; 840def STFDX : XForm_28<31, 727, (outs), (ins F8RC:$frS, memrr:$dst), 841 "stfdx $frS, $dst", LdStUX, 842 [(store F8RC:$frS, xaddr:$dst)]>; 843} 844 845def SYNC : XForm_24_sync<31, 598, (outs), (ins), 846 "sync", LdStSync, 847 [(int_ppc_sync)]>; 848 849//===----------------------------------------------------------------------===// 850// PPC32 Arithmetic Instructions. 851// 852 853let PPC970_Unit = 1 in { // FXU Operations. 854def ADDI : DForm_2<14, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm), 855 "addi $rD, $rA, $imm", IntGeneral, 856 [(set GPRC:$rD, (add GPRC:$rA, immSExt16:$imm))]>; 857let Defs = [CARRY] in { 858def ADDIC : DForm_2<12, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm), 859 "addic $rD, $rA, $imm", IntGeneral, 860 [(set GPRC:$rD, (addc GPRC:$rA, immSExt16:$imm))]>, 861 PPC970_DGroup_Cracked; 862def ADDICo : DForm_2<13, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm), 863 "addic. $rD, $rA, $imm", IntGeneral, 864 []>; 865} 866def ADDIS : DForm_2<15, (outs GPRC:$rD), (ins GPRC:$rA, symbolHi:$imm), 867 "addis $rD, $rA, $imm", IntGeneral, 868 [(set GPRC:$rD, (add GPRC:$rA, imm16ShiftedSExt:$imm))]>; 869def LA : DForm_2<14, (outs GPRC:$rD), (ins GPRC:$rA, symbolLo:$sym), 870 "la $rD, $sym($rA)", IntGeneral, 871 [(set GPRC:$rD, (add GPRC:$rA, 872 (PPClo tglobaladdr:$sym, 0)))]>; 873def MULLI : DForm_2< 7, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm), 874 "mulli $rD, $rA, $imm", IntMulLI, 875 [(set GPRC:$rD, (mul GPRC:$rA, immSExt16:$imm))]>; 876let Defs = [CARRY] in { 877def SUBFIC : DForm_2< 8, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm), 878 "subfic $rD, $rA, $imm", IntGeneral, 879 [(set GPRC:$rD, (subc immSExt16:$imm, GPRC:$rA))]>; 880} 881 882let isReMaterializable = 1 in { 883 def LI : DForm_2_r0<14, (outs GPRC:$rD), (ins symbolLo:$imm), 884 "li $rD, $imm", IntGeneral, 885 [(set GPRC:$rD, immSExt16:$imm)]>; 886 def LIS : DForm_2_r0<15, (outs GPRC:$rD), (ins symbolHi:$imm), 887 "lis $rD, $imm", IntGeneral, 888 [(set GPRC:$rD, imm16ShiftedSExt:$imm)]>; 889} 890} 891 892let PPC970_Unit = 1 in { // FXU Operations. 893def ANDIo : DForm_4<28, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2), 894 "andi. $dst, $src1, $src2", IntGeneral, 895 [(set GPRC:$dst, (and GPRC:$src1, immZExt16:$src2))]>, 896 isDOT; 897def ANDISo : DForm_4<29, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2), 898 "andis. $dst, $src1, $src2", IntGeneral, 899 [(set GPRC:$dst, (and GPRC:$src1,imm16ShiftedZExt:$src2))]>, 900 isDOT; 901def ORI : DForm_4<24, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2), 902 "ori $dst, $src1, $src2", IntGeneral, 903 [(set GPRC:$dst, (or GPRC:$src1, immZExt16:$src2))]>; 904def ORIS : DForm_4<25, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2), 905 "oris $dst, $src1, $src2", IntGeneral, 906 [(set GPRC:$dst, (or GPRC:$src1, imm16ShiftedZExt:$src2))]>; 907def XORI : DForm_4<26, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2), 908 "xori $dst, $src1, $src2", IntGeneral, 909 [(set GPRC:$dst, (xor GPRC:$src1, immZExt16:$src2))]>; 910def XORIS : DForm_4<27, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2), 911 "xoris $dst, $src1, $src2", IntGeneral, 912 [(set GPRC:$dst, (xor GPRC:$src1,imm16ShiftedZExt:$src2))]>; 913def NOP : DForm_4_zero<24, (outs), (ins), "nop", IntGeneral, 914 []>; 915def CMPWI : DForm_5_ext<11, (outs CRRC:$crD), (ins GPRC:$rA, s16imm:$imm), 916 "cmpwi $crD, $rA, $imm", IntCompare>; 917def CMPLWI : DForm_6_ext<10, (outs CRRC:$dst), (ins GPRC:$src1, u16imm:$src2), 918 "cmplwi $dst, $src1, $src2", IntCompare>; 919} 920 921 922let PPC970_Unit = 1 in { // FXU Operations. 923def NAND : XForm_6<31, 476, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB), 924 "nand $rA, $rS, $rB", IntGeneral, 925 [(set GPRC:$rA, (not (and GPRC:$rS, GPRC:$rB)))]>; 926def AND : XForm_6<31, 28, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB), 927 "and $rA, $rS, $rB", IntGeneral, 928 [(set GPRC:$rA, (and GPRC:$rS, GPRC:$rB))]>; 929def ANDC : XForm_6<31, 60, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB), 930 "andc $rA, $rS, $rB", IntGeneral, 931 [(set GPRC:$rA, (and GPRC:$rS, (not GPRC:$rB)))]>; 932def OR : XForm_6<31, 444, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB), 933 "or $rA, $rS, $rB", IntGeneral, 934 [(set GPRC:$rA, (or GPRC:$rS, GPRC:$rB))]>; 935def NOR : XForm_6<31, 124, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB), 936 "nor $rA, $rS, $rB", IntGeneral, 937 [(set GPRC:$rA, (not (or GPRC:$rS, GPRC:$rB)))]>; 938def ORC : XForm_6<31, 412, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB), 939 "orc $rA, $rS, $rB", IntGeneral, 940 [(set GPRC:$rA, (or GPRC:$rS, (not GPRC:$rB)))]>; 941def EQV : XForm_6<31, 284, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB), 942 "eqv $rA, $rS, $rB", IntGeneral, 943 [(set GPRC:$rA, (not (xor GPRC:$rS, GPRC:$rB)))]>; 944def XOR : XForm_6<31, 316, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB), 945 "xor $rA, $rS, $rB", IntGeneral, 946 [(set GPRC:$rA, (xor GPRC:$rS, GPRC:$rB))]>; 947def SLW : XForm_6<31, 24, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB), 948 "slw $rA, $rS, $rB", IntGeneral, 949 [(set GPRC:$rA, (PPCshl GPRC:$rS, GPRC:$rB))]>; 950def SRW : XForm_6<31, 536, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB), 951 "srw $rA, $rS, $rB", IntGeneral, 952 [(set GPRC:$rA, (PPCsrl GPRC:$rS, GPRC:$rB))]>; 953let Defs = [CARRY] in { 954def SRAW : XForm_6<31, 792, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB), 955 "sraw $rA, $rS, $rB", IntShift, 956 [(set GPRC:$rA, (PPCsra GPRC:$rS, GPRC:$rB))]>; 957} 958} 959 960let PPC970_Unit = 1 in { // FXU Operations. 961let Defs = [CARRY] in { 962def SRAWI : XForm_10<31, 824, (outs GPRC:$rA), (ins GPRC:$rS, u5imm:$SH), 963 "srawi $rA, $rS, $SH", IntShift, 964 [(set GPRC:$rA, (sra GPRC:$rS, (i32 imm:$SH)))]>; 965} 966def CNTLZW : XForm_11<31, 26, (outs GPRC:$rA), (ins GPRC:$rS), 967 "cntlzw $rA, $rS", IntGeneral, 968 [(set GPRC:$rA, (ctlz GPRC:$rS))]>; 969def EXTSB : XForm_11<31, 954, (outs GPRC:$rA), (ins GPRC:$rS), 970 "extsb $rA, $rS", IntGeneral, 971 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i8))]>; 972def EXTSH : XForm_11<31, 922, (outs GPRC:$rA), (ins GPRC:$rS), 973 "extsh $rA, $rS", IntGeneral, 974 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i16))]>; 975 976def CMPW : XForm_16_ext<31, 0, (outs CRRC:$crD), (ins GPRC:$rA, GPRC:$rB), 977 "cmpw $crD, $rA, $rB", IntCompare>; 978def CMPLW : XForm_16_ext<31, 32, (outs CRRC:$crD), (ins GPRC:$rA, GPRC:$rB), 979 "cmplw $crD, $rA, $rB", IntCompare>; 980} 981let PPC970_Unit = 3 in { // FPU Operations. 982//def FCMPO : XForm_17<63, 32, (outs CRRC:$crD), (ins FPRC:$fA, FPRC:$fB), 983// "fcmpo $crD, $fA, $fB", FPCompare>; 984def FCMPUS : XForm_17<63, 0, (outs CRRC:$crD), (ins F4RC:$fA, F4RC:$fB), 985 "fcmpu $crD, $fA, $fB", FPCompare>; 986def FCMPUD : XForm_17<63, 0, (outs CRRC:$crD), (ins F8RC:$fA, F8RC:$fB), 987 "fcmpu $crD, $fA, $fB", FPCompare>; 988 989let Uses = [RM] in { 990 def FCTIWZ : XForm_26<63, 15, (outs F8RC:$frD), (ins F8RC:$frB), 991 "fctiwz $frD, $frB", FPGeneral, 992 [(set F8RC:$frD, (PPCfctiwz F8RC:$frB))]>; 993 def FRSP : XForm_26<63, 12, (outs F4RC:$frD), (ins F8RC:$frB), 994 "frsp $frD, $frB", FPGeneral, 995 [(set F4RC:$frD, (fround F8RC:$frB))]>; 996 def FSQRT : XForm_26<63, 22, (outs F8RC:$frD), (ins F8RC:$frB), 997 "fsqrt $frD, $frB", FPSqrt, 998 [(set F8RC:$frD, (fsqrt F8RC:$frB))]>; 999 def FSQRTS : XForm_26<59, 22, (outs F4RC:$frD), (ins F4RC:$frB), 1000 "fsqrts $frD, $frB", FPSqrt, 1001 [(set F4RC:$frD, (fsqrt F4RC:$frB))]>; 1002 } 1003} 1004 1005/// Note that FMR is defined as pseudo-ops on the PPC970 because they are 1006/// often coalesced away and we don't want the dispatch group builder to think 1007/// that they will fill slots (which could cause the load of a LSU reject to 1008/// sneak into a d-group with a store). 1009def FMR : XForm_26<63, 72, (outs F4RC:$frD), (ins F4RC:$frB), 1010 "fmr $frD, $frB", FPGeneral, 1011 []>, // (set F4RC:$frD, F4RC:$frB) 1012 PPC970_Unit_Pseudo; 1013 1014let PPC970_Unit = 3 in { // FPU Operations. 1015// These are artificially split into two different forms, for 4/8 byte FP. 1016def FABSS : XForm_26<63, 264, (outs F4RC:$frD), (ins F4RC:$frB), 1017 "fabs $frD, $frB", FPGeneral, 1018 [(set F4RC:$frD, (fabs F4RC:$frB))]>; 1019def FABSD : XForm_26<63, 264, (outs F8RC:$frD), (ins F8RC:$frB), 1020 "fabs $frD, $frB", FPGeneral, 1021 [(set F8RC:$frD, (fabs F8RC:$frB))]>; 1022def FNABSS : XForm_26<63, 136, (outs F4RC:$frD), (ins F4RC:$frB), 1023 "fnabs $frD, $frB", FPGeneral, 1024 [(set F4RC:$frD, (fneg (fabs F4RC:$frB)))]>; 1025def FNABSD : XForm_26<63, 136, (outs F8RC:$frD), (ins F8RC:$frB), 1026 "fnabs $frD, $frB", FPGeneral, 1027 [(set F8RC:$frD, (fneg (fabs F8RC:$frB)))]>; 1028def FNEGS : XForm_26<63, 40, (outs F4RC:$frD), (ins F4RC:$frB), 1029 "fneg $frD, $frB", FPGeneral, 1030 [(set F4RC:$frD, (fneg F4RC:$frB))]>; 1031def FNEGD : XForm_26<63, 40, (outs F8RC:$frD), (ins F8RC:$frB), 1032 "fneg $frD, $frB", FPGeneral, 1033 [(set F8RC:$frD, (fneg F8RC:$frB))]>; 1034} 1035 1036 1037// XL-Form instructions. condition register logical ops. 1038// 1039def MCRF : XLForm_3<19, 0, (outs CRRC:$BF), (ins CRRC:$BFA), 1040 "mcrf $BF, $BFA", BrMCR>, 1041 PPC970_DGroup_First, PPC970_Unit_CRU; 1042 1043def CREQV : XLForm_1<19, 289, (outs CRBITRC:$CRD), 1044 (ins CRBITRC:$CRA, CRBITRC:$CRB), 1045 "creqv $CRD, $CRA, $CRB", BrCR, 1046 []>; 1047 1048def CROR : XLForm_1<19, 449, (outs CRBITRC:$CRD), 1049 (ins CRBITRC:$CRA, CRBITRC:$CRB), 1050 "cror $CRD, $CRA, $CRB", BrCR, 1051 []>; 1052 1053def CRSET : XLForm_1_ext<19, 289, (outs CRBITRC:$dst), (ins), 1054 "creqv $dst, $dst, $dst", BrCR, 1055 []>; 1056 1057// XFX-Form instructions. Instructions that deal with SPRs. 1058// 1059let Uses = [CTR] in { 1060def MFCTR : XFXForm_1_ext<31, 339, 9, (outs GPRC:$rT), (ins), 1061 "mfctr $rT", SprMFSPR>, 1062 PPC970_DGroup_First, PPC970_Unit_FXU; 1063} 1064let Defs = [CTR], Pattern = [(PPCmtctr GPRC:$rS)] in { 1065def MTCTR : XFXForm_7_ext<31, 467, 9, (outs), (ins GPRC:$rS), 1066 "mtctr $rS", SprMTSPR>, 1067 PPC970_DGroup_First, PPC970_Unit_FXU; 1068} 1069 1070let Defs = [LR] in { 1071def MTLR : XFXForm_7_ext<31, 467, 8, (outs), (ins GPRC:$rS), 1072 "mtlr $rS", SprMTSPR>, 1073 PPC970_DGroup_First, PPC970_Unit_FXU; 1074} 1075let Uses = [LR] in { 1076def MFLR : XFXForm_1_ext<31, 339, 8, (outs GPRC:$rT), (ins), 1077 "mflr $rT", SprMFSPR>, 1078 PPC970_DGroup_First, PPC970_Unit_FXU; 1079} 1080 1081// Move to/from VRSAVE: despite being a SPR, the VRSAVE register is renamed like 1082// a GPR on the PPC970. As such, copies in and out have the same performance 1083// characteristics as an OR instruction. 1084def MTVRSAVE : XFXForm_7_ext<31, 467, 256, (outs), (ins GPRC:$rS), 1085 "mtspr 256, $rS", IntGeneral>, 1086 PPC970_DGroup_Single, PPC970_Unit_FXU; 1087def MFVRSAVE : XFXForm_1_ext<31, 339, 256, (outs GPRC:$rT), (ins), 1088 "mfspr $rT, 256", IntGeneral>, 1089 PPC970_DGroup_First, PPC970_Unit_FXU; 1090 1091def MTCRF : XFXForm_5<31, 144, (outs), (ins crbitm:$FXM, GPRC:$rS), 1092 "mtcrf $FXM, $rS", BrMCRX>, 1093 PPC970_MicroCode, PPC970_Unit_CRU; 1094 1095// This is a pseudo for MFCR, which implicitly uses all 8 of its subregisters; 1096// declaring that here gives the local register allocator problems with this: 1097// vreg = MCRF CR0 1098// MFCR <kill of whatever preg got assigned to vreg> 1099// while not declaring it breaks DeadMachineInstructionElimination. 1100// As it turns out, in all cases where we currently use this, 1101// we're only interested in one subregister of it. Represent this in the 1102// instruction to keep the register allocator from becoming confused. 1103// 1104// FIXME: Make this a real Pseudo instruction when the JIT switches to MC. 1105def MFCRpseud: XFXForm_3<31, 19, (outs GPRC:$rT), (ins crbitm:$FXM), 1106 "", SprMFCR>, 1107 PPC970_MicroCode, PPC970_Unit_CRU; 1108 1109def MFCR : XFXForm_3<31, 19, (outs GPRC:$rT), (ins), 1110 "mfcr $rT", SprMFCR>, 1111 PPC970_MicroCode, PPC970_Unit_CRU; 1112 1113def MFOCRF: XFXForm_5a<31, 19, (outs GPRC:$rT), (ins crbitm:$FXM), 1114 "mfcr $rT, $FXM", SprMFCR>, 1115 PPC970_DGroup_First, PPC970_Unit_CRU; 1116 1117// Instructions to manipulate FPSCR. Only long double handling uses these. 1118// FPSCR is not modelled; we use the SDNode Flag to keep things in order. 1119 1120let Uses = [RM], Defs = [RM] in { 1121 def MTFSB0 : XForm_43<63, 70, (outs), (ins u5imm:$FM), 1122 "mtfsb0 $FM", IntMTFSB0, 1123 [(PPCmtfsb0 (i32 imm:$FM))]>, 1124 PPC970_DGroup_Single, PPC970_Unit_FPU; 1125 def MTFSB1 : XForm_43<63, 38, (outs), (ins u5imm:$FM), 1126 "mtfsb1 $FM", IntMTFSB0, 1127 [(PPCmtfsb1 (i32 imm:$FM))]>, 1128 PPC970_DGroup_Single, PPC970_Unit_FPU; 1129 // MTFSF does not actually produce an FP result. We pretend it copies 1130 // input reg B to the output. If we didn't do this it would look like the 1131 // instruction had no outputs (because we aren't modelling the FPSCR) and 1132 // it would be deleted. 1133 def MTFSF : XFLForm<63, 711, (outs F8RC:$FRA), 1134 (ins i32imm:$FM, F8RC:$rT, F8RC:$FRB), 1135 "mtfsf $FM, $rT", "$FRB = $FRA", IntMTFSB0, 1136 [(set F8RC:$FRA, (PPCmtfsf (i32 imm:$FM), 1137 F8RC:$rT, F8RC:$FRB))]>, 1138 PPC970_DGroup_Single, PPC970_Unit_FPU; 1139} 1140let Uses = [RM] in { 1141 def MFFS : XForm_42<63, 583, (outs F8RC:$rT), (ins), 1142 "mffs $rT", IntMFFS, 1143 [(set F8RC:$rT, (PPCmffs))]>, 1144 PPC970_DGroup_Single, PPC970_Unit_FPU; 1145 def FADDrtz: AForm_2<63, 21, 1146 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB), 1147 "fadd $FRT, $FRA, $FRB", FPGeneral, 1148 [(set F8RC:$FRT, (PPCfaddrtz F8RC:$FRA, F8RC:$FRB))]>, 1149 PPC970_DGroup_Single, PPC970_Unit_FPU; 1150} 1151 1152 1153let PPC970_Unit = 1 in { // FXU Operations. 1154 1155// XO-Form instructions. Arithmetic instructions that can set overflow bit 1156// 1157def ADD4 : XOForm_1<31, 266, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB), 1158 "add $rT, $rA, $rB", IntGeneral, 1159 [(set GPRC:$rT, (add GPRC:$rA, GPRC:$rB))]>; 1160let Defs = [CARRY] in { 1161def ADDC : XOForm_1<31, 10, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB), 1162 "addc $rT, $rA, $rB", IntGeneral, 1163 [(set GPRC:$rT, (addc GPRC:$rA, GPRC:$rB))]>, 1164 PPC970_DGroup_Cracked; 1165} 1166def DIVW : XOForm_1<31, 491, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB), 1167 "divw $rT, $rA, $rB", IntDivW, 1168 [(set GPRC:$rT, (sdiv GPRC:$rA, GPRC:$rB))]>, 1169 PPC970_DGroup_First, PPC970_DGroup_Cracked; 1170def DIVWU : XOForm_1<31, 459, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB), 1171 "divwu $rT, $rA, $rB", IntDivW, 1172 [(set GPRC:$rT, (udiv GPRC:$rA, GPRC:$rB))]>, 1173 PPC970_DGroup_First, PPC970_DGroup_Cracked; 1174def MULHW : XOForm_1<31, 75, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB), 1175 "mulhw $rT, $rA, $rB", IntMulHW, 1176 [(set GPRC:$rT, (mulhs GPRC:$rA, GPRC:$rB))]>; 1177def MULHWU : XOForm_1<31, 11, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB), 1178 "mulhwu $rT, $rA, $rB", IntMulHWU, 1179 [(set GPRC:$rT, (mulhu GPRC:$rA, GPRC:$rB))]>; 1180def MULLW : XOForm_1<31, 235, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB), 1181 "mullw $rT, $rA, $rB", IntMulHW, 1182 [(set GPRC:$rT, (mul GPRC:$rA, GPRC:$rB))]>; 1183def SUBF : XOForm_1<31, 40, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB), 1184 "subf $rT, $rA, $rB", IntGeneral, 1185 [(set GPRC:$rT, (sub GPRC:$rB, GPRC:$rA))]>; 1186let Defs = [CARRY] in { 1187def SUBFC : XOForm_1<31, 8, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB), 1188 "subfc $rT, $rA, $rB", IntGeneral, 1189 [(set GPRC:$rT, (subc GPRC:$rB, GPRC:$rA))]>, 1190 PPC970_DGroup_Cracked; 1191} 1192def NEG : XOForm_3<31, 104, 0, (outs GPRC:$rT), (ins GPRC:$rA), 1193 "neg $rT, $rA", IntGeneral, 1194 [(set GPRC:$rT, (ineg GPRC:$rA))]>; 1195let Uses = [CARRY], Defs = [CARRY] in { 1196def ADDE : XOForm_1<31, 138, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB), 1197 "adde $rT, $rA, $rB", IntGeneral, 1198 [(set GPRC:$rT, (adde GPRC:$rA, GPRC:$rB))]>; 1199def ADDME : XOForm_3<31, 234, 0, (outs GPRC:$rT), (ins GPRC:$rA), 1200 "addme $rT, $rA", IntGeneral, 1201 [(set GPRC:$rT, (adde GPRC:$rA, -1))]>; 1202def ADDZE : XOForm_3<31, 202, 0, (outs GPRC:$rT), (ins GPRC:$rA), 1203 "addze $rT, $rA", IntGeneral, 1204 [(set GPRC:$rT, (adde GPRC:$rA, 0))]>; 1205def SUBFE : XOForm_1<31, 136, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB), 1206 "subfe $rT, $rA, $rB", IntGeneral, 1207 [(set GPRC:$rT, (sube GPRC:$rB, GPRC:$rA))]>; 1208def SUBFME : XOForm_3<31, 232, 0, (outs GPRC:$rT), (ins GPRC:$rA), 1209 "subfme $rT, $rA", IntGeneral, 1210 [(set GPRC:$rT, (sube -1, GPRC:$rA))]>; 1211def SUBFZE : XOForm_3<31, 200, 0, (outs GPRC:$rT), (ins GPRC:$rA), 1212 "subfze $rT, $rA", IntGeneral, 1213 [(set GPRC:$rT, (sube 0, GPRC:$rA))]>; 1214} 1215} 1216 1217// A-Form instructions. Most of the instructions executed in the FPU are of 1218// this type. 1219// 1220let PPC970_Unit = 3 in { // FPU Operations. 1221let Uses = [RM] in { 1222 def FMADD : AForm_1<63, 29, 1223 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB), 1224 "fmadd $FRT, $FRA, $FRC, $FRB", FPFused, 1225 [(set F8RC:$FRT, (fadd (fmul F8RC:$FRA, F8RC:$FRC), 1226 F8RC:$FRB))]>, 1227 Requires<[FPContractions]>; 1228 def FMADDS : AForm_1<59, 29, 1229 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB), 1230 "fmadds $FRT, $FRA, $FRC, $FRB", FPGeneral, 1231 [(set F4RC:$FRT, (fadd (fmul F4RC:$FRA, F4RC:$FRC), 1232 F4RC:$FRB))]>, 1233 Requires<[FPContractions]>; 1234 def FMSUB : AForm_1<63, 28, 1235 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB), 1236 "fmsub $FRT, $FRA, $FRC, $FRB", FPFused, 1237 [(set F8RC:$FRT, (fsub (fmul F8RC:$FRA, F8RC:$FRC), 1238 F8RC:$FRB))]>, 1239 Requires<[FPContractions]>; 1240 def FMSUBS : AForm_1<59, 28, 1241 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB), 1242 "fmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral, 1243 [(set F4RC:$FRT, (fsub (fmul F4RC:$FRA, F4RC:$FRC), 1244 F4RC:$FRB))]>, 1245 Requires<[FPContractions]>; 1246 def FNMADD : AForm_1<63, 31, 1247 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB), 1248 "fnmadd $FRT, $FRA, $FRC, $FRB", FPFused, 1249 [(set F8RC:$FRT, (fneg (fadd (fmul F8RC:$FRA, F8RC:$FRC), 1250 F8RC:$FRB)))]>, 1251 Requires<[FPContractions]>; 1252 def FNMADDS : AForm_1<59, 31, 1253 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB), 1254 "fnmadds $FRT, $FRA, $FRC, $FRB", FPGeneral, 1255 [(set F4RC:$FRT, (fneg (fadd (fmul F4RC:$FRA, F4RC:$FRC), 1256 F4RC:$FRB)))]>, 1257 Requires<[FPContractions]>; 1258 def FNMSUB : AForm_1<63, 30, 1259 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB), 1260 "fnmsub $FRT, $FRA, $FRC, $FRB", FPFused, 1261 [(set F8RC:$FRT, (fneg (fsub (fmul F8RC:$FRA, F8RC:$FRC), 1262 F8RC:$FRB)))]>, 1263 Requires<[FPContractions]>; 1264 def FNMSUBS : AForm_1<59, 30, 1265 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB), 1266 "fnmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral, 1267 [(set F4RC:$FRT, (fneg (fsub (fmul F4RC:$FRA, F4RC:$FRC), 1268 F4RC:$FRB)))]>, 1269 Requires<[FPContractions]>; 1270} 1271// FSEL is artificially split into 4 and 8-byte forms for the result. To avoid 1272// having 4 of these, force the comparison to always be an 8-byte double (code 1273// should use an FMRSD if the input comparison value really wants to be a float) 1274// and 4/8 byte forms for the result and operand type.. 1275def FSELD : AForm_1<63, 23, 1276 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB), 1277 "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral, 1278 [(set F8RC:$FRT, (PPCfsel F8RC:$FRA,F8RC:$FRC,F8RC:$FRB))]>; 1279def FSELS : AForm_1<63, 23, 1280 (outs F4RC:$FRT), (ins F8RC:$FRA, F4RC:$FRC, F4RC:$FRB), 1281 "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral, 1282 [(set F4RC:$FRT, (PPCfsel F8RC:$FRA,F4RC:$FRC,F4RC:$FRB))]>; 1283let Uses = [RM] in { 1284 def FADD : AForm_2<63, 21, 1285 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB), 1286 "fadd $FRT, $FRA, $FRB", FPGeneral, 1287 [(set F8RC:$FRT, (fadd F8RC:$FRA, F8RC:$FRB))]>; 1288 def FADDS : AForm_2<59, 21, 1289 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB), 1290 "fadds $FRT, $FRA, $FRB", FPGeneral, 1291 [(set F4RC:$FRT, (fadd F4RC:$FRA, F4RC:$FRB))]>; 1292 def FDIV : AForm_2<63, 18, 1293 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB), 1294 "fdiv $FRT, $FRA, $FRB", FPDivD, 1295 [(set F8RC:$FRT, (fdiv F8RC:$FRA, F8RC:$FRB))]>; 1296 def FDIVS : AForm_2<59, 18, 1297 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB), 1298 "fdivs $FRT, $FRA, $FRB", FPDivS, 1299 [(set F4RC:$FRT, (fdiv F4RC:$FRA, F4RC:$FRB))]>; 1300 def FMUL : AForm_3<63, 25, 1301 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB), 1302 "fmul $FRT, $FRA, $FRB", FPFused, 1303 [(set F8RC:$FRT, (fmul F8RC:$FRA, F8RC:$FRB))]>; 1304 def FMULS : AForm_3<59, 25, 1305 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB), 1306 "fmuls $FRT, $FRA, $FRB", FPGeneral, 1307 [(set F4RC:$FRT, (fmul F4RC:$FRA, F4RC:$FRB))]>; 1308 def FSUB : AForm_2<63, 20, 1309 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB), 1310 "fsub $FRT, $FRA, $FRB", FPGeneral, 1311 [(set F8RC:$FRT, (fsub F8RC:$FRA, F8RC:$FRB))]>; 1312 def FSUBS : AForm_2<59, 20, 1313 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB), 1314 "fsubs $FRT, $FRA, $FRB", FPGeneral, 1315 [(set F4RC:$FRT, (fsub F4RC:$FRA, F4RC:$FRB))]>; 1316 } 1317} 1318 1319let PPC970_Unit = 1 in { // FXU Operations. 1320// M-Form instructions. rotate and mask instructions. 1321// 1322let isCommutable = 1 in { 1323// RLWIMI can be commuted if the rotate amount is zero. 1324def RLWIMI : MForm_2<20, 1325 (outs GPRC:$rA), (ins GPRC:$rSi, GPRC:$rS, u5imm:$SH, u5imm:$MB, 1326 u5imm:$ME), "rlwimi $rA, $rS, $SH, $MB, $ME", IntRotate, 1327 []>, PPC970_DGroup_Cracked, RegConstraint<"$rSi = $rA">, 1328 NoEncode<"$rSi">; 1329} 1330def RLWINM : MForm_2<21, 1331 (outs GPRC:$rA), (ins GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME), 1332 "rlwinm $rA, $rS, $SH, $MB, $ME", IntGeneral, 1333 []>; 1334def RLWINMo : MForm_2<21, 1335 (outs GPRC:$rA), (ins GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME), 1336 "rlwinm. $rA, $rS, $SH, $MB, $ME", IntGeneral, 1337 []>, isDOT, PPC970_DGroup_Cracked; 1338def RLWNM : MForm_2<23, 1339 (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB, u5imm:$MB, u5imm:$ME), 1340 "rlwnm $rA, $rS, $rB, $MB, $ME", IntGeneral, 1341 []>; 1342} 1343 1344 1345//===----------------------------------------------------------------------===// 1346// PowerPC Instruction Patterns 1347// 1348 1349// Arbitrary immediate support. Implement in terms of LIS/ORI. 1350def : Pat<(i32 imm:$imm), 1351 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>; 1352 1353// Implement the 'not' operation with the NOR instruction. 1354def NOT : Pat<(not GPRC:$in), 1355 (NOR GPRC:$in, GPRC:$in)>; 1356 1357// ADD an arbitrary immediate. 1358def : Pat<(add GPRC:$in, imm:$imm), 1359 (ADDIS (ADDI GPRC:$in, (LO16 imm:$imm)), (HA16 imm:$imm))>; 1360// OR an arbitrary immediate. 1361def : Pat<(or GPRC:$in, imm:$imm), 1362 (ORIS (ORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>; 1363// XOR an arbitrary immediate. 1364def : Pat<(xor GPRC:$in, imm:$imm), 1365 (XORIS (XORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>; 1366// SUBFIC 1367def : Pat<(sub immSExt16:$imm, GPRC:$in), 1368 (SUBFIC GPRC:$in, imm:$imm)>; 1369 1370// SHL/SRL 1371def : Pat<(shl GPRC:$in, (i32 imm:$imm)), 1372 (RLWINM GPRC:$in, imm:$imm, 0, (SHL32 imm:$imm))>; 1373def : Pat<(srl GPRC:$in, (i32 imm:$imm)), 1374 (RLWINM GPRC:$in, (SRL32 imm:$imm), imm:$imm, 31)>; 1375 1376// ROTL 1377def : Pat<(rotl GPRC:$in, GPRC:$sh), 1378 (RLWNM GPRC:$in, GPRC:$sh, 0, 31)>; 1379def : Pat<(rotl GPRC:$in, (i32 imm:$imm)), 1380 (RLWINM GPRC:$in, imm:$imm, 0, 31)>; 1381 1382// RLWNM 1383def : Pat<(and (rotl GPRC:$in, GPRC:$sh), maskimm32:$imm), 1384 (RLWNM GPRC:$in, GPRC:$sh, (MB maskimm32:$imm), (ME maskimm32:$imm))>; 1385 1386// Calls 1387def : Pat<(PPCcall_Darwin (i32 tglobaladdr:$dst)), 1388 (BL_Darwin tglobaladdr:$dst)>; 1389def : Pat<(PPCcall_Darwin (i32 texternalsym:$dst)), 1390 (BL_Darwin texternalsym:$dst)>; 1391def : Pat<(PPCcall_SVR4 (i32 tglobaladdr:$dst)), 1392 (BL_SVR4 tglobaladdr:$dst)>; 1393def : Pat<(PPCcall_SVR4 (i32 texternalsym:$dst)), 1394 (BL_SVR4 texternalsym:$dst)>; 1395 1396 1397def : Pat<(PPCtc_return (i32 tglobaladdr:$dst), imm:$imm), 1398 (TCRETURNdi tglobaladdr:$dst, imm:$imm)>; 1399 1400def : Pat<(PPCtc_return (i32 texternalsym:$dst), imm:$imm), 1401 (TCRETURNdi texternalsym:$dst, imm:$imm)>; 1402 1403def : Pat<(PPCtc_return CTRRC:$dst, imm:$imm), 1404 (TCRETURNri CTRRC:$dst, imm:$imm)>; 1405 1406 1407 1408// Hi and Lo for Darwin Global Addresses. 1409def : Pat<(PPChi tglobaladdr:$in, 0), (LIS tglobaladdr:$in)>; 1410def : Pat<(PPClo tglobaladdr:$in, 0), (LI tglobaladdr:$in)>; 1411def : Pat<(PPChi tconstpool:$in, 0), (LIS tconstpool:$in)>; 1412def : Pat<(PPClo tconstpool:$in, 0), (LI tconstpool:$in)>; 1413def : Pat<(PPChi tjumptable:$in, 0), (LIS tjumptable:$in)>; 1414def : Pat<(PPClo tjumptable:$in, 0), (LI tjumptable:$in)>; 1415def : Pat<(PPChi tblockaddress:$in, 0), (LIS tblockaddress:$in)>; 1416def : Pat<(PPClo tblockaddress:$in, 0), (LI tblockaddress:$in)>; 1417def : Pat<(add GPRC:$in, (PPChi tglobaladdr:$g, 0)), 1418 (ADDIS GPRC:$in, tglobaladdr:$g)>; 1419def : Pat<(add GPRC:$in, (PPChi tconstpool:$g, 0)), 1420 (ADDIS GPRC:$in, tconstpool:$g)>; 1421def : Pat<(add GPRC:$in, (PPChi tjumptable:$g, 0)), 1422 (ADDIS GPRC:$in, tjumptable:$g)>; 1423def : Pat<(add GPRC:$in, (PPChi tblockaddress:$g, 0)), 1424 (ADDIS GPRC:$in, tblockaddress:$g)>; 1425 1426// Fused negative multiply subtract, alternate pattern 1427def : Pat<(fsub F8RC:$B, (fmul F8RC:$A, F8RC:$C)), 1428 (FNMSUB F8RC:$A, F8RC:$C, F8RC:$B)>, 1429 Requires<[FPContractions]>; 1430def : Pat<(fsub F4RC:$B, (fmul F4RC:$A, F4RC:$C)), 1431 (FNMSUBS F4RC:$A, F4RC:$C, F4RC:$B)>, 1432 Requires<[FPContractions]>; 1433 1434// Standard shifts. These are represented separately from the real shifts above 1435// so that we can distinguish between shifts that allow 5-bit and 6-bit shift 1436// amounts. 1437def : Pat<(sra GPRC:$rS, GPRC:$rB), 1438 (SRAW GPRC:$rS, GPRC:$rB)>; 1439def : Pat<(srl GPRC:$rS, GPRC:$rB), 1440 (SRW GPRC:$rS, GPRC:$rB)>; 1441def : Pat<(shl GPRC:$rS, GPRC:$rB), 1442 (SLW GPRC:$rS, GPRC:$rB)>; 1443 1444def : Pat<(zextloadi1 iaddr:$src), 1445 (LBZ iaddr:$src)>; 1446def : Pat<(zextloadi1 xaddr:$src), 1447 (LBZX xaddr:$src)>; 1448def : Pat<(extloadi1 iaddr:$src), 1449 (LBZ iaddr:$src)>; 1450def : Pat<(extloadi1 xaddr:$src), 1451 (LBZX xaddr:$src)>; 1452def : Pat<(extloadi8 iaddr:$src), 1453 (LBZ iaddr:$src)>; 1454def : Pat<(extloadi8 xaddr:$src), 1455 (LBZX xaddr:$src)>; 1456def : Pat<(extloadi16 iaddr:$src), 1457 (LHZ iaddr:$src)>; 1458def : Pat<(extloadi16 xaddr:$src), 1459 (LHZX xaddr:$src)>; 1460def : Pat<(f64 (extloadf32 iaddr:$src)), 1461 (COPY_TO_REGCLASS (LFS iaddr:$src), F8RC)>; 1462def : Pat<(f64 (extloadf32 xaddr:$src)), 1463 (COPY_TO_REGCLASS (LFSX xaddr:$src), F8RC)>; 1464 1465def : Pat<(f64 (fextend F4RC:$src)), 1466 (COPY_TO_REGCLASS F4RC:$src, F8RC)>; 1467 1468// Memory barriers 1469def : Pat<(membarrier (i32 imm /*ll*/), 1470 (i32 imm /*ls*/), 1471 (i32 imm /*sl*/), 1472 (i32 imm /*ss*/), 1473 (i32 imm /*device*/)), 1474 (SYNC)>; 1475 1476include "PPCInstrAltivec.td" 1477include "PPCInstr64Bit.td" 1478