PPCInstrInfo.td revision 198953
1//===- PPCInstrInfo.td - The PowerPC Instruction Set -------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the subset of the 32-bit PowerPC instruction set, as used 11// by the PowerPC instruction selector. 12// 13//===----------------------------------------------------------------------===// 14 15include "PPCInstrFormats.td" 16 17//===----------------------------------------------------------------------===// 18// PowerPC specific type constraints. 19// 20def SDT_PPCstfiwx : SDTypeProfile<0, 2, [ // stfiwx 21 SDTCisVT<0, f64>, SDTCisPtrTy<1> 22]>; 23def SDT_PPCCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>; 24def SDT_PPCCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, 25 SDTCisVT<1, i32> ]>; 26def SDT_PPCvperm : SDTypeProfile<1, 3, [ 27 SDTCisVT<3, v16i8>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2> 28]>; 29 30def SDT_PPCvcmp : SDTypeProfile<1, 3, [ 31 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32> 32]>; 33 34def SDT_PPCcondbr : SDTypeProfile<0, 3, [ 35 SDTCisVT<0, i32>, SDTCisVT<2, OtherVT> 36]>; 37 38def SDT_PPClbrx : SDTypeProfile<1, 2, [ 39 SDTCisVT<0, i32>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT> 40]>; 41def SDT_PPCstbrx : SDTypeProfile<0, 3, [ 42 SDTCisVT<0, i32>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT> 43]>; 44 45def SDT_PPClarx : SDTypeProfile<1, 1, [ 46 SDTCisInt<0>, SDTCisPtrTy<1> 47]>; 48def SDT_PPCstcx : SDTypeProfile<0, 2, [ 49 SDTCisInt<0>, SDTCisPtrTy<1> 50]>; 51 52def SDT_PPCTC_ret : SDTypeProfile<0, 2, [ 53 SDTCisPtrTy<0>, SDTCisVT<1, i32> 54]>; 55 56def SDT_PPCnop : SDTypeProfile<0, 0, []>; 57 58//===----------------------------------------------------------------------===// 59// PowerPC specific DAG Nodes. 60// 61 62def PPCfcfid : SDNode<"PPCISD::FCFID" , SDTFPUnaryOp, []>; 63def PPCfctidz : SDNode<"PPCISD::FCTIDZ", SDTFPUnaryOp, []>; 64def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>; 65def PPCstfiwx : SDNode<"PPCISD::STFIWX", SDT_PPCstfiwx, 66 [SDNPHasChain, SDNPMayStore]>; 67 68// This sequence is used for long double->int conversions. It changes the 69// bits in the FPSCR which is not modelled. 70def PPCmffs : SDNode<"PPCISD::MFFS", SDTypeProfile<1, 0, [SDTCisVT<0, f64>]>, 71 [SDNPOutFlag]>; 72def PPCmtfsb0 : SDNode<"PPCISD::MTFSB0", SDTypeProfile<0, 1, [SDTCisInt<0>]>, 73 [SDNPInFlag, SDNPOutFlag]>; 74def PPCmtfsb1 : SDNode<"PPCISD::MTFSB1", SDTypeProfile<0, 1, [SDTCisInt<0>]>, 75 [SDNPInFlag, SDNPOutFlag]>; 76def PPCfaddrtz: SDNode<"PPCISD::FADDRTZ", SDTFPBinOp, 77 [SDNPInFlag, SDNPOutFlag]>; 78def PPCmtfsf : SDNode<"PPCISD::MTFSF", SDTypeProfile<1, 3, 79 [SDTCisVT<0, f64>, SDTCisInt<1>, SDTCisVT<2, f64>, 80 SDTCisVT<3, f64>]>, 81 [SDNPInFlag]>; 82 83def PPCfsel : SDNode<"PPCISD::FSEL", 84 // Type constraint for fsel. 85 SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, 86 SDTCisFP<0>, SDTCisVT<1, f64>]>, []>; 87 88def PPChi : SDNode<"PPCISD::Hi", SDTIntBinOp, []>; 89def PPClo : SDNode<"PPCISD::Lo", SDTIntBinOp, []>; 90def PPCtoc_entry: SDNode<"PPCISD::TOC_ENTRY", SDTIntBinOp, [SDNPMayLoad]>; 91def PPCvmaddfp : SDNode<"PPCISD::VMADDFP", SDTFPTernaryOp, []>; 92def PPCvnmsubfp : SDNode<"PPCISD::VNMSUBFP", SDTFPTernaryOp, []>; 93 94def PPCvperm : SDNode<"PPCISD::VPERM", SDT_PPCvperm, []>; 95 96// These nodes represent the 32-bit PPC shifts that operate on 6-bit shift 97// amounts. These nodes are generated by the multi-precision shift code. 98def PPCsrl : SDNode<"PPCISD::SRL" , SDTIntShiftOp>; 99def PPCsra : SDNode<"PPCISD::SRA" , SDTIntShiftOp>; 100def PPCshl : SDNode<"PPCISD::SHL" , SDTIntShiftOp>; 101 102def PPCextsw_32 : SDNode<"PPCISD::EXTSW_32" , SDTIntUnaryOp>; 103def PPCstd_32 : SDNode<"PPCISD::STD_32" , SDTStore, 104 [SDNPHasChain, SDNPMayStore]>; 105 106// These are target-independent nodes, but have target-specific formats. 107def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeqStart, 108 [SDNPHasChain, SDNPOutFlag]>; 109def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_PPCCallSeqEnd, 110 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>; 111 112def SDT_PPCCall : SDTypeProfile<0, -1, [SDTCisInt<0>]>; 113def PPCcall_Darwin : SDNode<"PPCISD::CALL_Darwin", SDT_PPCCall, 114 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>; 115def PPCcall_SVR4 : SDNode<"PPCISD::CALL_SVR4", SDT_PPCCall, 116 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>; 117def PPCnop : SDNode<"PPCISD::NOP", SDT_PPCnop, [SDNPInFlag, SDNPOutFlag]>; 118def PPCmtctr : SDNode<"PPCISD::MTCTR", SDT_PPCCall, 119 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>; 120def PPCbctrl_Darwin : SDNode<"PPCISD::BCTRL_Darwin", SDTNone, 121 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>; 122 123def PPCbctrl_SVR4 : SDNode<"PPCISD::BCTRL_SVR4", SDTNone, 124 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>; 125 126def retflag : SDNode<"PPCISD::RET_FLAG", SDTNone, 127 [SDNPHasChain, SDNPOptInFlag]>; 128 129def PPCtc_return : SDNode<"PPCISD::TC_RETURN", SDT_PPCTC_ret, 130 [SDNPHasChain, SDNPOptInFlag]>; 131 132def PPCvcmp : SDNode<"PPCISD::VCMP" , SDT_PPCvcmp, []>; 133def PPCvcmp_o : SDNode<"PPCISD::VCMPo", SDT_PPCvcmp, [SDNPOutFlag]>; 134 135def PPCcondbranch : SDNode<"PPCISD::COND_BRANCH", SDT_PPCcondbr, 136 [SDNPHasChain, SDNPOptInFlag]>; 137 138def PPClbrx : SDNode<"PPCISD::LBRX", SDT_PPClbrx, 139 [SDNPHasChain, SDNPMayLoad]>; 140def PPCstbrx : SDNode<"PPCISD::STBRX", SDT_PPCstbrx, 141 [SDNPHasChain, SDNPMayStore]>; 142 143// Instructions to support atomic operations 144def PPClarx : SDNode<"PPCISD::LARX", SDT_PPClarx, 145 [SDNPHasChain, SDNPMayLoad]>; 146def PPCstcx : SDNode<"PPCISD::STCX", SDT_PPCstcx, 147 [SDNPHasChain, SDNPMayStore]>; 148 149// Instructions to support dynamic alloca. 150def SDTDynOp : SDTypeProfile<1, 2, []>; 151def PPCdynalloc : SDNode<"PPCISD::DYNALLOC", SDTDynOp, [SDNPHasChain]>; 152 153//===----------------------------------------------------------------------===// 154// PowerPC specific transformation functions and pattern fragments. 155// 156 157def SHL32 : SDNodeXForm<imm, [{ 158 // Transformation function: 31 - imm 159 return getI32Imm(31 - N->getZExtValue()); 160}]>; 161 162def SRL32 : SDNodeXForm<imm, [{ 163 // Transformation function: 32 - imm 164 return N->getZExtValue() ? getI32Imm(32 - N->getZExtValue()) : getI32Imm(0); 165}]>; 166 167def LO16 : SDNodeXForm<imm, [{ 168 // Transformation function: get the low 16 bits. 169 return getI32Imm((unsigned short)N->getZExtValue()); 170}]>; 171 172def HI16 : SDNodeXForm<imm, [{ 173 // Transformation function: shift the immediate value down into the low bits. 174 return getI32Imm((unsigned)N->getZExtValue() >> 16); 175}]>; 176 177def HA16 : SDNodeXForm<imm, [{ 178 // Transformation function: shift the immediate value down into the low bits. 179 signed int Val = N->getZExtValue(); 180 return getI32Imm((Val - (signed short)Val) >> 16); 181}]>; 182def MB : SDNodeXForm<imm, [{ 183 // Transformation function: get the start bit of a mask 184 unsigned mb = 0, me; 185 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me); 186 return getI32Imm(mb); 187}]>; 188 189def ME : SDNodeXForm<imm, [{ 190 // Transformation function: get the end bit of a mask 191 unsigned mb, me = 0; 192 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me); 193 return getI32Imm(me); 194}]>; 195def maskimm32 : PatLeaf<(imm), [{ 196 // maskImm predicate - True if immediate is a run of ones. 197 unsigned mb, me; 198 if (N->getValueType(0) == MVT::i32) 199 return isRunOfOnes((unsigned)N->getZExtValue(), mb, me); 200 else 201 return false; 202}]>; 203 204def immSExt16 : PatLeaf<(imm), [{ 205 // immSExt16 predicate - True if the immediate fits in a 16-bit sign extended 206 // field. Used by instructions like 'addi'. 207 if (N->getValueType(0) == MVT::i32) 208 return (int32_t)N->getZExtValue() == (short)N->getZExtValue(); 209 else 210 return (int64_t)N->getZExtValue() == (short)N->getZExtValue(); 211}]>; 212def immZExt16 : PatLeaf<(imm), [{ 213 // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended 214 // field. Used by instructions like 'ori'. 215 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue(); 216}], LO16>; 217 218// imm16Shifted* - These match immediates where the low 16-bits are zero. There 219// are two forms: imm16ShiftedSExt and imm16ShiftedZExt. These two forms are 220// identical in 32-bit mode, but in 64-bit mode, they return true if the 221// immediate fits into a sign/zero extended 32-bit immediate (with the low bits 222// clear). 223def imm16ShiftedZExt : PatLeaf<(imm), [{ 224 // imm16ShiftedZExt predicate - True if only bits in the top 16-bits of the 225 // immediate are set. Used by instructions like 'xoris'. 226 return (N->getZExtValue() & ~uint64_t(0xFFFF0000)) == 0; 227}], HI16>; 228 229def imm16ShiftedSExt : PatLeaf<(imm), [{ 230 // imm16ShiftedSExt predicate - True if only bits in the top 16-bits of the 231 // immediate are set. Used by instructions like 'addis'. Identical to 232 // imm16ShiftedZExt in 32-bit mode. 233 if (N->getZExtValue() & 0xFFFF) return false; 234 if (N->getValueType(0) == MVT::i32) 235 return true; 236 // For 64-bit, make sure it is sext right. 237 return N->getZExtValue() == (uint64_t)(int)N->getZExtValue(); 238}], HI16>; 239 240 241//===----------------------------------------------------------------------===// 242// PowerPC Flag Definitions. 243 244class isPPC64 { bit PPC64 = 1; } 245class isDOT { 246 list<Register> Defs = [CR0]; 247 bit RC = 1; 248} 249 250class RegConstraint<string C> { 251 string Constraints = C; 252} 253class NoEncode<string E> { 254 string DisableEncoding = E; 255} 256 257 258//===----------------------------------------------------------------------===// 259// PowerPC Operand Definitions. 260 261def s5imm : Operand<i32> { 262 let PrintMethod = "printS5ImmOperand"; 263} 264def u5imm : Operand<i32> { 265 let PrintMethod = "printU5ImmOperand"; 266} 267def u6imm : Operand<i32> { 268 let PrintMethod = "printU6ImmOperand"; 269} 270def s16imm : Operand<i32> { 271 let PrintMethod = "printS16ImmOperand"; 272} 273def u16imm : Operand<i32> { 274 let PrintMethod = "printU16ImmOperand"; 275} 276def s16immX4 : Operand<i32> { // Multiply imm by 4 before printing. 277 let PrintMethod = "printS16X4ImmOperand"; 278} 279def target : Operand<OtherVT> { 280 let PrintMethod = "printBranchOperand"; 281} 282def calltarget : Operand<iPTR> { 283 let PrintMethod = "printCallOperand"; 284} 285def aaddr : Operand<iPTR> { 286 let PrintMethod = "printAbsAddrOperand"; 287} 288def piclabel: Operand<iPTR> { 289 let PrintMethod = "printPICLabel"; 290} 291def symbolHi: Operand<i32> { 292 let PrintMethod = "printSymbolHi"; 293} 294def symbolLo: Operand<i32> { 295 let PrintMethod = "printSymbolLo"; 296} 297def crbitm: Operand<i8> { 298 let PrintMethod = "printcrbitm"; 299} 300// Address operands 301def memri : Operand<iPTR> { 302 let PrintMethod = "printMemRegImm"; 303 let MIOperandInfo = (ops i32imm:$imm, ptr_rc:$reg); 304} 305def memrr : Operand<iPTR> { 306 let PrintMethod = "printMemRegReg"; 307 let MIOperandInfo = (ops ptr_rc, ptr_rc); 308} 309def memrix : Operand<iPTR> { // memri where the imm is shifted 2 bits. 310 let PrintMethod = "printMemRegImmShifted"; 311 let MIOperandInfo = (ops i32imm:$imm, ptr_rc:$reg); 312} 313def tocentry : Operand<iPTR> { 314 let PrintMethod = "printTOCEntryLabel"; 315 let MIOperandInfo = (ops i32imm:$imm); 316} 317 318// PowerPC Predicate operand. 20 = (0<<5)|20 = always, CR0 is a dummy reg 319// that doesn't matter. 320def pred : PredicateOperand<OtherVT, (ops imm, CRRC), 321 (ops (i32 20), (i32 zero_reg))> { 322 let PrintMethod = "printPredicateOperand"; 323} 324 325// Define PowerPC specific addressing mode. 326def iaddr : ComplexPattern<iPTR, 2, "SelectAddrImm", [], []>; 327def xaddr : ComplexPattern<iPTR, 2, "SelectAddrIdx", [], []>; 328def xoaddr : ComplexPattern<iPTR, 2, "SelectAddrIdxOnly",[], []>; 329def ixaddr : ComplexPattern<iPTR, 2, "SelectAddrImmShift", [], []>; // "std" 330 331/// This is just the offset part of iaddr, used for preinc. 332def iaddroff : ComplexPattern<iPTR, 1, "SelectAddrImmOffs", [], []>; 333 334//===----------------------------------------------------------------------===// 335// PowerPC Instruction Predicate Definitions. 336def FPContractions : Predicate<"!NoExcessFPPrecision">; 337def In32BitMode : Predicate<"!PPCSubTarget.isPPC64()">; 338def In64BitMode : Predicate<"PPCSubTarget.isPPC64()">; 339 340 341//===----------------------------------------------------------------------===// 342// PowerPC Instruction Definitions. 343 344// Pseudo-instructions: 345 346let hasCtrlDep = 1 in { 347let Defs = [R1], Uses = [R1] in { 348def ADJCALLSTACKDOWN : Pseudo<(outs), (ins u16imm:$amt), 349 "${:comment} ADJCALLSTACKDOWN", 350 [(callseq_start timm:$amt)]>; 351def ADJCALLSTACKUP : Pseudo<(outs), (ins u16imm:$amt1, u16imm:$amt2), 352 "${:comment} ADJCALLSTACKUP", 353 [(callseq_end timm:$amt1, timm:$amt2)]>; 354} 355 356def UPDATE_VRSAVE : Pseudo<(outs GPRC:$rD), (ins GPRC:$rS), 357 "UPDATE_VRSAVE $rD, $rS", []>; 358} 359 360let Defs = [R1], Uses = [R1] in 361def DYNALLOC : Pseudo<(outs GPRC:$result), (ins GPRC:$negsize, memri:$fpsi), 362 "${:comment} DYNALLOC $result, $negsize, $fpsi", 363 [(set GPRC:$result, 364 (PPCdynalloc GPRC:$negsize, iaddr:$fpsi))]>; 365 366// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after 367// instruction selection into a branch sequence. 368let usesCustomInserter = 1, // Expanded after instruction selection. 369 PPC970_Single = 1 in { 370 def SELECT_CC_I4 : Pseudo<(outs GPRC:$dst), (ins CRRC:$cond, GPRC:$T, GPRC:$F, 371 i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!", 372 []>; 373 def SELECT_CC_I8 : Pseudo<(outs G8RC:$dst), (ins CRRC:$cond, G8RC:$T, G8RC:$F, 374 i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!", 375 []>; 376 def SELECT_CC_F4 : Pseudo<(outs F4RC:$dst), (ins CRRC:$cond, F4RC:$T, F4RC:$F, 377 i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!", 378 []>; 379 def SELECT_CC_F8 : Pseudo<(outs F8RC:$dst), (ins CRRC:$cond, F8RC:$T, F8RC:$F, 380 i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!", 381 []>; 382 def SELECT_CC_VRRC: Pseudo<(outs VRRC:$dst), (ins CRRC:$cond, VRRC:$T, VRRC:$F, 383 i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!", 384 []>; 385} 386 387// SPILL_CR - Indicate that we're dumping the CR register, so we'll need to 388// scavenge a register for it. 389def SPILL_CR : Pseudo<(outs), (ins GPRC:$cond, memri:$F), 390 "${:comment} SPILL_CR $cond $F", []>; 391 392let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in { 393 let isReturn = 1, Uses = [LR, RM] in 394 def BLR : XLForm_2_br<19, 16, 0, (outs), (ins pred:$p), 395 "b${p:cc}lr ${p:reg}", BrB, 396 [(retflag)]>; 397 let isBranch = 1, isIndirectBranch = 1, Uses = [CTR] in 398 def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>; 399} 400 401let Defs = [LR] in 402 def MovePCtoLR : Pseudo<(outs), (ins piclabel:$label), "bl $label", []>, 403 PPC970_Unit_BRU; 404 405let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in { 406 let isBarrier = 1 in { 407 def B : IForm<18, 0, 0, (outs), (ins target:$dst), 408 "b $dst", BrB, 409 [(br bb:$dst)]>; 410 } 411 412 // BCC represents an arbitrary conditional branch on a predicate. 413 // FIXME: should be able to write a pattern for PPCcondbranch, but can't use 414 // a two-value operand where a dag node expects two operands. :( 415 def BCC : BForm<16, 0, 0, (outs), (ins pred:$cond, target:$dst), 416 "b${cond:cc} ${cond:reg}, $dst" 417 /*[(PPCcondbranch CRRC:$crS, imm:$opc, bb:$dst)]*/>; 418} 419 420// Darwin ABI Calls. 421let isCall = 1, PPC970_Unit = 7, 422 // All calls clobber the non-callee saved registers... 423 Defs = [R0,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12, 424 F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13, 425 V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16,V17,V18,V19, 426 LR,CTR, 427 CR0,CR1,CR5,CR6,CR7, 428 CR0LT,CR0GT,CR0EQ,CR0UN,CR1LT,CR1GT,CR1EQ,CR1UN,CR5LT,CR5GT,CR5EQ, 429 CR5UN,CR6LT,CR6GT,CR6EQ,CR6UN,CR7LT,CR7GT,CR7EQ,CR7UN,CARRY] in { 430 // Convenient aliases for call instructions 431 let Uses = [RM] in { 432 def BL_Darwin : IForm<18, 0, 1, 433 (outs), (ins calltarget:$func, variable_ops), 434 "bl $func", BrB, []>; // See Pat patterns below. 435 def BLA_Darwin : IForm<18, 1, 1, 436 (outs), (ins aaddr:$func, variable_ops), 437 "bla $func", BrB, [(PPCcall_Darwin (i32 imm:$func))]>; 438 } 439 let Uses = [CTR, RM] in { 440 def BCTRL_Darwin : XLForm_2_ext<19, 528, 20, 0, 1, 441 (outs), (ins variable_ops), 442 "bctrl", BrB, 443 [(PPCbctrl_Darwin)]>, Requires<[In32BitMode]>; 444 } 445} 446 447// SVR4 ABI Calls. 448let isCall = 1, PPC970_Unit = 7, 449 // All calls clobber the non-callee saved registers... 450 Defs = [R0,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12, 451 F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13, 452 V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16,V17,V18,V19, 453 LR,CTR, 454 CR0,CR1,CR5,CR6,CR7, 455 CR0LT,CR0GT,CR0EQ,CR0UN,CR1LT,CR1GT,CR1EQ,CR1UN,CR5LT,CR5GT,CR5EQ, 456 CR5UN,CR6LT,CR6GT,CR6EQ,CR6UN,CR7LT,CR7GT,CR7EQ,CR7UN,CARRY] in { 457 // Convenient aliases for call instructions 458 let Uses = [RM] in { 459 def BL_SVR4 : IForm<18, 0, 1, 460 (outs), (ins calltarget:$func, variable_ops), 461 "bl $func", BrB, []>; // See Pat patterns below. 462 def BLA_SVR4 : IForm<18, 1, 1, 463 (outs), (ins aaddr:$func, variable_ops), 464 "bla $func", BrB, 465 [(PPCcall_SVR4 (i32 imm:$func))]>; 466 } 467 let Uses = [CTR, RM] in { 468 def BCTRL_SVR4 : XLForm_2_ext<19, 528, 20, 0, 1, 469 (outs), (ins variable_ops), 470 "bctrl", BrB, 471 [(PPCbctrl_SVR4)]>, Requires<[In32BitMode]>; 472 } 473} 474 475 476let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 477def TCRETURNdi :Pseudo< (outs), 478 (ins calltarget:$dst, i32imm:$offset, variable_ops), 479 "#TC_RETURNd $dst $offset", 480 []>; 481 482 483let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 484def TCRETURNai :Pseudo<(outs), (ins aaddr:$func, i32imm:$offset, variable_ops), 485 "#TC_RETURNa $func $offset", 486 [(PPCtc_return (i32 imm:$func), imm:$offset)]>; 487 488let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 489def TCRETURNri : Pseudo<(outs), (ins CTRRC:$dst, i32imm:$offset, variable_ops), 490 "#TC_RETURNr $dst $offset", 491 []>; 492 493 494let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1, 495 isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR, RM] in 496def TAILBCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>, 497 Requires<[In32BitMode]>; 498 499 500 501let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 502 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 503def TAILB : IForm<18, 0, 0, (outs), (ins calltarget:$dst), 504 "b $dst", BrB, 505 []>; 506 507 508let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 509 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 510def TAILBA : IForm<18, 0, 0, (outs), (ins aaddr:$dst), 511 "ba $dst", BrB, 512 []>; 513 514 515// DCB* instructions. 516def DCBA : DCB_Form<758, 0, (outs), (ins memrr:$dst), 517 "dcba $dst", LdStDCBF, [(int_ppc_dcba xoaddr:$dst)]>, 518 PPC970_DGroup_Single; 519def DCBF : DCB_Form<86, 0, (outs), (ins memrr:$dst), 520 "dcbf $dst", LdStDCBF, [(int_ppc_dcbf xoaddr:$dst)]>, 521 PPC970_DGroup_Single; 522def DCBI : DCB_Form<470, 0, (outs), (ins memrr:$dst), 523 "dcbi $dst", LdStDCBF, [(int_ppc_dcbi xoaddr:$dst)]>, 524 PPC970_DGroup_Single; 525def DCBST : DCB_Form<54, 0, (outs), (ins memrr:$dst), 526 "dcbst $dst", LdStDCBF, [(int_ppc_dcbst xoaddr:$dst)]>, 527 PPC970_DGroup_Single; 528def DCBT : DCB_Form<278, 0, (outs), (ins memrr:$dst), 529 "dcbt $dst", LdStDCBF, [(int_ppc_dcbt xoaddr:$dst)]>, 530 PPC970_DGroup_Single; 531def DCBTST : DCB_Form<246, 0, (outs), (ins memrr:$dst), 532 "dcbtst $dst", LdStDCBF, [(int_ppc_dcbtst xoaddr:$dst)]>, 533 PPC970_DGroup_Single; 534def DCBZ : DCB_Form<1014, 0, (outs), (ins memrr:$dst), 535 "dcbz $dst", LdStDCBF, [(int_ppc_dcbz xoaddr:$dst)]>, 536 PPC970_DGroup_Single; 537def DCBZL : DCB_Form<1014, 1, (outs), (ins memrr:$dst), 538 "dcbzl $dst", LdStDCBF, [(int_ppc_dcbzl xoaddr:$dst)]>, 539 PPC970_DGroup_Single; 540 541// Atomic operations 542let usesCustomInserter = 1 in { 543 let Uses = [CR0] in { 544 def ATOMIC_LOAD_ADD_I8 : Pseudo< 545 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), 546 "${:comment} ATOMIC_LOAD_ADD_I8 PSEUDO!", 547 [(set GPRC:$dst, (atomic_load_add_8 xoaddr:$ptr, GPRC:$incr))]>; 548 def ATOMIC_LOAD_SUB_I8 : Pseudo< 549 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), 550 "${:comment} ATOMIC_LOAD_SUB_I8 PSEUDO!", 551 [(set GPRC:$dst, (atomic_load_sub_8 xoaddr:$ptr, GPRC:$incr))]>; 552 def ATOMIC_LOAD_AND_I8 : Pseudo< 553 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), 554 "${:comment} ATOMIC_LOAD_AND_I8 PSEUDO!", 555 [(set GPRC:$dst, (atomic_load_and_8 xoaddr:$ptr, GPRC:$incr))]>; 556 def ATOMIC_LOAD_OR_I8 : Pseudo< 557 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), 558 "${:comment} ATOMIC_LOAD_OR_I8 PSEUDO!", 559 [(set GPRC:$dst, (atomic_load_or_8 xoaddr:$ptr, GPRC:$incr))]>; 560 def ATOMIC_LOAD_XOR_I8 : Pseudo< 561 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), 562 "${:comment} ATOMIC_LOAD_XOR_I8 PSEUDO!", 563 [(set GPRC:$dst, (atomic_load_xor_8 xoaddr:$ptr, GPRC:$incr))]>; 564 def ATOMIC_LOAD_NAND_I8 : Pseudo< 565 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), 566 "${:comment} ATOMIC_LOAD_NAND_I8 PSEUDO!", 567 [(set GPRC:$dst, (atomic_load_nand_8 xoaddr:$ptr, GPRC:$incr))]>; 568 def ATOMIC_LOAD_ADD_I16 : Pseudo< 569 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), 570 "${:comment} ATOMIC_LOAD_ADD_I16 PSEUDO!", 571 [(set GPRC:$dst, (atomic_load_add_16 xoaddr:$ptr, GPRC:$incr))]>; 572 def ATOMIC_LOAD_SUB_I16 : Pseudo< 573 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), 574 "${:comment} ATOMIC_LOAD_SUB_I16 PSEUDO!", 575 [(set GPRC:$dst, (atomic_load_sub_16 xoaddr:$ptr, GPRC:$incr))]>; 576 def ATOMIC_LOAD_AND_I16 : Pseudo< 577 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), 578 "${:comment} ATOMIC_LOAD_AND_I16 PSEUDO!", 579 [(set GPRC:$dst, (atomic_load_and_16 xoaddr:$ptr, GPRC:$incr))]>; 580 def ATOMIC_LOAD_OR_I16 : Pseudo< 581 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), 582 "${:comment} ATOMIC_LOAD_OR_I16 PSEUDO!", 583 [(set GPRC:$dst, (atomic_load_or_16 xoaddr:$ptr, GPRC:$incr))]>; 584 def ATOMIC_LOAD_XOR_I16 : Pseudo< 585 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), 586 "${:comment} ATOMIC_LOAD_XOR_I16 PSEUDO!", 587 [(set GPRC:$dst, (atomic_load_xor_16 xoaddr:$ptr, GPRC:$incr))]>; 588 def ATOMIC_LOAD_NAND_I16 : Pseudo< 589 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), 590 "${:comment} ATOMIC_LOAD_NAND_I16 PSEUDO!", 591 [(set GPRC:$dst, (atomic_load_nand_16 xoaddr:$ptr, GPRC:$incr))]>; 592 def ATOMIC_LOAD_ADD_I32 : Pseudo< 593 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), 594 "${:comment} ATOMIC_LOAD_ADD_I32 PSEUDO!", 595 [(set GPRC:$dst, (atomic_load_add_32 xoaddr:$ptr, GPRC:$incr))]>; 596 def ATOMIC_LOAD_SUB_I32 : Pseudo< 597 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), 598 "${:comment} ATOMIC_LOAD_SUB_I32 PSEUDO!", 599 [(set GPRC:$dst, (atomic_load_sub_32 xoaddr:$ptr, GPRC:$incr))]>; 600 def ATOMIC_LOAD_AND_I32 : Pseudo< 601 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), 602 "${:comment} ATOMIC_LOAD_AND_I32 PSEUDO!", 603 [(set GPRC:$dst, (atomic_load_and_32 xoaddr:$ptr, GPRC:$incr))]>; 604 def ATOMIC_LOAD_OR_I32 : Pseudo< 605 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), 606 "${:comment} ATOMIC_LOAD_OR_I32 PSEUDO!", 607 [(set GPRC:$dst, (atomic_load_or_32 xoaddr:$ptr, GPRC:$incr))]>; 608 def ATOMIC_LOAD_XOR_I32 : Pseudo< 609 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), 610 "${:comment} ATOMIC_LOAD_XOR_I32 PSEUDO!", 611 [(set GPRC:$dst, (atomic_load_xor_32 xoaddr:$ptr, GPRC:$incr))]>; 612 def ATOMIC_LOAD_NAND_I32 : Pseudo< 613 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), 614 "${:comment} ATOMIC_LOAD_NAND_I32 PSEUDO!", 615 [(set GPRC:$dst, (atomic_load_nand_32 xoaddr:$ptr, GPRC:$incr))]>; 616 617 def ATOMIC_CMP_SWAP_I8 : Pseudo< 618 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$old, GPRC:$new), 619 "${:comment} ATOMIC_CMP_SWAP_I8 PSEUDO!", 620 [(set GPRC:$dst, 621 (atomic_cmp_swap_8 xoaddr:$ptr, GPRC:$old, GPRC:$new))]>; 622 def ATOMIC_CMP_SWAP_I16 : Pseudo< 623 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$old, GPRC:$new), 624 "${:comment} ATOMIC_CMP_SWAP_I16 PSEUDO!", 625 [(set GPRC:$dst, 626 (atomic_cmp_swap_16 xoaddr:$ptr, GPRC:$old, GPRC:$new))]>; 627 def ATOMIC_CMP_SWAP_I32 : Pseudo< 628 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$old, GPRC:$new), 629 "${:comment} ATOMIC_CMP_SWAP_I32 PSEUDO!", 630 [(set GPRC:$dst, 631 (atomic_cmp_swap_32 xoaddr:$ptr, GPRC:$old, GPRC:$new))]>; 632 633 def ATOMIC_SWAP_I8 : Pseudo< 634 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$new), 635 "${:comment} ATOMIC_SWAP_I8 PSEUDO!", 636 [(set GPRC:$dst, (atomic_swap_8 xoaddr:$ptr, GPRC:$new))]>; 637 def ATOMIC_SWAP_I16 : Pseudo< 638 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$new), 639 "${:comment} ATOMIC_SWAP_I16 PSEUDO!", 640 [(set GPRC:$dst, (atomic_swap_16 xoaddr:$ptr, GPRC:$new))]>; 641 def ATOMIC_SWAP_I32 : Pseudo< 642 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$new), 643 "${:comment} ATOMIC_SWAP_I32 PSEUDO!", 644 [(set GPRC:$dst, (atomic_swap_32 xoaddr:$ptr, GPRC:$new))]>; 645 } 646} 647 648// Instructions to support atomic operations 649def LWARX : XForm_1<31, 20, (outs GPRC:$rD), (ins memrr:$src), 650 "lwarx $rD, $src", LdStLWARX, 651 [(set GPRC:$rD, (PPClarx xoaddr:$src))]>; 652 653let Defs = [CR0] in 654def STWCX : XForm_1<31, 150, (outs), (ins GPRC:$rS, memrr:$dst), 655 "stwcx. $rS, $dst", LdStSTWCX, 656 [(PPCstcx GPRC:$rS, xoaddr:$dst)]>, 657 isDOT; 658 659let isBarrier = 1, hasCtrlDep = 1 in 660def TRAP : XForm_24<31, 4, (outs), (ins), "trap", LdStGeneral, [(trap)]>; 661 662//===----------------------------------------------------------------------===// 663// PPC32 Load Instructions. 664// 665 666// Unindexed (r+i) Loads. 667let canFoldAsLoad = 1, PPC970_Unit = 2 in { 668def LBZ : DForm_1<34, (outs GPRC:$rD), (ins memri:$src), 669 "lbz $rD, $src", LdStGeneral, 670 [(set GPRC:$rD, (zextloadi8 iaddr:$src))]>; 671def LHA : DForm_1<42, (outs GPRC:$rD), (ins memri:$src), 672 "lha $rD, $src", LdStLHA, 673 [(set GPRC:$rD, (sextloadi16 iaddr:$src))]>, 674 PPC970_DGroup_Cracked; 675def LHZ : DForm_1<40, (outs GPRC:$rD), (ins memri:$src), 676 "lhz $rD, $src", LdStGeneral, 677 [(set GPRC:$rD, (zextloadi16 iaddr:$src))]>; 678def LWZ : DForm_1<32, (outs GPRC:$rD), (ins memri:$src), 679 "lwz $rD, $src", LdStGeneral, 680 [(set GPRC:$rD, (load iaddr:$src))]>; 681 682def LFS : DForm_1<48, (outs F4RC:$rD), (ins memri:$src), 683 "lfs $rD, $src", LdStLFDU, 684 [(set F4RC:$rD, (load iaddr:$src))]>; 685def LFD : DForm_1<50, (outs F8RC:$rD), (ins memri:$src), 686 "lfd $rD, $src", LdStLFD, 687 [(set F8RC:$rD, (load iaddr:$src))]>; 688 689 690// Unindexed (r+i) Loads with Update (preinc). 691let mayLoad = 1 in { 692def LBZU : DForm_1<35, (outs GPRC:$rD, ptr_rc:$ea_result), (ins memri:$addr), 693 "lbzu $rD, $addr", LdStGeneral, 694 []>, RegConstraint<"$addr.reg = $ea_result">, 695 NoEncode<"$ea_result">; 696 697def LHAU : DForm_1<43, (outs GPRC:$rD, ptr_rc:$ea_result), (ins memri:$addr), 698 "lhau $rD, $addr", LdStGeneral, 699 []>, RegConstraint<"$addr.reg = $ea_result">, 700 NoEncode<"$ea_result">; 701 702def LHZU : DForm_1<41, (outs GPRC:$rD, ptr_rc:$ea_result), (ins memri:$addr), 703 "lhzu $rD, $addr", LdStGeneral, 704 []>, RegConstraint<"$addr.reg = $ea_result">, 705 NoEncode<"$ea_result">; 706 707def LWZU : DForm_1<33, (outs GPRC:$rD, ptr_rc:$ea_result), (ins memri:$addr), 708 "lwzu $rD, $addr", LdStGeneral, 709 []>, RegConstraint<"$addr.reg = $ea_result">, 710 NoEncode<"$ea_result">; 711 712def LFSU : DForm_1<49, (outs F4RC:$rD, ptr_rc:$ea_result), (ins memri:$addr), 713 "lfs $rD, $addr", LdStLFDU, 714 []>, RegConstraint<"$addr.reg = $ea_result">, 715 NoEncode<"$ea_result">; 716 717def LFDU : DForm_1<51, (outs F8RC:$rD, ptr_rc:$ea_result), (ins memri:$addr), 718 "lfd $rD, $addr", LdStLFD, 719 []>, RegConstraint<"$addr.reg = $ea_result">, 720 NoEncode<"$ea_result">; 721} 722} 723 724// Indexed (r+r) Loads. 725// 726let canFoldAsLoad = 1, PPC970_Unit = 2 in { 727def LBZX : XForm_1<31, 87, (outs GPRC:$rD), (ins memrr:$src), 728 "lbzx $rD, $src", LdStGeneral, 729 [(set GPRC:$rD, (zextloadi8 xaddr:$src))]>; 730def LHAX : XForm_1<31, 343, (outs GPRC:$rD), (ins memrr:$src), 731 "lhax $rD, $src", LdStLHA, 732 [(set GPRC:$rD, (sextloadi16 xaddr:$src))]>, 733 PPC970_DGroup_Cracked; 734def LHZX : XForm_1<31, 279, (outs GPRC:$rD), (ins memrr:$src), 735 "lhzx $rD, $src", LdStGeneral, 736 [(set GPRC:$rD, (zextloadi16 xaddr:$src))]>; 737def LWZX : XForm_1<31, 23, (outs GPRC:$rD), (ins memrr:$src), 738 "lwzx $rD, $src", LdStGeneral, 739 [(set GPRC:$rD, (load xaddr:$src))]>; 740 741 742def LHBRX : XForm_1<31, 790, (outs GPRC:$rD), (ins memrr:$src), 743 "lhbrx $rD, $src", LdStGeneral, 744 [(set GPRC:$rD, (PPClbrx xoaddr:$src, i16))]>; 745def LWBRX : XForm_1<31, 534, (outs GPRC:$rD), (ins memrr:$src), 746 "lwbrx $rD, $src", LdStGeneral, 747 [(set GPRC:$rD, (PPClbrx xoaddr:$src, i32))]>; 748 749def LFSX : XForm_25<31, 535, (outs F4RC:$frD), (ins memrr:$src), 750 "lfsx $frD, $src", LdStLFDU, 751 [(set F4RC:$frD, (load xaddr:$src))]>; 752def LFDX : XForm_25<31, 599, (outs F8RC:$frD), (ins memrr:$src), 753 "lfdx $frD, $src", LdStLFDU, 754 [(set F8RC:$frD, (load xaddr:$src))]>; 755} 756 757//===----------------------------------------------------------------------===// 758// PPC32 Store Instructions. 759// 760 761// Unindexed (r+i) Stores. 762let PPC970_Unit = 2 in { 763def STB : DForm_1<38, (outs), (ins GPRC:$rS, memri:$src), 764 "stb $rS, $src", LdStGeneral, 765 [(truncstorei8 GPRC:$rS, iaddr:$src)]>; 766def STH : DForm_1<44, (outs), (ins GPRC:$rS, memri:$src), 767 "sth $rS, $src", LdStGeneral, 768 [(truncstorei16 GPRC:$rS, iaddr:$src)]>; 769def STW : DForm_1<36, (outs), (ins GPRC:$rS, memri:$src), 770 "stw $rS, $src", LdStGeneral, 771 [(store GPRC:$rS, iaddr:$src)]>; 772def STFS : DForm_1<52, (outs), (ins F4RC:$rS, memri:$dst), 773 "stfs $rS, $dst", LdStUX, 774 [(store F4RC:$rS, iaddr:$dst)]>; 775def STFD : DForm_1<54, (outs), (ins F8RC:$rS, memri:$dst), 776 "stfd $rS, $dst", LdStUX, 777 [(store F8RC:$rS, iaddr:$dst)]>; 778} 779 780// Unindexed (r+i) Stores with Update (preinc). 781let PPC970_Unit = 2 in { 782def STBU : DForm_1<39, (outs ptr_rc:$ea_res), (ins GPRC:$rS, 783 symbolLo:$ptroff, ptr_rc:$ptrreg), 784 "stbu $rS, $ptroff($ptrreg)", LdStGeneral, 785 [(set ptr_rc:$ea_res, 786 (pre_truncsti8 GPRC:$rS, ptr_rc:$ptrreg, 787 iaddroff:$ptroff))]>, 788 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">; 789def STHU : DForm_1<45, (outs ptr_rc:$ea_res), (ins GPRC:$rS, 790 symbolLo:$ptroff, ptr_rc:$ptrreg), 791 "sthu $rS, $ptroff($ptrreg)", LdStGeneral, 792 [(set ptr_rc:$ea_res, 793 (pre_truncsti16 GPRC:$rS, ptr_rc:$ptrreg, 794 iaddroff:$ptroff))]>, 795 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">; 796def STWU : DForm_1<37, (outs ptr_rc:$ea_res), (ins GPRC:$rS, 797 symbolLo:$ptroff, ptr_rc:$ptrreg), 798 "stwu $rS, $ptroff($ptrreg)", LdStGeneral, 799 [(set ptr_rc:$ea_res, (pre_store GPRC:$rS, ptr_rc:$ptrreg, 800 iaddroff:$ptroff))]>, 801 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">; 802def STFSU : DForm_1<37, (outs ptr_rc:$ea_res), (ins F4RC:$rS, 803 symbolLo:$ptroff, ptr_rc:$ptrreg), 804 "stfsu $rS, $ptroff($ptrreg)", LdStGeneral, 805 [(set ptr_rc:$ea_res, (pre_store F4RC:$rS, ptr_rc:$ptrreg, 806 iaddroff:$ptroff))]>, 807 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">; 808def STFDU : DForm_1<37, (outs ptr_rc:$ea_res), (ins F8RC:$rS, 809 symbolLo:$ptroff, ptr_rc:$ptrreg), 810 "stfdu $rS, $ptroff($ptrreg)", LdStGeneral, 811 [(set ptr_rc:$ea_res, (pre_store F8RC:$rS, ptr_rc:$ptrreg, 812 iaddroff:$ptroff))]>, 813 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">; 814} 815 816 817// Indexed (r+r) Stores. 818// 819let PPC970_Unit = 2 in { 820def STBX : XForm_8<31, 215, (outs), (ins GPRC:$rS, memrr:$dst), 821 "stbx $rS, $dst", LdStGeneral, 822 [(truncstorei8 GPRC:$rS, xaddr:$dst)]>, 823 PPC970_DGroup_Cracked; 824def STHX : XForm_8<31, 407, (outs), (ins GPRC:$rS, memrr:$dst), 825 "sthx $rS, $dst", LdStGeneral, 826 [(truncstorei16 GPRC:$rS, xaddr:$dst)]>, 827 PPC970_DGroup_Cracked; 828def STWX : XForm_8<31, 151, (outs), (ins GPRC:$rS, memrr:$dst), 829 "stwx $rS, $dst", LdStGeneral, 830 [(store GPRC:$rS, xaddr:$dst)]>, 831 PPC970_DGroup_Cracked; 832 833let mayStore = 1 in { 834def STWUX : XForm_8<31, 183, (outs), (ins GPRC:$rS, GPRC:$rA, GPRC:$rB), 835 "stwux $rS, $rA, $rB", LdStGeneral, 836 []>; 837} 838def STHBRX: XForm_8<31, 918, (outs), (ins GPRC:$rS, memrr:$dst), 839 "sthbrx $rS, $dst", LdStGeneral, 840 [(PPCstbrx GPRC:$rS, xoaddr:$dst, i16)]>, 841 PPC970_DGroup_Cracked; 842def STWBRX: XForm_8<31, 662, (outs), (ins GPRC:$rS, memrr:$dst), 843 "stwbrx $rS, $dst", LdStGeneral, 844 [(PPCstbrx GPRC:$rS, xoaddr:$dst, i32)]>, 845 PPC970_DGroup_Cracked; 846 847def STFIWX: XForm_28<31, 983, (outs), (ins F8RC:$frS, memrr:$dst), 848 "stfiwx $frS, $dst", LdStUX, 849 [(PPCstfiwx F8RC:$frS, xoaddr:$dst)]>; 850 851def STFSX : XForm_28<31, 663, (outs), (ins F4RC:$frS, memrr:$dst), 852 "stfsx $frS, $dst", LdStUX, 853 [(store F4RC:$frS, xaddr:$dst)]>; 854def STFDX : XForm_28<31, 727, (outs), (ins F8RC:$frS, memrr:$dst), 855 "stfdx $frS, $dst", LdStUX, 856 [(store F8RC:$frS, xaddr:$dst)]>; 857} 858 859let isBarrier = 1 in 860def SYNC : XForm_24_sync<31, 598, (outs), (ins), 861 "sync", LdStSync, 862 [(int_ppc_sync)]>; 863 864//===----------------------------------------------------------------------===// 865// PPC32 Arithmetic Instructions. 866// 867 868let PPC970_Unit = 1 in { // FXU Operations. 869def ADDI : DForm_2<14, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm), 870 "addi $rD, $rA, $imm", IntGeneral, 871 [(set GPRC:$rD, (add GPRC:$rA, immSExt16:$imm))]>; 872let Defs = [CARRY] in { 873def ADDIC : DForm_2<12, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm), 874 "addic $rD, $rA, $imm", IntGeneral, 875 [(set GPRC:$rD, (addc GPRC:$rA, immSExt16:$imm))]>, 876 PPC970_DGroup_Cracked; 877def ADDICo : DForm_2<13, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm), 878 "addic. $rD, $rA, $imm", IntGeneral, 879 []>; 880} 881def ADDIS : DForm_2<15, (outs GPRC:$rD), (ins GPRC:$rA, symbolHi:$imm), 882 "addis $rD, $rA, $imm", IntGeneral, 883 [(set GPRC:$rD, (add GPRC:$rA, imm16ShiftedSExt:$imm))]>; 884def LA : DForm_2<14, (outs GPRC:$rD), (ins GPRC:$rA, symbolLo:$sym), 885 "la $rD, $sym($rA)", IntGeneral, 886 [(set GPRC:$rD, (add GPRC:$rA, 887 (PPClo tglobaladdr:$sym, 0)))]>; 888def MULLI : DForm_2< 7, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm), 889 "mulli $rD, $rA, $imm", IntMulLI, 890 [(set GPRC:$rD, (mul GPRC:$rA, immSExt16:$imm))]>; 891let Defs = [CARRY] in { 892def SUBFIC : DForm_2< 8, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm), 893 "subfic $rD, $rA, $imm", IntGeneral, 894 [(set GPRC:$rD, (subc immSExt16:$imm, GPRC:$rA))]>; 895} 896 897let isReMaterializable = 1 in { 898 def LI : DForm_2_r0<14, (outs GPRC:$rD), (ins symbolLo:$imm), 899 "li $rD, $imm", IntGeneral, 900 [(set GPRC:$rD, immSExt16:$imm)]>; 901 def LIS : DForm_2_r0<15, (outs GPRC:$rD), (ins symbolHi:$imm), 902 "lis $rD, $imm", IntGeneral, 903 [(set GPRC:$rD, imm16ShiftedSExt:$imm)]>; 904} 905} 906 907let PPC970_Unit = 1 in { // FXU Operations. 908def ANDIo : DForm_4<28, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2), 909 "andi. $dst, $src1, $src2", IntGeneral, 910 [(set GPRC:$dst, (and GPRC:$src1, immZExt16:$src2))]>, 911 isDOT; 912def ANDISo : DForm_4<29, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2), 913 "andis. $dst, $src1, $src2", IntGeneral, 914 [(set GPRC:$dst, (and GPRC:$src1,imm16ShiftedZExt:$src2))]>, 915 isDOT; 916def ORI : DForm_4<24, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2), 917 "ori $dst, $src1, $src2", IntGeneral, 918 [(set GPRC:$dst, (or GPRC:$src1, immZExt16:$src2))]>; 919def ORIS : DForm_4<25, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2), 920 "oris $dst, $src1, $src2", IntGeneral, 921 [(set GPRC:$dst, (or GPRC:$src1, imm16ShiftedZExt:$src2))]>; 922def XORI : DForm_4<26, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2), 923 "xori $dst, $src1, $src2", IntGeneral, 924 [(set GPRC:$dst, (xor GPRC:$src1, immZExt16:$src2))]>; 925def XORIS : DForm_4<27, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2), 926 "xoris $dst, $src1, $src2", IntGeneral, 927 [(set GPRC:$dst, (xor GPRC:$src1,imm16ShiftedZExt:$src2))]>; 928def NOP : DForm_4_zero<24, (outs), (ins), "nop", IntGeneral, 929 []>; 930def CMPWI : DForm_5_ext<11, (outs CRRC:$crD), (ins GPRC:$rA, s16imm:$imm), 931 "cmpwi $crD, $rA, $imm", IntCompare>; 932def CMPLWI : DForm_6_ext<10, (outs CRRC:$dst), (ins GPRC:$src1, u16imm:$src2), 933 "cmplwi $dst, $src1, $src2", IntCompare>; 934} 935 936 937let PPC970_Unit = 1 in { // FXU Operations. 938def NAND : XForm_6<31, 476, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB), 939 "nand $rA, $rS, $rB", IntGeneral, 940 [(set GPRC:$rA, (not (and GPRC:$rS, GPRC:$rB)))]>; 941def AND : XForm_6<31, 28, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB), 942 "and $rA, $rS, $rB", IntGeneral, 943 [(set GPRC:$rA, (and GPRC:$rS, GPRC:$rB))]>; 944def ANDC : XForm_6<31, 60, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB), 945 "andc $rA, $rS, $rB", IntGeneral, 946 [(set GPRC:$rA, (and GPRC:$rS, (not GPRC:$rB)))]>; 947def OR : XForm_6<31, 444, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB), 948 "or $rA, $rS, $rB", IntGeneral, 949 [(set GPRC:$rA, (or GPRC:$rS, GPRC:$rB))]>; 950def NOR : XForm_6<31, 124, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB), 951 "nor $rA, $rS, $rB", IntGeneral, 952 [(set GPRC:$rA, (not (or GPRC:$rS, GPRC:$rB)))]>; 953def ORC : XForm_6<31, 412, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB), 954 "orc $rA, $rS, $rB", IntGeneral, 955 [(set GPRC:$rA, (or GPRC:$rS, (not GPRC:$rB)))]>; 956def EQV : XForm_6<31, 284, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB), 957 "eqv $rA, $rS, $rB", IntGeneral, 958 [(set GPRC:$rA, (not (xor GPRC:$rS, GPRC:$rB)))]>; 959def XOR : XForm_6<31, 316, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB), 960 "xor $rA, $rS, $rB", IntGeneral, 961 [(set GPRC:$rA, (xor GPRC:$rS, GPRC:$rB))]>; 962def SLW : XForm_6<31, 24, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB), 963 "slw $rA, $rS, $rB", IntGeneral, 964 [(set GPRC:$rA, (PPCshl GPRC:$rS, GPRC:$rB))]>; 965def SRW : XForm_6<31, 536, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB), 966 "srw $rA, $rS, $rB", IntGeneral, 967 [(set GPRC:$rA, (PPCsrl GPRC:$rS, GPRC:$rB))]>; 968let Defs = [CARRY] in { 969def SRAW : XForm_6<31, 792, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB), 970 "sraw $rA, $rS, $rB", IntShift, 971 [(set GPRC:$rA, (PPCsra GPRC:$rS, GPRC:$rB))]>; 972} 973} 974 975let PPC970_Unit = 1 in { // FXU Operations. 976let Defs = [CARRY] in { 977def SRAWI : XForm_10<31, 824, (outs GPRC:$rA), (ins GPRC:$rS, u5imm:$SH), 978 "srawi $rA, $rS, $SH", IntShift, 979 [(set GPRC:$rA, (sra GPRC:$rS, (i32 imm:$SH)))]>; 980} 981def CNTLZW : XForm_11<31, 26, (outs GPRC:$rA), (ins GPRC:$rS), 982 "cntlzw $rA, $rS", IntGeneral, 983 [(set GPRC:$rA, (ctlz GPRC:$rS))]>; 984def EXTSB : XForm_11<31, 954, (outs GPRC:$rA), (ins GPRC:$rS), 985 "extsb $rA, $rS", IntGeneral, 986 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i8))]>; 987def EXTSH : XForm_11<31, 922, (outs GPRC:$rA), (ins GPRC:$rS), 988 "extsh $rA, $rS", IntGeneral, 989 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i16))]>; 990 991def CMPW : XForm_16_ext<31, 0, (outs CRRC:$crD), (ins GPRC:$rA, GPRC:$rB), 992 "cmpw $crD, $rA, $rB", IntCompare>; 993def CMPLW : XForm_16_ext<31, 32, (outs CRRC:$crD), (ins GPRC:$rA, GPRC:$rB), 994 "cmplw $crD, $rA, $rB", IntCompare>; 995} 996let PPC970_Unit = 3 in { // FPU Operations. 997//def FCMPO : XForm_17<63, 32, (outs CRRC:$crD), (ins FPRC:$fA, FPRC:$fB), 998// "fcmpo $crD, $fA, $fB", FPCompare>; 999def FCMPUS : XForm_17<63, 0, (outs CRRC:$crD), (ins F4RC:$fA, F4RC:$fB), 1000 "fcmpu $crD, $fA, $fB", FPCompare>; 1001def FCMPUD : XForm_17<63, 0, (outs CRRC:$crD), (ins F8RC:$fA, F8RC:$fB), 1002 "fcmpu $crD, $fA, $fB", FPCompare>; 1003 1004let Uses = [RM] in { 1005 def FCTIWZ : XForm_26<63, 15, (outs F8RC:$frD), (ins F8RC:$frB), 1006 "fctiwz $frD, $frB", FPGeneral, 1007 [(set F8RC:$frD, (PPCfctiwz F8RC:$frB))]>; 1008 def FRSP : XForm_26<63, 12, (outs F4RC:$frD), (ins F8RC:$frB), 1009 "frsp $frD, $frB", FPGeneral, 1010 [(set F4RC:$frD, (fround F8RC:$frB))]>; 1011 def FSQRT : XForm_26<63, 22, (outs F8RC:$frD), (ins F8RC:$frB), 1012 "fsqrt $frD, $frB", FPSqrt, 1013 [(set F8RC:$frD, (fsqrt F8RC:$frB))]>; 1014 def FSQRTS : XForm_26<59, 22, (outs F4RC:$frD), (ins F4RC:$frB), 1015 "fsqrts $frD, $frB", FPSqrt, 1016 [(set F4RC:$frD, (fsqrt F4RC:$frB))]>; 1017 } 1018} 1019 1020/// FMR is split into 3 versions, one for 4/8 byte FP, and one for extending. 1021/// 1022/// Note that these are defined as pseudo-ops on the PPC970 because they are 1023/// often coalesced away and we don't want the dispatch group builder to think 1024/// that they will fill slots (which could cause the load of a LSU reject to 1025/// sneak into a d-group with a store). 1026def FMRS : XForm_26<63, 72, (outs F4RC:$frD), (ins F4RC:$frB), 1027 "fmr $frD, $frB", FPGeneral, 1028 []>, // (set F4RC:$frD, F4RC:$frB) 1029 PPC970_Unit_Pseudo; 1030def FMRD : XForm_26<63, 72, (outs F8RC:$frD), (ins F8RC:$frB), 1031 "fmr $frD, $frB", FPGeneral, 1032 []>, // (set F8RC:$frD, F8RC:$frB) 1033 PPC970_Unit_Pseudo; 1034def FMRSD : XForm_26<63, 72, (outs F8RC:$frD), (ins F4RC:$frB), 1035 "fmr $frD, $frB", FPGeneral, 1036 [(set F8RC:$frD, (fextend F4RC:$frB))]>, 1037 PPC970_Unit_Pseudo; 1038 1039let PPC970_Unit = 3 in { // FPU Operations. 1040// These are artificially split into two different forms, for 4/8 byte FP. 1041def FABSS : XForm_26<63, 264, (outs F4RC:$frD), (ins F4RC:$frB), 1042 "fabs $frD, $frB", FPGeneral, 1043 [(set F4RC:$frD, (fabs F4RC:$frB))]>; 1044def FABSD : XForm_26<63, 264, (outs F8RC:$frD), (ins F8RC:$frB), 1045 "fabs $frD, $frB", FPGeneral, 1046 [(set F8RC:$frD, (fabs F8RC:$frB))]>; 1047def FNABSS : XForm_26<63, 136, (outs F4RC:$frD), (ins F4RC:$frB), 1048 "fnabs $frD, $frB", FPGeneral, 1049 [(set F4RC:$frD, (fneg (fabs F4RC:$frB)))]>; 1050def FNABSD : XForm_26<63, 136, (outs F8RC:$frD), (ins F8RC:$frB), 1051 "fnabs $frD, $frB", FPGeneral, 1052 [(set F8RC:$frD, (fneg (fabs F8RC:$frB)))]>; 1053def FNEGS : XForm_26<63, 40, (outs F4RC:$frD), (ins F4RC:$frB), 1054 "fneg $frD, $frB", FPGeneral, 1055 [(set F4RC:$frD, (fneg F4RC:$frB))]>; 1056def FNEGD : XForm_26<63, 40, (outs F8RC:$frD), (ins F8RC:$frB), 1057 "fneg $frD, $frB", FPGeneral, 1058 [(set F8RC:$frD, (fneg F8RC:$frB))]>; 1059} 1060 1061 1062// XL-Form instructions. condition register logical ops. 1063// 1064def MCRF : XLForm_3<19, 0, (outs CRRC:$BF), (ins CRRC:$BFA), 1065 "mcrf $BF, $BFA", BrMCR>, 1066 PPC970_DGroup_First, PPC970_Unit_CRU; 1067 1068def CREQV : XLForm_1<19, 289, (outs CRBITRC:$CRD), 1069 (ins CRBITRC:$CRA, CRBITRC:$CRB), 1070 "creqv $CRD, $CRA, $CRB", BrCR, 1071 []>; 1072 1073def CROR : XLForm_1<19, 449, (outs CRBITRC:$CRD), 1074 (ins CRBITRC:$CRA, CRBITRC:$CRB), 1075 "cror $CRD, $CRA, $CRB", BrCR, 1076 []>; 1077 1078def CRSET : XLForm_1_ext<19, 289, (outs CRBITRC:$dst), (ins), 1079 "creqv $dst, $dst, $dst", BrCR, 1080 []>; 1081 1082// XFX-Form instructions. Instructions that deal with SPRs. 1083// 1084let Uses = [CTR] in { 1085def MFCTR : XFXForm_1_ext<31, 339, 9, (outs GPRC:$rT), (ins), 1086 "mfctr $rT", SprMFSPR>, 1087 PPC970_DGroup_First, PPC970_Unit_FXU; 1088} 1089let Defs = [CTR], Pattern = [(PPCmtctr GPRC:$rS)] in { 1090def MTCTR : XFXForm_7_ext<31, 467, 9, (outs), (ins GPRC:$rS), 1091 "mtctr $rS", SprMTSPR>, 1092 PPC970_DGroup_First, PPC970_Unit_FXU; 1093} 1094 1095let Defs = [LR] in { 1096def MTLR : XFXForm_7_ext<31, 467, 8, (outs), (ins GPRC:$rS), 1097 "mtlr $rS", SprMTSPR>, 1098 PPC970_DGroup_First, PPC970_Unit_FXU; 1099} 1100let Uses = [LR] in { 1101def MFLR : XFXForm_1_ext<31, 339, 8, (outs GPRC:$rT), (ins), 1102 "mflr $rT", SprMFSPR>, 1103 PPC970_DGroup_First, PPC970_Unit_FXU; 1104} 1105 1106// Move to/from VRSAVE: despite being a SPR, the VRSAVE register is renamed like 1107// a GPR on the PPC970. As such, copies in and out have the same performance 1108// characteristics as an OR instruction. 1109def MTVRSAVE : XFXForm_7_ext<31, 467, 256, (outs), (ins GPRC:$rS), 1110 "mtspr 256, $rS", IntGeneral>, 1111 PPC970_DGroup_Single, PPC970_Unit_FXU; 1112def MFVRSAVE : XFXForm_1_ext<31, 339, 256, (outs GPRC:$rT), (ins), 1113 "mfspr $rT, 256", IntGeneral>, 1114 PPC970_DGroup_First, PPC970_Unit_FXU; 1115 1116def MTCRF : XFXForm_5<31, 144, (outs), (ins crbitm:$FXM, GPRC:$rS), 1117 "mtcrf $FXM, $rS", BrMCRX>, 1118 PPC970_MicroCode, PPC970_Unit_CRU; 1119// FIXME: this Uses all the CR registers. Marking it as such is 1120// necessary for DeadMachineInstructionElim to do the right thing. 1121// However, marking it also exposes PR 2964, and causes crashes in 1122// the Local RA because it doesn't like this sequence: 1123// vreg = MCRF CR0 1124// MFCR <kill of whatever preg got assigned to vreg> 1125// For now DeadMachineInstructionElim is turned off, so don't do the marking. 1126def MFCR : XFXForm_3<31, 19, (outs GPRC:$rT), (ins), "mfcr $rT", SprMFCR>, 1127 PPC970_MicroCode, PPC970_Unit_CRU; 1128def MFOCRF: XFXForm_5a<31, 19, (outs GPRC:$rT), (ins crbitm:$FXM), 1129 "mfcr $rT, $FXM", SprMFCR>, 1130 PPC970_DGroup_First, PPC970_Unit_CRU; 1131 1132// Instructions to manipulate FPSCR. Only long double handling uses these. 1133// FPSCR is not modelled; we use the SDNode Flag to keep things in order. 1134 1135let Uses = [RM], Defs = [RM] in { 1136 def MTFSB0 : XForm_43<63, 70, (outs), (ins u5imm:$FM), 1137 "mtfsb0 $FM", IntMTFSB0, 1138 [(PPCmtfsb0 (i32 imm:$FM))]>, 1139 PPC970_DGroup_Single, PPC970_Unit_FPU; 1140 def MTFSB1 : XForm_43<63, 38, (outs), (ins u5imm:$FM), 1141 "mtfsb1 $FM", IntMTFSB0, 1142 [(PPCmtfsb1 (i32 imm:$FM))]>, 1143 PPC970_DGroup_Single, PPC970_Unit_FPU; 1144 // MTFSF does not actually produce an FP result. We pretend it copies 1145 // input reg B to the output. If we didn't do this it would look like the 1146 // instruction had no outputs (because we aren't modelling the FPSCR) and 1147 // it would be deleted. 1148 def MTFSF : XFLForm<63, 711, (outs F8RC:$FRA), 1149 (ins i32imm:$FM, F8RC:$rT, F8RC:$FRB), 1150 "mtfsf $FM, $rT", "$FRB = $FRA", IntMTFSB0, 1151 [(set F8RC:$FRA, (PPCmtfsf (i32 imm:$FM), 1152 F8RC:$rT, F8RC:$FRB))]>, 1153 PPC970_DGroup_Single, PPC970_Unit_FPU; 1154} 1155let Uses = [RM] in { 1156 def MFFS : XForm_42<63, 583, (outs F8RC:$rT), (ins), 1157 "mffs $rT", IntMFFS, 1158 [(set F8RC:$rT, (PPCmffs))]>, 1159 PPC970_DGroup_Single, PPC970_Unit_FPU; 1160 def FADDrtz: AForm_2<63, 21, 1161 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB), 1162 "fadd $FRT, $FRA, $FRB", FPGeneral, 1163 [(set F8RC:$FRT, (PPCfaddrtz F8RC:$FRA, F8RC:$FRB))]>, 1164 PPC970_DGroup_Single, PPC970_Unit_FPU; 1165} 1166 1167 1168let PPC970_Unit = 1 in { // FXU Operations. 1169 1170// XO-Form instructions. Arithmetic instructions that can set overflow bit 1171// 1172def ADD4 : XOForm_1<31, 266, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB), 1173 "add $rT, $rA, $rB", IntGeneral, 1174 [(set GPRC:$rT, (add GPRC:$rA, GPRC:$rB))]>; 1175let Defs = [CARRY] in { 1176def ADDC : XOForm_1<31, 10, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB), 1177 "addc $rT, $rA, $rB", IntGeneral, 1178 [(set GPRC:$rT, (addc GPRC:$rA, GPRC:$rB))]>, 1179 PPC970_DGroup_Cracked; 1180} 1181def DIVW : XOForm_1<31, 491, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB), 1182 "divw $rT, $rA, $rB", IntDivW, 1183 [(set GPRC:$rT, (sdiv GPRC:$rA, GPRC:$rB))]>, 1184 PPC970_DGroup_First, PPC970_DGroup_Cracked; 1185def DIVWU : XOForm_1<31, 459, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB), 1186 "divwu $rT, $rA, $rB", IntDivW, 1187 [(set GPRC:$rT, (udiv GPRC:$rA, GPRC:$rB))]>, 1188 PPC970_DGroup_First, PPC970_DGroup_Cracked; 1189def MULHW : XOForm_1<31, 75, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB), 1190 "mulhw $rT, $rA, $rB", IntMulHW, 1191 [(set GPRC:$rT, (mulhs GPRC:$rA, GPRC:$rB))]>; 1192def MULHWU : XOForm_1<31, 11, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB), 1193 "mulhwu $rT, $rA, $rB", IntMulHWU, 1194 [(set GPRC:$rT, (mulhu GPRC:$rA, GPRC:$rB))]>; 1195def MULLW : XOForm_1<31, 235, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB), 1196 "mullw $rT, $rA, $rB", IntMulHW, 1197 [(set GPRC:$rT, (mul GPRC:$rA, GPRC:$rB))]>; 1198def SUBF : XOForm_1<31, 40, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB), 1199 "subf $rT, $rA, $rB", IntGeneral, 1200 [(set GPRC:$rT, (sub GPRC:$rB, GPRC:$rA))]>; 1201let Defs = [CARRY] in { 1202def SUBFC : XOForm_1<31, 8, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB), 1203 "subfc $rT, $rA, $rB", IntGeneral, 1204 [(set GPRC:$rT, (subc GPRC:$rB, GPRC:$rA))]>, 1205 PPC970_DGroup_Cracked; 1206} 1207def NEG : XOForm_3<31, 104, 0, (outs GPRC:$rT), (ins GPRC:$rA), 1208 "neg $rT, $rA", IntGeneral, 1209 [(set GPRC:$rT, (ineg GPRC:$rA))]>; 1210let Uses = [CARRY], Defs = [CARRY] in { 1211def ADDE : XOForm_1<31, 138, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB), 1212 "adde $rT, $rA, $rB", IntGeneral, 1213 [(set GPRC:$rT, (adde GPRC:$rA, GPRC:$rB))]>; 1214def ADDME : XOForm_3<31, 234, 0, (outs GPRC:$rT), (ins GPRC:$rA), 1215 "addme $rT, $rA", IntGeneral, 1216 [(set GPRC:$rT, (adde GPRC:$rA, immAllOnes))]>; 1217def ADDZE : XOForm_3<31, 202, 0, (outs GPRC:$rT), (ins GPRC:$rA), 1218 "addze $rT, $rA", IntGeneral, 1219 [(set GPRC:$rT, (adde GPRC:$rA, 0))]>; 1220def SUBFE : XOForm_1<31, 136, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB), 1221 "subfe $rT, $rA, $rB", IntGeneral, 1222 [(set GPRC:$rT, (sube GPRC:$rB, GPRC:$rA))]>; 1223def SUBFME : XOForm_3<31, 232, 0, (outs GPRC:$rT), (ins GPRC:$rA), 1224 "subfme $rT, $rA", IntGeneral, 1225 [(set GPRC:$rT, (sube immAllOnes, GPRC:$rA))]>; 1226def SUBFZE : XOForm_3<31, 200, 0, (outs GPRC:$rT), (ins GPRC:$rA), 1227 "subfze $rT, $rA", IntGeneral, 1228 [(set GPRC:$rT, (sube 0, GPRC:$rA))]>; 1229} 1230} 1231 1232// A-Form instructions. Most of the instructions executed in the FPU are of 1233// this type. 1234// 1235let PPC970_Unit = 3 in { // FPU Operations. 1236let Uses = [RM] in { 1237 def FMADD : AForm_1<63, 29, 1238 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB), 1239 "fmadd $FRT, $FRA, $FRC, $FRB", FPFused, 1240 [(set F8RC:$FRT, (fadd (fmul F8RC:$FRA, F8RC:$FRC), 1241 F8RC:$FRB))]>, 1242 Requires<[FPContractions]>; 1243 def FMADDS : AForm_1<59, 29, 1244 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB), 1245 "fmadds $FRT, $FRA, $FRC, $FRB", FPGeneral, 1246 [(set F4RC:$FRT, (fadd (fmul F4RC:$FRA, F4RC:$FRC), 1247 F4RC:$FRB))]>, 1248 Requires<[FPContractions]>; 1249 def FMSUB : AForm_1<63, 28, 1250 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB), 1251 "fmsub $FRT, $FRA, $FRC, $FRB", FPFused, 1252 [(set F8RC:$FRT, (fsub (fmul F8RC:$FRA, F8RC:$FRC), 1253 F8RC:$FRB))]>, 1254 Requires<[FPContractions]>; 1255 def FMSUBS : AForm_1<59, 28, 1256 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB), 1257 "fmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral, 1258 [(set F4RC:$FRT, (fsub (fmul F4RC:$FRA, F4RC:$FRC), 1259 F4RC:$FRB))]>, 1260 Requires<[FPContractions]>; 1261 def FNMADD : AForm_1<63, 31, 1262 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB), 1263 "fnmadd $FRT, $FRA, $FRC, $FRB", FPFused, 1264 [(set F8RC:$FRT, (fneg (fadd (fmul F8RC:$FRA, F8RC:$FRC), 1265 F8RC:$FRB)))]>, 1266 Requires<[FPContractions]>; 1267 def FNMADDS : AForm_1<59, 31, 1268 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB), 1269 "fnmadds $FRT, $FRA, $FRC, $FRB", FPGeneral, 1270 [(set F4RC:$FRT, (fneg (fadd (fmul F4RC:$FRA, F4RC:$FRC), 1271 F4RC:$FRB)))]>, 1272 Requires<[FPContractions]>; 1273 def FNMSUB : AForm_1<63, 30, 1274 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB), 1275 "fnmsub $FRT, $FRA, $FRC, $FRB", FPFused, 1276 [(set F8RC:$FRT, (fneg (fsub (fmul F8RC:$FRA, F8RC:$FRC), 1277 F8RC:$FRB)))]>, 1278 Requires<[FPContractions]>; 1279 def FNMSUBS : AForm_1<59, 30, 1280 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB), 1281 "fnmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral, 1282 [(set F4RC:$FRT, (fneg (fsub (fmul F4RC:$FRA, F4RC:$FRC), 1283 F4RC:$FRB)))]>, 1284 Requires<[FPContractions]>; 1285} 1286// FSEL is artificially split into 4 and 8-byte forms for the result. To avoid 1287// having 4 of these, force the comparison to always be an 8-byte double (code 1288// should use an FMRSD if the input comparison value really wants to be a float) 1289// and 4/8 byte forms for the result and operand type.. 1290def FSELD : AForm_1<63, 23, 1291 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB), 1292 "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral, 1293 [(set F8RC:$FRT, (PPCfsel F8RC:$FRA,F8RC:$FRC,F8RC:$FRB))]>; 1294def FSELS : AForm_1<63, 23, 1295 (outs F4RC:$FRT), (ins F8RC:$FRA, F4RC:$FRC, F4RC:$FRB), 1296 "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral, 1297 [(set F4RC:$FRT, (PPCfsel F8RC:$FRA,F4RC:$FRC,F4RC:$FRB))]>; 1298let Uses = [RM] in { 1299 def FADD : AForm_2<63, 21, 1300 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB), 1301 "fadd $FRT, $FRA, $FRB", FPGeneral, 1302 [(set F8RC:$FRT, (fadd F8RC:$FRA, F8RC:$FRB))]>; 1303 def FADDS : AForm_2<59, 21, 1304 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB), 1305 "fadds $FRT, $FRA, $FRB", FPGeneral, 1306 [(set F4RC:$FRT, (fadd F4RC:$FRA, F4RC:$FRB))]>; 1307 def FDIV : AForm_2<63, 18, 1308 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB), 1309 "fdiv $FRT, $FRA, $FRB", FPDivD, 1310 [(set F8RC:$FRT, (fdiv F8RC:$FRA, F8RC:$FRB))]>; 1311 def FDIVS : AForm_2<59, 18, 1312 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB), 1313 "fdivs $FRT, $FRA, $FRB", FPDivS, 1314 [(set F4RC:$FRT, (fdiv F4RC:$FRA, F4RC:$FRB))]>; 1315 def FMUL : AForm_3<63, 25, 1316 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB), 1317 "fmul $FRT, $FRA, $FRB", FPFused, 1318 [(set F8RC:$FRT, (fmul F8RC:$FRA, F8RC:$FRB))]>; 1319 def FMULS : AForm_3<59, 25, 1320 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB), 1321 "fmuls $FRT, $FRA, $FRB", FPGeneral, 1322 [(set F4RC:$FRT, (fmul F4RC:$FRA, F4RC:$FRB))]>; 1323 def FSUB : AForm_2<63, 20, 1324 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB), 1325 "fsub $FRT, $FRA, $FRB", FPGeneral, 1326 [(set F8RC:$FRT, (fsub F8RC:$FRA, F8RC:$FRB))]>; 1327 def FSUBS : AForm_2<59, 20, 1328 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB), 1329 "fsubs $FRT, $FRA, $FRB", FPGeneral, 1330 [(set F4RC:$FRT, (fsub F4RC:$FRA, F4RC:$FRB))]>; 1331 } 1332} 1333 1334let PPC970_Unit = 1 in { // FXU Operations. 1335// M-Form instructions. rotate and mask instructions. 1336// 1337let isCommutable = 1 in { 1338// RLWIMI can be commuted if the rotate amount is zero. 1339def RLWIMI : MForm_2<20, 1340 (outs GPRC:$rA), (ins GPRC:$rSi, GPRC:$rS, u5imm:$SH, u5imm:$MB, 1341 u5imm:$ME), "rlwimi $rA, $rS, $SH, $MB, $ME", IntRotate, 1342 []>, PPC970_DGroup_Cracked, RegConstraint<"$rSi = $rA">, 1343 NoEncode<"$rSi">; 1344} 1345def RLWINM : MForm_2<21, 1346 (outs GPRC:$rA), (ins GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME), 1347 "rlwinm $rA, $rS, $SH, $MB, $ME", IntGeneral, 1348 []>; 1349def RLWINMo : MForm_2<21, 1350 (outs GPRC:$rA), (ins GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME), 1351 "rlwinm. $rA, $rS, $SH, $MB, $ME", IntGeneral, 1352 []>, isDOT, PPC970_DGroup_Cracked; 1353def RLWNM : MForm_2<23, 1354 (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB, u5imm:$MB, u5imm:$ME), 1355 "rlwnm $rA, $rS, $rB, $MB, $ME", IntGeneral, 1356 []>; 1357} 1358 1359 1360//===----------------------------------------------------------------------===// 1361// DWARF Pseudo Instructions 1362// 1363 1364def DWARF_LOC : Pseudo<(outs), (ins i32imm:$line, i32imm:$col, i32imm:$file), 1365 "${:comment} .loc $file, $line, $col", 1366 [(dwarf_loc (i32 imm:$line), (i32 imm:$col), 1367 (i32 imm:$file))]>; 1368 1369//===----------------------------------------------------------------------===// 1370// PowerPC Instruction Patterns 1371// 1372 1373// Arbitrary immediate support. Implement in terms of LIS/ORI. 1374def : Pat<(i32 imm:$imm), 1375 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>; 1376 1377// Implement the 'not' operation with the NOR instruction. 1378def NOT : Pat<(not GPRC:$in), 1379 (NOR GPRC:$in, GPRC:$in)>; 1380 1381// ADD an arbitrary immediate. 1382def : Pat<(add GPRC:$in, imm:$imm), 1383 (ADDIS (ADDI GPRC:$in, (LO16 imm:$imm)), (HA16 imm:$imm))>; 1384// OR an arbitrary immediate. 1385def : Pat<(or GPRC:$in, imm:$imm), 1386 (ORIS (ORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>; 1387// XOR an arbitrary immediate. 1388def : Pat<(xor GPRC:$in, imm:$imm), 1389 (XORIS (XORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>; 1390// SUBFIC 1391def : Pat<(sub immSExt16:$imm, GPRC:$in), 1392 (SUBFIC GPRC:$in, imm:$imm)>; 1393 1394// SHL/SRL 1395def : Pat<(shl GPRC:$in, (i32 imm:$imm)), 1396 (RLWINM GPRC:$in, imm:$imm, 0, (SHL32 imm:$imm))>; 1397def : Pat<(srl GPRC:$in, (i32 imm:$imm)), 1398 (RLWINM GPRC:$in, (SRL32 imm:$imm), imm:$imm, 31)>; 1399 1400// ROTL 1401def : Pat<(rotl GPRC:$in, GPRC:$sh), 1402 (RLWNM GPRC:$in, GPRC:$sh, 0, 31)>; 1403def : Pat<(rotl GPRC:$in, (i32 imm:$imm)), 1404 (RLWINM GPRC:$in, imm:$imm, 0, 31)>; 1405 1406// RLWNM 1407def : Pat<(and (rotl GPRC:$in, GPRC:$sh), maskimm32:$imm), 1408 (RLWNM GPRC:$in, GPRC:$sh, (MB maskimm32:$imm), (ME maskimm32:$imm))>; 1409 1410// Calls 1411def : Pat<(PPCcall_Darwin (i32 tglobaladdr:$dst)), 1412 (BL_Darwin tglobaladdr:$dst)>; 1413def : Pat<(PPCcall_Darwin (i32 texternalsym:$dst)), 1414 (BL_Darwin texternalsym:$dst)>; 1415def : Pat<(PPCcall_SVR4 (i32 tglobaladdr:$dst)), 1416 (BL_SVR4 tglobaladdr:$dst)>; 1417def : Pat<(PPCcall_SVR4 (i32 texternalsym:$dst)), 1418 (BL_SVR4 texternalsym:$dst)>; 1419 1420 1421def : Pat<(PPCtc_return (i32 tglobaladdr:$dst), imm:$imm), 1422 (TCRETURNdi tglobaladdr:$dst, imm:$imm)>; 1423 1424def : Pat<(PPCtc_return (i32 texternalsym:$dst), imm:$imm), 1425 (TCRETURNdi texternalsym:$dst, imm:$imm)>; 1426 1427def : Pat<(PPCtc_return CTRRC:$dst, imm:$imm), 1428 (TCRETURNri CTRRC:$dst, imm:$imm)>; 1429 1430 1431 1432// Hi and Lo for Darwin Global Addresses. 1433def : Pat<(PPChi tglobaladdr:$in, 0), (LIS tglobaladdr:$in)>; 1434def : Pat<(PPClo tglobaladdr:$in, 0), (LI tglobaladdr:$in)>; 1435def : Pat<(PPChi tconstpool:$in, 0), (LIS tconstpool:$in)>; 1436def : Pat<(PPClo tconstpool:$in, 0), (LI tconstpool:$in)>; 1437def : Pat<(PPChi tjumptable:$in, 0), (LIS tjumptable:$in)>; 1438def : Pat<(PPClo tjumptable:$in, 0), (LI tjumptable:$in)>; 1439def : Pat<(PPChi tblockaddress:$in, 0), (LIS tblockaddress:$in)>; 1440def : Pat<(PPClo tblockaddress:$in, 0), (LI tblockaddress:$in)>; 1441def : Pat<(add GPRC:$in, (PPChi tglobaladdr:$g, 0)), 1442 (ADDIS GPRC:$in, tglobaladdr:$g)>; 1443def : Pat<(add GPRC:$in, (PPChi tconstpool:$g, 0)), 1444 (ADDIS GPRC:$in, tconstpool:$g)>; 1445def : Pat<(add GPRC:$in, (PPChi tjumptable:$g, 0)), 1446 (ADDIS GPRC:$in, tjumptable:$g)>; 1447def : Pat<(add GPRC:$in, (PPChi tblockaddress:$g, 0)), 1448 (ADDIS GPRC:$in, tblockaddress:$g)>; 1449 1450// Fused negative multiply subtract, alternate pattern 1451def : Pat<(fsub F8RC:$B, (fmul F8RC:$A, F8RC:$C)), 1452 (FNMSUB F8RC:$A, F8RC:$C, F8RC:$B)>, 1453 Requires<[FPContractions]>; 1454def : Pat<(fsub F4RC:$B, (fmul F4RC:$A, F4RC:$C)), 1455 (FNMSUBS F4RC:$A, F4RC:$C, F4RC:$B)>, 1456 Requires<[FPContractions]>; 1457 1458// Standard shifts. These are represented separately from the real shifts above 1459// so that we can distinguish between shifts that allow 5-bit and 6-bit shift 1460// amounts. 1461def : Pat<(sra GPRC:$rS, GPRC:$rB), 1462 (SRAW GPRC:$rS, GPRC:$rB)>; 1463def : Pat<(srl GPRC:$rS, GPRC:$rB), 1464 (SRW GPRC:$rS, GPRC:$rB)>; 1465def : Pat<(shl GPRC:$rS, GPRC:$rB), 1466 (SLW GPRC:$rS, GPRC:$rB)>; 1467 1468def : Pat<(zextloadi1 iaddr:$src), 1469 (LBZ iaddr:$src)>; 1470def : Pat<(zextloadi1 xaddr:$src), 1471 (LBZX xaddr:$src)>; 1472def : Pat<(extloadi1 iaddr:$src), 1473 (LBZ iaddr:$src)>; 1474def : Pat<(extloadi1 xaddr:$src), 1475 (LBZX xaddr:$src)>; 1476def : Pat<(extloadi8 iaddr:$src), 1477 (LBZ iaddr:$src)>; 1478def : Pat<(extloadi8 xaddr:$src), 1479 (LBZX xaddr:$src)>; 1480def : Pat<(extloadi16 iaddr:$src), 1481 (LHZ iaddr:$src)>; 1482def : Pat<(extloadi16 xaddr:$src), 1483 (LHZX xaddr:$src)>; 1484def : Pat<(extloadf32 iaddr:$src), 1485 (FMRSD (LFS iaddr:$src))>; 1486def : Pat<(extloadf32 xaddr:$src), 1487 (FMRSD (LFSX xaddr:$src))>; 1488 1489// Memory barriers 1490def : Pat<(membarrier (i32 imm:$ll), 1491 (i32 imm:$ls), 1492 (i32 imm:$sl), 1493 (i32 imm:$ss), 1494 (i32 imm:$device)), 1495 (SYNC)>; 1496 1497include "PPCInstrAltivec.td" 1498include "PPCInstr64Bit.td" 1499