MipsSubtarget.h revision 234353 
1//===-- MipsSubtarget.h - Define Subtarget for the Mips ---------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file declares the Mips specific subclass of TargetSubtargetInfo.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef MIPSSUBTARGET_H
15#define MIPSSUBTARGET_H
16
17#include "llvm/Target/TargetSubtargetInfo.h"
18#include "llvm/MC/MCInstrItineraries.h"
19#include <string>
20
21#define GET_SUBTARGETINFO_HEADER
22#include "MipsGenSubtargetInfo.inc"
23
24namespace llvm {
25class StringRef;
26
27class MipsSubtarget : public MipsGenSubtargetInfo {
28  virtual void anchor();
29
30public:
31  // NOTE: O64 will not be supported.
32  enum MipsABIEnum {
33    UnknownABI, O32, N32, N64, EABI
34  };
35
36protected:
37
38  enum MipsArchEnum {
39    Mips32, Mips32r2, Mips64, Mips64r2
40  };
41
42  // Mips architecture version
43  MipsArchEnum MipsArchVersion;
44
45  // Mips supported ABIs
46  MipsABIEnum MipsABI;
47
48  // IsLittle - The target is Little Endian
49  bool IsLittle;
50
51  // IsSingleFloat - The target only supports single precision float
52  // point operations. This enable the target to use all 32 32-bit
53  // floating point registers instead of only using even ones.
54  bool IsSingleFloat;
55
56  // IsFP64bit - The target processor has 64-bit floating point registers.
57  bool IsFP64bit;
58
59  // IsFP64bit - General-purpose registers are 64 bits wide
60  bool IsGP64bit;
61
62  // HasVFPU - Processor has a vector floating point unit.
63  bool HasVFPU;
64
65  // isLinux - Target system is Linux. Is false we consider ELFOS for now.
66  bool IsLinux;
67
68  /// Features related to the presence of specific instructions.
69
70  // HasSEInReg - SEB and SEH (signext in register) instructions.
71  bool HasSEInReg;
72
73  // HasCondMov - Conditional mov (MOVZ, MOVN) instructions.
74  bool HasCondMov;
75
76  // HasMulDivAdd - Multiply add and sub (MADD, MADDu, MSUB, MSUBu)
77  // instructions.
78  bool HasMulDivAdd;
79
80  // HasMinMax - MIN and MAX instructions.
81  bool HasMinMax;
82
83  // HasSwap - Byte and half swap instructions.
84  bool HasSwap;
85
86  // HasBitCount - Count leading '1' and '0' bits.
87  bool HasBitCount;
88
89  InstrItineraryData InstrItins;
90
91public:
92  virtual bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
93                                     AntiDepBreakMode& Mode,
94                                     RegClassVector& CriticalPathRCs) const;
95
96  /// Only O32 and EABI supported right now.
97  bool isABI_EABI() const { return MipsABI == EABI; }
98  bool isABI_N64() const { return MipsABI == N64; }
99  bool isABI_N32() const { return MipsABI == N32; }
100  bool isABI_O32() const { return MipsABI == O32; }
101  unsigned getTargetABI() const { return MipsABI; }
102
103  /// This constructor initializes the data members to match that
104  /// of the specified triple.
105  MipsSubtarget(const std::string &TT, const std::string &CPU,
106                const std::string &FS, bool little);
107
108  /// ParseSubtargetFeatures - Parses features string setting specified
109  /// subtarget options.  Definition of function is auto generated by tblgen.
110  void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
111
112  bool hasMips32() const { return MipsArchVersion >= Mips32; }
113  bool hasMips32r2() const { return MipsArchVersion == Mips32r2 ||
114                                   MipsArchVersion == Mips64r2; }
115  bool hasMips64() const { return MipsArchVersion >= Mips64; }
116  bool hasMips64r2() const { return MipsArchVersion == Mips64r2; }
117
118  bool hasMips32r2Or64() const { return hasMips32r2() || hasMips64(); }
119
120  bool isLittle() const { return IsLittle; }
121  bool isFP64bit() const { return IsFP64bit; }
122  bool isGP64bit() const { return IsGP64bit; }
123  bool isGP32bit() const { return !IsGP64bit; }
124  bool isSingleFloat() const { return IsSingleFloat; }
125  bool isNotSingleFloat() const { return !IsSingleFloat; }
126  bool hasVFPU() const { return HasVFPU; }
127  bool isLinux() const { return IsLinux; }
128
129  /// Features related to the presence of specific instructions.
130  bool hasSEInReg()   const { return HasSEInReg; }
131  bool hasCondMov()   const { return HasCondMov; }
132  bool hasMulDivAdd() const { return HasMulDivAdd; }
133  bool hasMinMax()    const { return HasMinMax; }
134  bool hasSwap()      const { return HasSwap; }
135  bool hasBitCount()  const { return HasBitCount; }
136};
137} // End llvm namespace
138
139#endif
140