MipsRegisterInfo.td revision 243830
1191783Srmacklem//===-- MipsRegisterInfo.td - Mips Register defs -----------*- tablegen -*-===// 2191783Srmacklem// 3191783Srmacklem// The LLVM Compiler Infrastructure 4191783Srmacklem// 5191783Srmacklem// This file is distributed under the University of Illinois Open Source 6191783Srmacklem// License. See LICENSE.TXT for details. 7191783Srmacklem// 8191783Srmacklem//===----------------------------------------------------------------------===// 9191783Srmacklem 10191783Srmacklem//===----------------------------------------------------------------------===// 11191783Srmacklem// Declarations that describe the MIPS register file 12191783Srmacklem//===----------------------------------------------------------------------===// 13191783Srmacklemlet Namespace = "Mips" in { 14191783Srmacklemdef sub_fpeven : SubRegIndex; 15191783Srmacklemdef sub_fpodd : SubRegIndex; 16191783Srmacklemdef sub_32 : SubRegIndex; 17191783Srmacklemdef sub_lo : SubRegIndex; 18191783Srmacklemdef sub_hi : SubRegIndex; 19191783Srmacklem} 20191783Srmacklem 21191783Srmacklem// We have banks of 32 registers each. 22191783Srmacklemclass MipsReg<string n> : Register<n> { 23191783Srmacklem field bits<5> Num; 24191783Srmacklem let Namespace = "Mips"; 25191783Srmacklem} 26191783Srmacklem 27191783Srmacklemclass MipsRegWithSubRegs<string n, list<Register> subregs> 28191783Srmacklem : RegisterWithSubRegs<n, subregs> { 29191783Srmacklem field bits<5> Num; 30191783Srmacklem let Namespace = "Mips"; 31191783Srmacklem} 32191783Srmacklem 33191783Srmacklem// Mips CPU Registers 34191783Srmacklemclass MipsGPRReg<bits<5> num, string n> : MipsReg<n> { 35191783Srmacklem let Num = num; 36191783Srmacklem} 37191783Srmacklem 38191783Srmacklem// Mips 64-bit CPU Registers 39191783Srmacklemclass Mips64GPRReg<bits<5> num, string n, list<Register> subregs> 40191783Srmacklem : MipsRegWithSubRegs<n, subregs> { 41191783Srmacklem let Num = num; 42191783Srmacklem let SubRegIndices = [sub_32]; 43191783Srmacklem} 44191783Srmacklem 45191783Srmacklem// Mips 32-bit FPU Registers 46191783Srmacklemclass FPR<bits<5> num, string n> : MipsReg<n> { 47191783Srmacklem let Num = num; 48191783Srmacklem} 49191783Srmacklem 50191783Srmacklem// Mips 64-bit (aliased) FPU Registers 51191783Srmacklemclass AFPR<bits<5> num, string n, list<Register> subregs> 52194368Sbz : MipsRegWithSubRegs<n, subregs> { 53191783Srmacklem let Num = num; 54191783Srmacklem let SubRegIndices = [sub_fpeven, sub_fpodd]; 55191783Srmacklem let CoveredBySubRegs = 1; 56191783Srmacklem} 57191783Srmacklem 58191783Srmacklemclass AFPR64<bits<5> num, string n, list<Register> subregs> 59191783Srmacklem : MipsRegWithSubRegs<n, subregs> { 60191783Srmacklem let Num = num; 61191783Srmacklem let SubRegIndices = [sub_32]; 62191783Srmacklem} 63191783Srmacklem 64191783Srmacklem// Mips Hardware Registers 65191783Srmacklemclass HWR<bits<5> num, string n> : MipsReg<n> { 66191783Srmacklem let Num = num; 67191783Srmacklem} 68191783Srmacklem 69191783Srmacklem//===----------------------------------------------------------------------===// 70191783Srmacklem// Registers 71191783Srmacklem//===----------------------------------------------------------------------===// 72191783Srmacklem 73223280Srmacklemlet Namespace = "Mips" in { 74191783Srmacklem // General Purpose Registers 75191783Srmacklem def ZERO : MipsGPRReg< 0, "zero">, DwarfRegNum<[0]>; 76191783Srmacklem def AT : MipsGPRReg< 1, "1">, DwarfRegNum<[1]>; 77191783Srmacklem def V0 : MipsGPRReg< 2, "2">, DwarfRegNum<[2]>; 78191783Srmacklem def V1 : MipsGPRReg< 3, "3">, DwarfRegNum<[3]>; 79210455Srmacklem def A0 : MipsGPRReg< 4, "4">, DwarfRegNum<[4]>; 80210455Srmacklem def A1 : MipsGPRReg< 5, "5">, DwarfRegNum<[5]>; 81223280Srmacklem def A2 : MipsGPRReg< 6, "6">, DwarfRegNum<[6]>; 82223280Srmacklem def A3 : MipsGPRReg< 7, "7">, DwarfRegNum<[7]>; 83223280Srmacklem def T0 : MipsGPRReg< 8, "8">, DwarfRegNum<[8]>; 84223280Srmacklem def T1 : MipsGPRReg< 9, "9">, DwarfRegNum<[9]>; 85223280Srmacklem def T2 : MipsGPRReg< 10, "10">, DwarfRegNum<[10]>; 86223280Srmacklem def T3 : MipsGPRReg< 11, "11">, DwarfRegNum<[11]>; 87223280Srmacklem def T4 : MipsGPRReg< 12, "12">, DwarfRegNum<[12]>; 88223280Srmacklem def T5 : MipsGPRReg< 13, "13">, DwarfRegNum<[13]>; 89223280Srmacklem def T6 : MipsGPRReg< 14, "14">, DwarfRegNum<[14]>; 90223280Srmacklem def T7 : MipsGPRReg< 15, "15">, DwarfRegNum<[15]>; 91223280Srmacklem def S0 : MipsGPRReg< 16, "16">, DwarfRegNum<[16]>; 92223280Srmacklem def S1 : MipsGPRReg< 17, "17">, DwarfRegNum<[17]>; 93223280Srmacklem def S2 : MipsGPRReg< 18, "18">, DwarfRegNum<[18]>; 94223280Srmacklem def S3 : MipsGPRReg< 19, "19">, DwarfRegNum<[19]>; 95223280Srmacklem def S4 : MipsGPRReg< 20, "20">, DwarfRegNum<[20]>; 96223280Srmacklem def S5 : MipsGPRReg< 21, "21">, DwarfRegNum<[21]>; 97223280Srmacklem def S6 : MipsGPRReg< 22, "22">, DwarfRegNum<[22]>; 98223280Srmacklem def S7 : MipsGPRReg< 23, "23">, DwarfRegNum<[23]>; 99191783Srmacklem def T8 : MipsGPRReg< 24, "24">, DwarfRegNum<[24]>; 100191783Srmacklem def T9 : MipsGPRReg< 25, "25">, DwarfRegNum<[25]>; 101191783Srmacklem def K0 : MipsGPRReg< 26, "26">, DwarfRegNum<[26]>; 102191783Srmacklem def K1 : MipsGPRReg< 27, "27">, DwarfRegNum<[27]>; 103191783Srmacklem def GP : MipsGPRReg< 28, "gp">, DwarfRegNum<[28]>; 104220611Srmacklem def SP : MipsGPRReg< 29, "sp">, DwarfRegNum<[29]>; 105244042Srmacklem def FP : MipsGPRReg< 30, "fp">, DwarfRegNum<[30]>; 106191783Srmacklem def RA : MipsGPRReg< 31, "ra">, DwarfRegNum<[31]>; 107191783Srmacklem 108191783Srmacklem // General Purpose 64-bit Registers 109191783Srmacklem def ZERO_64 : Mips64GPRReg< 0, "zero", [ZERO]>, DwarfRegNum<[0]>; 110191783Srmacklem def AT_64 : Mips64GPRReg< 1, "1", [AT]>, DwarfRegNum<[1]>; 111191783Srmacklem def V0_64 : Mips64GPRReg< 2, "2", [V0]>, DwarfRegNum<[2]>; 112191783Srmacklem def V1_64 : Mips64GPRReg< 3, "3", [V1]>, DwarfRegNum<[3]>; 113191783Srmacklem def A0_64 : Mips64GPRReg< 4, "4", [A0]>, DwarfRegNum<[4]>; 114191783Srmacklem def A1_64 : Mips64GPRReg< 5, "5", [A1]>, DwarfRegNum<[5]>; 115191783Srmacklem def A2_64 : Mips64GPRReg< 6, "6", [A2]>, DwarfRegNum<[6]>; 116191783Srmacklem def A3_64 : Mips64GPRReg< 7, "7", [A3]>, DwarfRegNum<[7]>; 117191783Srmacklem def T0_64 : Mips64GPRReg< 8, "8", [T0]>, DwarfRegNum<[8]>; 118191783Srmacklem def T1_64 : Mips64GPRReg< 9, "9", [T1]>, DwarfRegNum<[9]>; 119191783Srmacklem def T2_64 : Mips64GPRReg< 10, "10", [T2]>, DwarfRegNum<[10]>; 120191783Srmacklem def T3_64 : Mips64GPRReg< 11, "11", [T3]>, DwarfRegNum<[11]>; 121191783Srmacklem def T4_64 : Mips64GPRReg< 12, "12", [T4]>, DwarfRegNum<[12]>; 122191783Srmacklem def T5_64 : Mips64GPRReg< 13, "13", [T5]>, DwarfRegNum<[13]>; 123191783Srmacklem def T6_64 : Mips64GPRReg< 14, "14", [T6]>, DwarfRegNum<[14]>; 124191783Srmacklem def T7_64 : Mips64GPRReg< 15, "15", [T7]>, DwarfRegNum<[15]>; 125191783Srmacklem def S0_64 : Mips64GPRReg< 16, "16", [S0]>, DwarfRegNum<[16]>; 126220611Srmacklem def S1_64 : Mips64GPRReg< 17, "17", [S1]>, DwarfRegNum<[17]>; 127191783Srmacklem def S2_64 : Mips64GPRReg< 18, "18", [S2]>, DwarfRegNum<[18]>; 128191783Srmacklem def S3_64 : Mips64GPRReg< 19, "19", [S3]>, DwarfRegNum<[19]>; 129191783Srmacklem def S4_64 : Mips64GPRReg< 20, "20", [S4]>, DwarfRegNum<[20]>; 130191783Srmacklem def S5_64 : Mips64GPRReg< 21, "21", [S5]>, DwarfRegNum<[21]>; 131191783Srmacklem def S6_64 : Mips64GPRReg< 22, "22", [S6]>, DwarfRegNum<[22]>; 132191783Srmacklem def S7_64 : Mips64GPRReg< 23, "23", [S7]>, DwarfRegNum<[23]>; 133191783Srmacklem def T8_64 : Mips64GPRReg< 24, "24", [T8]>, DwarfRegNum<[24]>; 134191783Srmacklem def T9_64 : Mips64GPRReg< 25, "25", [T9]>, DwarfRegNum<[25]>; 135191783Srmacklem def K0_64 : Mips64GPRReg< 26, "26", [K0]>, DwarfRegNum<[26]>; 136191783Srmacklem def K1_64 : Mips64GPRReg< 27, "27", [K1]>, DwarfRegNum<[27]>; 137191783Srmacklem def GP_64 : Mips64GPRReg< 28, "gp", [GP]>, DwarfRegNum<[28]>; 138191783Srmacklem def SP_64 : Mips64GPRReg< 29, "sp", [SP]>, DwarfRegNum<[29]>; 139191783Srmacklem def FP_64 : Mips64GPRReg< 30, "fp", [FP]>, DwarfRegNum<[30]>; 140191783Srmacklem def RA_64 : Mips64GPRReg< 31, "ra", [RA]>, DwarfRegNum<[31]>; 141191783Srmacklem 142191783Srmacklem /// Mips Single point precision FPU Registers 143191783Srmacklem def F0 : FPR< 0, "f0">, DwarfRegNum<[32]>; 144191783Srmacklem def F1 : FPR< 1, "f1">, DwarfRegNum<[33]>; 145191783Srmacklem def F2 : FPR< 2, "f2">, DwarfRegNum<[34]>; 146191783Srmacklem def F3 : FPR< 3, "f3">, DwarfRegNum<[35]>; 147191783Srmacklem def F4 : FPR< 4, "f4">, DwarfRegNum<[36]>; 148191783Srmacklem def F5 : FPR< 5, "f5">, DwarfRegNum<[37]>; 149191783Srmacklem def F6 : FPR< 6, "f6">, DwarfRegNum<[38]>; 150191783Srmacklem def F7 : FPR< 7, "f7">, DwarfRegNum<[39]>; 151191783Srmacklem def F8 : FPR< 8, "f8">, DwarfRegNum<[40]>; 152191783Srmacklem def F9 : FPR< 9, "f9">, DwarfRegNum<[41]>; 153191783Srmacklem def F10 : FPR<10, "f10">, DwarfRegNum<[42]>; 154191783Srmacklem def F11 : FPR<11, "f11">, DwarfRegNum<[43]>; 155191783Srmacklem def F12 : FPR<12, "f12">, DwarfRegNum<[44]>; 156191783Srmacklem def F13 : FPR<13, "f13">, DwarfRegNum<[45]>; 157191783Srmacklem def F14 : FPR<14, "f14">, DwarfRegNum<[46]>; 158191783Srmacklem def F15 : FPR<15, "f15">, DwarfRegNum<[47]>; 159191783Srmacklem def F16 : FPR<16, "f16">, DwarfRegNum<[48]>; 160191783Srmacklem def F17 : FPR<17, "f17">, DwarfRegNum<[49]>; 161191783Srmacklem def F18 : FPR<18, "f18">, DwarfRegNum<[50]>; 162191783Srmacklem def F19 : FPR<19, "f19">, DwarfRegNum<[51]>; 163191783Srmacklem def F20 : FPR<20, "f20">, DwarfRegNum<[52]>; 164191783Srmacklem def F21 : FPR<21, "f21">, DwarfRegNum<[53]>; 165191783Srmacklem def F22 : FPR<22, "f22">, DwarfRegNum<[54]>; 166191783Srmacklem def F23 : FPR<23, "f23">, DwarfRegNum<[55]>; 167191783Srmacklem def F24 : FPR<24, "f24">, DwarfRegNum<[56]>; 168191783Srmacklem def F25 : FPR<25, "f25">, DwarfRegNum<[57]>; 169191783Srmacklem def F26 : FPR<26, "f26">, DwarfRegNum<[58]>; 170191783Srmacklem def F27 : FPR<27, "f27">, DwarfRegNum<[59]>; 171191783Srmacklem def F28 : FPR<28, "f28">, DwarfRegNum<[60]>; 172191783Srmacklem def F29 : FPR<29, "f29">, DwarfRegNum<[61]>; 173220611Srmacklem def F30 : FPR<30, "f30">, DwarfRegNum<[62]>; 174191783Srmacklem def F31 : FPR<31, "f31">, DwarfRegNum<[63]>; 175191783Srmacklem 176191783Srmacklem /// Mips Double point precision FPU Registers (aliased 177191783Srmacklem /// with the single precision to hold 64 bit values) 178191783Srmacklem def D0 : AFPR< 0, "f0", [F0, F1]>; 179191783Srmacklem def D1 : AFPR< 2, "f2", [F2, F3]>; 180191783Srmacklem def D2 : AFPR< 4, "f4", [F4, F5]>; 181191783Srmacklem def D3 : AFPR< 6, "f6", [F6, F7]>; 182191783Srmacklem def D4 : AFPR< 8, "f8", [F8, F9]>; 183191783Srmacklem def D5 : AFPR<10, "f10", [F10, F11]>; 184191783Srmacklem def D6 : AFPR<12, "f12", [F12, F13]>; 185191783Srmacklem def D7 : AFPR<14, "f14", [F14, F15]>; 186191783Srmacklem def D8 : AFPR<16, "f16", [F16, F17]>; 187191783Srmacklem def D9 : AFPR<18, "f18", [F18, F19]>; 188191783Srmacklem def D10 : AFPR<20, "f20", [F20, F21]>; 189191783Srmacklem def D11 : AFPR<22, "f22", [F22, F23]>; 190191783Srmacklem def D12 : AFPR<24, "f24", [F24, F25]>; 191191783Srmacklem def D13 : AFPR<26, "f26", [F26, F27]>; 192191783Srmacklem def D14 : AFPR<28, "f28", [F28, F29]>; 193191783Srmacklem def D15 : AFPR<30, "f30", [F30, F31]>; 194191783Srmacklem 195191783Srmacklem /// Mips Double point precision FPU Registers in MFP64 mode. 196191783Srmacklem def D0_64 : AFPR64<0, "f0", [F0]>, DwarfRegNum<[32]>; 197191783Srmacklem def D1_64 : AFPR64<1, "f1", [F1]>, DwarfRegNum<[33]>; 198191783Srmacklem def D2_64 : AFPR64<2, "f2", [F2]>, DwarfRegNum<[34]>; 199191783Srmacklem def D3_64 : AFPR64<3, "f3", [F3]>, DwarfRegNum<[35]>; 200191783Srmacklem def D4_64 : AFPR64<4, "f4", [F4]>, DwarfRegNum<[36]>; 201191783Srmacklem def D5_64 : AFPR64<5, "f5", [F5]>, DwarfRegNum<[37]>; 202191783Srmacklem def D6_64 : AFPR64<6, "f6", [F6]>, DwarfRegNum<[38]>; 203191783Srmacklem def D7_64 : AFPR64<7, "f7", [F7]>, DwarfRegNum<[39]>; 204191783Srmacklem def D8_64 : AFPR64<8, "f8", [F8]>, DwarfRegNum<[40]>; 205191783Srmacklem def D9_64 : AFPR64<9, "f9", [F9]>, DwarfRegNum<[41]>; 206191783Srmacklem def D10_64 : AFPR64<10, "f10", [F10]>, DwarfRegNum<[42]>; 207191783Srmacklem def D11_64 : AFPR64<11, "f11", [F11]>, DwarfRegNum<[43]>; 208191783Srmacklem def D12_64 : AFPR64<12, "f12", [F12]>, DwarfRegNum<[44]>; 209191783Srmacklem def D13_64 : AFPR64<13, "f13", [F13]>, DwarfRegNum<[45]>; 210191783Srmacklem def D14_64 : AFPR64<14, "f14", [F14]>, DwarfRegNum<[46]>; 211191783Srmacklem def D15_64 : AFPR64<15, "f15", [F15]>, DwarfRegNum<[47]>; 212191783Srmacklem def D16_64 : AFPR64<16, "f16", [F16]>, DwarfRegNum<[48]>; 213191783Srmacklem def D17_64 : AFPR64<17, "f17", [F17]>, DwarfRegNum<[49]>; 214191783Srmacklem def D18_64 : AFPR64<18, "f18", [F18]>, DwarfRegNum<[50]>; 215191783Srmacklem def D19_64 : AFPR64<19, "f19", [F19]>, DwarfRegNum<[51]>; 216191783Srmacklem def D20_64 : AFPR64<20, "f20", [F20]>, DwarfRegNum<[52]>; 217191783Srmacklem def D21_64 : AFPR64<21, "f21", [F21]>, DwarfRegNum<[53]>; 218191783Srmacklem def D22_64 : AFPR64<22, "f22", [F22]>, DwarfRegNum<[54]>; 219221973Srmacklem def D23_64 : AFPR64<23, "f23", [F23]>, DwarfRegNum<[55]>; 220191783Srmacklem def D24_64 : AFPR64<24, "f24", [F24]>, DwarfRegNum<[56]>; 221191783Srmacklem def D25_64 : AFPR64<25, "f25", [F25]>, DwarfRegNum<[57]>; 222221973Srmacklem def D26_64 : AFPR64<26, "f26", [F26]>, DwarfRegNum<[58]>; 223191783Srmacklem def D27_64 : AFPR64<27, "f27", [F27]>, DwarfRegNum<[59]>; 224191783Srmacklem def D28_64 : AFPR64<28, "f28", [F28]>, DwarfRegNum<[60]>; 225191783Srmacklem def D29_64 : AFPR64<29, "f29", [F29]>, DwarfRegNum<[61]>; 226221973Srmacklem def D30_64 : AFPR64<30, "f30", [F30]>, DwarfRegNum<[62]>; 227191783Srmacklem def D31_64 : AFPR64<31, "f31", [F31]>, DwarfRegNum<[63]>; 228191783Srmacklem 229191783Srmacklem // Hi/Lo registers 230191783Srmacklem def HI : Register<"hi">, DwarfRegNum<[64]>; 231221973Srmacklem def LO : Register<"lo">, DwarfRegNum<[65]>; 232191783Srmacklem 233191783Srmacklem let SubRegIndices = [sub_32] in { 234191783Srmacklem def HI64 : RegisterWithSubRegs<"hi", [HI]>; 235221973Srmacklem def LO64 : RegisterWithSubRegs<"lo", [LO]>; 236191783Srmacklem } 237191783Srmacklem 238191783Srmacklem // Status flags register 239221973Srmacklem def FCR31 : Register<"31">; 240191783Srmacklem 241191783Srmacklem // fcc0 register 242233101Skib def FCC0 : Register<"fcc0">; 243233101Skib 244233101Skib // PC register 245233101Skib def PC : Register<"pc">; 246191783Srmacklem 247191783Srmacklem // Hardware register $29 248191783Srmacklem def HWR29 : Register<"29">; 249191783Srmacklem def HWR29_64 : Register<"29">; 250191783Srmacklem 251191783Srmacklem // Accum registers 252191783Srmacklem let SubRegIndices = [sub_lo, sub_hi] in 253191783Srmacklem def AC0 : RegisterWithSubRegs<"ac0", [LO, HI]>; 254191783Srmacklem def AC1 : Register<"ac1">; 255191783Srmacklem def AC2 : Register<"ac2">; 256191783Srmacklem def AC3 : Register<"ac3">; 257191783Srmacklem 258221973Srmacklem def DSPCtrl : Register<"dspctrl">; 259191783Srmacklem} 260191783Srmacklem 261191783Srmacklem//===----------------------------------------------------------------------===// 262221973Srmacklem// Register Classes 263191783Srmacklem//===----------------------------------------------------------------------===// 264191783Srmacklem 265221973Srmacklemclass CPURegsClass<list<ValueType> regTypes> : 266191783Srmacklem RegisterClass<"Mips", regTypes, 32, (add 267191783Srmacklem // Reserved 268191783Srmacklem ZERO, AT, 269191783Srmacklem // Return Values and Arguments 270191783Srmacklem V0, V1, A0, A1, A2, A3, 271191783Srmacklem // Not preserved across procedure calls 272191783Srmacklem T0, T1, T2, T3, T4, T5, T6, T7, 273191783Srmacklem // Callee save 274191783Srmacklem S0, S1, S2, S3, S4, S5, S6, S7, 275191783Srmacklem // Not preserved across procedure calls 276191783Srmacklem T8, T9, 277191783Srmacklem // Reserved 278191783Srmacklem K0, K1, GP, SP, FP, RA)>; 279191783Srmacklem 280191783Srmacklemdef CPURegs : CPURegsClass<[i32]>; 281191783Srmacklemdef DSPRegs : CPURegsClass<[v4i8, v2i16]>; 282191783Srmacklem 283191783Srmacklemdef CPU64Regs : RegisterClass<"Mips", [i64], 64, (add 284191783Srmacklem// Reserved 285191783Srmacklem ZERO_64, AT_64, 286191783Srmacklem // Return Values and Arguments 287191783Srmacklem V0_64, V1_64, A0_64, A1_64, A2_64, A3_64, 288191783Srmacklem // Not preserved across procedure calls 289191783Srmacklem T0_64, T1_64, T2_64, T3_64, T4_64, T5_64, T6_64, T7_64, 290191783Srmacklem // Callee save 291191783Srmacklem S0_64, S1_64, S2_64, S3_64, S4_64, S5_64, S6_64, S7_64, 292191783Srmacklem // Not preserved across procedure calls 293191783Srmacklem T8_64, T9_64, 294191783Srmacklem // Reserved 295191783Srmacklem K0_64, K1_64, GP_64, SP_64, FP_64, RA_64)>; 296191783Srmacklem 297191783Srmacklemdef CPU16Regs : RegisterClass<"Mips", [i32], 32, (add 298191783Srmacklem // Return Values and Arguments 299191783Srmacklem V0, V1, A0, A1, A2, A3, 300191783Srmacklem // Callee save 301191783Srmacklem S0, S1)>; 302191783Srmacklem 303191783Srmacklemdef CPURAReg : RegisterClass<"Mips", [i32], 32, (add RA)>; 304191783Srmacklem 305191783Srmacklemdef CPUSPReg : RegisterClass<"Mips", [i32], 32, (add SP)>; 306191783Srmacklem 307191783Srmacklem// 64bit fp: 308191783Srmacklem// * FGR64 - 32 64-bit registers 309191783Srmacklem// * AFGR64 - 16 32-bit even registers (32-bit FP Mode) 310191783Srmacklem// 311191783Srmacklem// 32bit fp: 312191783Srmacklem// * FGR32 - 16 32-bit even registers 313191783Srmacklem// * FGR32 - 32 32-bit registers (single float only mode) 314191783Srmacklemdef FGR32 : RegisterClass<"Mips", [f32], 32, (sequence "F%u", 0, 31)>; 315191783Srmacklem 316191783Srmacklemdef AFGR64 : RegisterClass<"Mips", [f64], 64, (add 317191783Srmacklem // Return Values and Arguments 318191783Srmacklem D0, D1, 319191783Srmacklem // Not preserved across procedure calls 320191783Srmacklem D2, D3, D4, D5, 321191783Srmacklem // Return Values and Arguments 322191783Srmacklem D6, D7, 323223280Srmacklem // Not preserved across procedure calls 324191783Srmacklem D8, D9, 325191783Srmacklem // Callee save 326191783Srmacklem D10, D11, D12, D13, D14, D15)>; 327223280Srmacklem 328223280Srmacklemdef FGR64 : RegisterClass<"Mips", [f64], 64, (sequence "D%u_64", 0, 31)>; 329223280Srmacklem 330223280Srmacklem// Condition Register for floating point operations 331223280Srmacklemdef CCR : RegisterClass<"Mips", [i32], 32, (add FCR31,FCC0)>; 332191783Srmacklem 333191783Srmacklem// Hi/Lo Registers 334191783Srmacklemdef HILO : RegisterClass<"Mips", [i32], 32, (add HI, LO)>; 335191783Srmacklemdef HILO64 : RegisterClass<"Mips", [i64], 64, (add HI64, LO64)>; 336191783Srmacklem 337191783Srmacklem// Hardware registers 338191783Srmacklemdef HWRegs : RegisterClass<"Mips", [i32], 32, (add HWR29)>; 339191783Srmacklemdef HWRegs64 : RegisterClass<"Mips", [i64], 32, (add HWR29_64)>; 340191783Srmacklem 341191783Srmacklem// Accumulator Registers 342191783Srmacklemdef ACRegs : RegisterClass<"Mips", [i64], 64, (sequence "AC%u", 0, 3)>; 343191783Srmacklem