MipsRegisterInfo.td revision 239462
1234353Sdim//===-- MipsRegisterInfo.td - Mips Register defs -----------*- tablegen -*-===// 2193323Sed// 3193323Sed// The LLVM Compiler Infrastructure 4193323Sed// 5193323Sed// This file is distributed under the University of Illinois Open Source 6193323Sed// License. See LICENSE.TXT for details. 7193323Sed// 8193323Sed//===----------------------------------------------------------------------===// 9193323Sed 10193323Sed//===----------------------------------------------------------------------===// 11193323Sed// Declarations that describe the MIPS register file 12193323Sed//===----------------------------------------------------------------------===// 13226633Sdimlet Namespace = "Mips" in { 14226633Sdimdef sub_fpeven : SubRegIndex; 15226633Sdimdef sub_fpodd : SubRegIndex; 16226633Sdimdef sub_32 : SubRegIndex; 17226633Sdim} 18193323Sed 19193323Sed// We have banks of 32 registers each. 20193323Sedclass MipsReg<string n> : Register<n> { 21193323Sed field bits<5> Num; 22193323Sed let Namespace = "Mips"; 23193323Sed} 24193323Sed 25221345Sdimclass MipsRegWithSubRegs<string n, list<Register> subregs> 26199511Srdivacky : RegisterWithSubRegs<n, subregs> { 27199511Srdivacky field bits<5> Num; 28199511Srdivacky let Namespace = "Mips"; 29199511Srdivacky} 30199511Srdivacky 31193323Sed// Mips CPU Registers 32193323Sedclass MipsGPRReg<bits<5> num, string n> : MipsReg<n> { 33193323Sed let Num = num; 34193323Sed} 35193323Sed 36226633Sdim// Mips 64-bit CPU Registers 37226633Sdimclass Mips64GPRReg<bits<5> num, string n, list<Register> subregs> 38226633Sdim : MipsRegWithSubRegs<n, subregs> { 39226633Sdim let Num = num; 40226633Sdim let SubRegIndices = [sub_32]; 41226633Sdim} 42226633Sdim 43193323Sed// Mips 32-bit FPU Registers 44193323Sedclass FPR<bits<5> num, string n> : MipsReg<n> { 45193323Sed let Num = num; 46193323Sed} 47193323Sed 48193323Sed// Mips 64-bit (aliased) FPU Registers 49208599Srdivackyclass AFPR<bits<5> num, string n, list<Register> subregs> 50199511Srdivacky : MipsRegWithSubRegs<n, subregs> { 51193323Sed let Num = num; 52208599Srdivacky let SubRegIndices = [sub_fpeven, sub_fpodd]; 53234353Sdim let CoveredBySubRegs = 1; 54193323Sed} 55193323Sed 56226633Sdimclass AFPR64<bits<5> num, string n, list<Register> subregs> 57226633Sdim : MipsRegWithSubRegs<n, subregs> { 58226633Sdim let Num = num; 59226633Sdim let SubRegIndices = [sub_32]; 60226633Sdim} 61226633Sdim 62223017Sdim// Mips Hardware Registers 63223017Sdimclass HWR<bits<5> num, string n> : MipsReg<n> { 64223017Sdim let Num = num; 65223017Sdim} 66223017Sdim 67193323Sed//===----------------------------------------------------------------------===// 68193323Sed// Registers 69193323Sed//===----------------------------------------------------------------------===// 70193323Sed 71193323Sedlet Namespace = "Mips" in { 72193323Sed // General Purpose Registers 73239462Sdim def ZERO : MipsGPRReg< 0, "zero">, DwarfRegNum<[0]>; 74239462Sdim def AT : MipsGPRReg< 1, "at">, DwarfRegNum<[1]>; 75193323Sed def V0 : MipsGPRReg< 2, "2">, DwarfRegNum<[2]>; 76193323Sed def V1 : MipsGPRReg< 3, "3">, DwarfRegNum<[3]>; 77223017Sdim def A0 : MipsGPRReg< 4, "4">, DwarfRegNum<[4]>; 78193323Sed def A1 : MipsGPRReg< 5, "5">, DwarfRegNum<[5]>; 79193323Sed def A2 : MipsGPRReg< 6, "6">, DwarfRegNum<[6]>; 80193323Sed def A3 : MipsGPRReg< 7, "7">, DwarfRegNum<[7]>; 81193323Sed def T0 : MipsGPRReg< 8, "8">, DwarfRegNum<[8]>; 82193323Sed def T1 : MipsGPRReg< 9, "9">, DwarfRegNum<[9]>; 83193323Sed def T2 : MipsGPRReg< 10, "10">, DwarfRegNum<[10]>; 84193323Sed def T3 : MipsGPRReg< 11, "11">, DwarfRegNum<[11]>; 85193323Sed def T4 : MipsGPRReg< 12, "12">, DwarfRegNum<[12]>; 86193323Sed def T5 : MipsGPRReg< 13, "13">, DwarfRegNum<[13]>; 87193323Sed def T6 : MipsGPRReg< 14, "14">, DwarfRegNum<[14]>; 88193323Sed def T7 : MipsGPRReg< 15, "15">, DwarfRegNum<[15]>; 89193323Sed def S0 : MipsGPRReg< 16, "16">, DwarfRegNum<[16]>; 90193323Sed def S1 : MipsGPRReg< 17, "17">, DwarfRegNum<[17]>; 91193323Sed def S2 : MipsGPRReg< 18, "18">, DwarfRegNum<[18]>; 92193323Sed def S3 : MipsGPRReg< 19, "19">, DwarfRegNum<[19]>; 93193323Sed def S4 : MipsGPRReg< 20, "20">, DwarfRegNum<[20]>; 94193323Sed def S5 : MipsGPRReg< 21, "21">, DwarfRegNum<[21]>; 95193323Sed def S6 : MipsGPRReg< 22, "22">, DwarfRegNum<[22]>; 96193323Sed def S7 : MipsGPRReg< 23, "23">, DwarfRegNum<[23]>; 97193323Sed def T8 : MipsGPRReg< 24, "24">, DwarfRegNum<[24]>; 98193323Sed def T9 : MipsGPRReg< 25, "25">, DwarfRegNum<[25]>; 99193323Sed def K0 : MipsGPRReg< 26, "26">, DwarfRegNum<[26]>; 100193323Sed def K1 : MipsGPRReg< 27, "27">, DwarfRegNum<[27]>; 101239462Sdim def GP : MipsGPRReg< 28, "gp">, DwarfRegNum<[28]>; 102239462Sdim def SP : MipsGPRReg< 29, "sp">, DwarfRegNum<[29]>; 103239462Sdim def FP : MipsGPRReg< 30, "fp">, DwarfRegNum<[30]>; 104239462Sdim def RA : MipsGPRReg< 31, "ra">, DwarfRegNum<[31]>; 105221345Sdim 106226633Sdim // General Purpose 64-bit Registers 107239462Sdim def ZERO_64 : Mips64GPRReg< 0, "zero", [ZERO]>, DwarfRegNum<[0]>; 108239462Sdim def AT_64 : Mips64GPRReg< 1, "at", [AT]>, DwarfRegNum<[1]>; 109234353Sdim def V0_64 : Mips64GPRReg< 2, "2", [V0]>, DwarfRegNum<[2]>; 110234353Sdim def V1_64 : Mips64GPRReg< 3, "3", [V1]>, DwarfRegNum<[3]>; 111234353Sdim def A0_64 : Mips64GPRReg< 4, "4", [A0]>, DwarfRegNum<[4]>; 112234353Sdim def A1_64 : Mips64GPRReg< 5, "5", [A1]>, DwarfRegNum<[5]>; 113234353Sdim def A2_64 : Mips64GPRReg< 6, "6", [A2]>, DwarfRegNum<[6]>; 114234353Sdim def A3_64 : Mips64GPRReg< 7, "7", [A3]>, DwarfRegNum<[7]>; 115234353Sdim def T0_64 : Mips64GPRReg< 8, "8", [T0]>, DwarfRegNum<[8]>; 116234353Sdim def T1_64 : Mips64GPRReg< 9, "9", [T1]>, DwarfRegNum<[9]>; 117234353Sdim def T2_64 : Mips64GPRReg< 10, "10", [T2]>, DwarfRegNum<[10]>; 118234353Sdim def T3_64 : Mips64GPRReg< 11, "11", [T3]>, DwarfRegNum<[11]>; 119234353Sdim def T4_64 : Mips64GPRReg< 12, "12", [T4]>, DwarfRegNum<[12]>; 120234353Sdim def T5_64 : Mips64GPRReg< 13, "13", [T5]>, DwarfRegNum<[13]>; 121234353Sdim def T6_64 : Mips64GPRReg< 14, "14", [T6]>, DwarfRegNum<[14]>; 122234353Sdim def T7_64 : Mips64GPRReg< 15, "15", [T7]>, DwarfRegNum<[15]>; 123234353Sdim def S0_64 : Mips64GPRReg< 16, "16", [S0]>, DwarfRegNum<[16]>; 124234353Sdim def S1_64 : Mips64GPRReg< 17, "17", [S1]>, DwarfRegNum<[17]>; 125234353Sdim def S2_64 : Mips64GPRReg< 18, "18", [S2]>, DwarfRegNum<[18]>; 126234353Sdim def S3_64 : Mips64GPRReg< 19, "19", [S3]>, DwarfRegNum<[19]>; 127234353Sdim def S4_64 : Mips64GPRReg< 20, "20", [S4]>, DwarfRegNum<[20]>; 128234353Sdim def S5_64 : Mips64GPRReg< 21, "21", [S5]>, DwarfRegNum<[21]>; 129234353Sdim def S6_64 : Mips64GPRReg< 22, "22", [S6]>, DwarfRegNum<[22]>; 130234353Sdim def S7_64 : Mips64GPRReg< 23, "23", [S7]>, DwarfRegNum<[23]>; 131234353Sdim def T8_64 : Mips64GPRReg< 24, "24", [T8]>, DwarfRegNum<[24]>; 132234353Sdim def T9_64 : Mips64GPRReg< 25, "25", [T9]>, DwarfRegNum<[25]>; 133234353Sdim def K0_64 : Mips64GPRReg< 26, "26", [K0]>, DwarfRegNum<[26]>; 134234353Sdim def K1_64 : Mips64GPRReg< 27, "27", [K1]>, DwarfRegNum<[27]>; 135239462Sdim def GP_64 : Mips64GPRReg< 28, "gp", [GP]>, DwarfRegNum<[28]>; 136239462Sdim def SP_64 : Mips64GPRReg< 29, "sp", [SP]>, DwarfRegNum<[29]>; 137239462Sdim def FP_64 : Mips64GPRReg< 30, "fp", [FP]>, DwarfRegNum<[30]>; 138239462Sdim def RA_64 : Mips64GPRReg< 31, "ra", [RA]>, DwarfRegNum<[31]>; 139226633Sdim 140193323Sed /// Mips Single point precision FPU Registers 141239462Sdim def F0 : FPR< 0, "f0">, DwarfRegNum<[32]>; 142239462Sdim def F1 : FPR< 1, "f1">, DwarfRegNum<[33]>; 143239462Sdim def F2 : FPR< 2, "f2">, DwarfRegNum<[34]>; 144239462Sdim def F3 : FPR< 3, "f3">, DwarfRegNum<[35]>; 145239462Sdim def F4 : FPR< 4, "f4">, DwarfRegNum<[36]>; 146239462Sdim def F5 : FPR< 5, "f5">, DwarfRegNum<[37]>; 147239462Sdim def F6 : FPR< 6, "f6">, DwarfRegNum<[38]>; 148239462Sdim def F7 : FPR< 7, "f7">, DwarfRegNum<[39]>; 149239462Sdim def F8 : FPR< 8, "f8">, DwarfRegNum<[40]>; 150239462Sdim def F9 : FPR< 9, "f9">, DwarfRegNum<[41]>; 151239462Sdim def F10 : FPR<10, "f10">, DwarfRegNum<[42]>; 152239462Sdim def F11 : FPR<11, "f11">, DwarfRegNum<[43]>; 153239462Sdim def F12 : FPR<12, "f12">, DwarfRegNum<[44]>; 154239462Sdim def F13 : FPR<13, "f13">, DwarfRegNum<[45]>; 155239462Sdim def F14 : FPR<14, "f14">, DwarfRegNum<[46]>; 156239462Sdim def F15 : FPR<15, "f15">, DwarfRegNum<[47]>; 157239462Sdim def F16 : FPR<16, "f16">, DwarfRegNum<[48]>; 158239462Sdim def F17 : FPR<17, "f17">, DwarfRegNum<[49]>; 159239462Sdim def F18 : FPR<18, "f18">, DwarfRegNum<[50]>; 160239462Sdim def F19 : FPR<19, "f19">, DwarfRegNum<[51]>; 161239462Sdim def F20 : FPR<20, "f20">, DwarfRegNum<[52]>; 162239462Sdim def F21 : FPR<21, "f21">, DwarfRegNum<[53]>; 163239462Sdim def F22 : FPR<22, "f22">, DwarfRegNum<[54]>; 164239462Sdim def F23 : FPR<23, "f23">, DwarfRegNum<[55]>; 165239462Sdim def F24 : FPR<24, "f24">, DwarfRegNum<[56]>; 166239462Sdim def F25 : FPR<25, "f25">, DwarfRegNum<[57]>; 167239462Sdim def F26 : FPR<26, "f26">, DwarfRegNum<[58]>; 168239462Sdim def F27 : FPR<27, "f27">, DwarfRegNum<[59]>; 169239462Sdim def F28 : FPR<28, "f28">, DwarfRegNum<[60]>; 170239462Sdim def F29 : FPR<29, "f29">, DwarfRegNum<[61]>; 171239462Sdim def F30 : FPR<30, "f30">, DwarfRegNum<[62]>; 172239462Sdim def F31 : FPR<31, "f31">, DwarfRegNum<[63]>; 173221345Sdim 174193323Sed /// Mips Double point precision FPU Registers (aliased 175193323Sed /// with the single precision to hold 64 bit values) 176239462Sdim def D0 : AFPR< 0, "f0", [F0, F1]>; 177239462Sdim def D1 : AFPR< 2, "f2", [F2, F3]>; 178239462Sdim def D2 : AFPR< 4, "f4", [F4, F5]>; 179239462Sdim def D3 : AFPR< 6, "f6", [F6, F7]>; 180239462Sdim def D4 : AFPR< 8, "f8", [F8, F9]>; 181239462Sdim def D5 : AFPR<10, "f10", [F10, F11]>; 182239462Sdim def D6 : AFPR<12, "f12", [F12, F13]>; 183239462Sdim def D7 : AFPR<14, "f14", [F14, F15]>; 184239462Sdim def D8 : AFPR<16, "f16", [F16, F17]>; 185239462Sdim def D9 : AFPR<18, "f18", [F18, F19]>; 186239462Sdim def D10 : AFPR<20, "f20", [F20, F21]>; 187239462Sdim def D11 : AFPR<22, "f22", [F22, F23]>; 188239462Sdim def D12 : AFPR<24, "f24", [F24, F25]>; 189239462Sdim def D13 : AFPR<26, "f26", [F26, F27]>; 190239462Sdim def D14 : AFPR<28, "f28", [F28, F29]>; 191239462Sdim def D15 : AFPR<30, "f30", [F30, F31]>; 192193323Sed 193226633Sdim /// Mips Double point precision FPU Registers in MFP64 mode. 194239462Sdim def D0_64 : AFPR64<0, "f0", [F0]>, DwarfRegNum<[32]>; 195239462Sdim def D1_64 : AFPR64<1, "f1", [F1]>, DwarfRegNum<[33]>; 196239462Sdim def D2_64 : AFPR64<2, "f2", [F2]>, DwarfRegNum<[34]>; 197239462Sdim def D3_64 : AFPR64<3, "f3", [F3]>, DwarfRegNum<[35]>; 198239462Sdim def D4_64 : AFPR64<4, "f4", [F4]>, DwarfRegNum<[36]>; 199239462Sdim def D5_64 : AFPR64<5, "f5", [F5]>, DwarfRegNum<[37]>; 200239462Sdim def D6_64 : AFPR64<6, "f6", [F6]>, DwarfRegNum<[38]>; 201239462Sdim def D7_64 : AFPR64<7, "f7", [F7]>, DwarfRegNum<[39]>; 202239462Sdim def D8_64 : AFPR64<8, "f8", [F8]>, DwarfRegNum<[40]>; 203239462Sdim def D9_64 : AFPR64<9, "f9", [F9]>, DwarfRegNum<[41]>; 204239462Sdim def D10_64 : AFPR64<10, "f10", [F10]>, DwarfRegNum<[42]>; 205239462Sdim def D11_64 : AFPR64<11, "f11", [F11]>, DwarfRegNum<[43]>; 206239462Sdim def D12_64 : AFPR64<12, "f12", [F12]>, DwarfRegNum<[44]>; 207239462Sdim def D13_64 : AFPR64<13, "f13", [F13]>, DwarfRegNum<[45]>; 208239462Sdim def D14_64 : AFPR64<14, "f14", [F14]>, DwarfRegNum<[46]>; 209239462Sdim def D15_64 : AFPR64<15, "f15", [F15]>, DwarfRegNum<[47]>; 210239462Sdim def D16_64 : AFPR64<16, "f16", [F16]>, DwarfRegNum<[48]>; 211239462Sdim def D17_64 : AFPR64<17, "f17", [F17]>, DwarfRegNum<[49]>; 212239462Sdim def D18_64 : AFPR64<18, "f18", [F18]>, DwarfRegNum<[50]>; 213239462Sdim def D19_64 : AFPR64<19, "f19", [F19]>, DwarfRegNum<[51]>; 214239462Sdim def D20_64 : AFPR64<20, "f20", [F20]>, DwarfRegNum<[52]>; 215239462Sdim def D21_64 : AFPR64<21, "f21", [F21]>, DwarfRegNum<[53]>; 216239462Sdim def D22_64 : AFPR64<22, "f22", [F22]>, DwarfRegNum<[54]>; 217239462Sdim def D23_64 : AFPR64<23, "f23", [F23]>, DwarfRegNum<[55]>; 218239462Sdim def D24_64 : AFPR64<24, "f24", [F24]>, DwarfRegNum<[56]>; 219239462Sdim def D25_64 : AFPR64<25, "f25", [F25]>, DwarfRegNum<[57]>; 220239462Sdim def D26_64 : AFPR64<26, "f26", [F26]>, DwarfRegNum<[58]>; 221239462Sdim def D27_64 : AFPR64<27, "f27", [F27]>, DwarfRegNum<[59]>; 222239462Sdim def D28_64 : AFPR64<28, "f28", [F28]>, DwarfRegNum<[60]>; 223239462Sdim def D29_64 : AFPR64<29, "f29", [F29]>, DwarfRegNum<[61]>; 224239462Sdim def D30_64 : AFPR64<30, "f30", [F30]>, DwarfRegNum<[62]>; 225239462Sdim def D31_64 : AFPR64<31, "f31", [F31]>, DwarfRegNum<[63]>; 226226633Sdim 227193323Sed // Hi/Lo registers 228193323Sed def HI : Register<"hi">, DwarfRegNum<[64]>; 229193323Sed def LO : Register<"lo">, DwarfRegNum<[65]>; 230193323Sed 231226633Sdim let SubRegIndices = [sub_32] in { 232226633Sdim def HI64 : RegisterWithSubRegs<"hi", [HI]>; 233226633Sdim def LO64 : RegisterWithSubRegs<"lo", [LO]>; 234226633Sdim } 235226633Sdim 236193323Sed // Status flags register 237193323Sed def FCR31 : Register<"31">; 238223017Sdim 239239462Sdim // fcc0 register 240239462Sdim def FCC0 : Register<"fcc0">; 241239462Sdim 242223017Sdim // Hardware register $29 243223017Sdim def HWR29 : Register<"29">; 244234353Sdim def HWR29_64 : Register<"29">; 245193323Sed} 246193323Sed 247193323Sed//===----------------------------------------------------------------------===// 248193323Sed// Register Classes 249193323Sed//===----------------------------------------------------------------------===// 250193323Sed 251224145Sdimdef CPURegs : RegisterClass<"Mips", [i32], 32, (add 252239462Sdim // Reserved 253239462Sdim ZERO, AT, 254193323Sed // Return Values and Arguments 255224145Sdim V0, V1, A0, A1, A2, A3, 256193323Sed // Not preserved across procedure calls 257239462Sdim T0, T1, T2, T3, T4, T5, T6, T7, 258193323Sed // Callee save 259193323Sed S0, S1, S2, S3, S4, S5, S6, S7, 260239462Sdim // Not preserved across procedure calls 261239462Sdim T8, T9, 262193323Sed // Reserved 263239462Sdim K0, K1, GP, SP, FP, RA)>; 264193323Sed 265226633Sdimdef CPU64Regs : RegisterClass<"Mips", [i64], 64, (add 266239462Sdim// Reserved 267239462Sdim ZERO_64, AT_64, 268226633Sdim // Return Values and Arguments 269226633Sdim V0_64, V1_64, A0_64, A1_64, A2_64, A3_64, 270226633Sdim // Not preserved across procedure calls 271239462Sdim T0_64, T1_64, T2_64, T3_64, T4_64, T5_64, T6_64, T7_64, 272226633Sdim // Callee save 273226633Sdim S0_64, S1_64, S2_64, S3_64, S4_64, S5_64, S6_64, S7_64, 274239462Sdim // Not preserved across procedure calls 275239462Sdim T8_64, T9_64, 276226633Sdim // Reserved 277239462Sdim K0_64, K1_64, GP_64, SP_64, FP_64, RA_64)>; 278226633Sdim 279239462Sdimdef CPU16Regs : RegisterClass<"Mips", [i32], 32, (add 280239462Sdim // Return Values and Arguments 281239462Sdim V0, V1, A0, A1, A2, A3, 282239462Sdim // Callee save 283239462Sdim S0, S1)>; 284239462Sdim 285239462Sdimdef CPURAReg : RegisterClass<"Mips", [i32], 32, (add RA)>; 286239462Sdim 287239462Sdim 288193323Sed// 64bit fp: 289193323Sed// * FGR64 - 32 64-bit registers 290221345Sdim// * AFGR64 - 16 32-bit even registers (32-bit FP Mode) 291193323Sed// 292193323Sed// 32bit fp: 293193323Sed// * FGR32 - 16 32-bit even registers 294193323Sed// * FGR32 - 32 32-bit registers (single float only mode) 295224145Sdimdef FGR32 : RegisterClass<"Mips", [f32], 32, (sequence "F%u", 0, 31)>; 296193323Sed 297224145Sdimdef AFGR64 : RegisterClass<"Mips", [f64], 64, (add 298193323Sed // Return Values and Arguments 299239462Sdim D0, D1, 300193323Sed // Not preserved across procedure calls 301239462Sdim D2, D3, D4, D5, 302239462Sdim // Return Values and Arguments 303239462Sdim D6, D7, 304239462Sdim // Not preserved across procedure calls 305239462Sdim D8, D9, 306193323Sed // Callee save 307239462Sdim D10, D11, D12, D13, D14, D15)>; 308193323Sed 309239462Sdimdef FGR64 : RegisterClass<"Mips", [f64], 64, (sequence "D%u_64", 0, 31)>; 310226633Sdim 311193323Sed// Condition Register for floating point operations 312239462Sdimdef CCR : RegisterClass<"Mips", [i32], 32, (add FCR31,FCC0)>; 313193323Sed 314193323Sed// Hi/Lo Registers 315224145Sdimdef HILO : RegisterClass<"Mips", [i32], 32, (add HI, LO)>; 316239462Sdimdef HILO64 : RegisterClass<"Mips", [i64], 64, (add HI64, LO64)>; 317193323Sed 318223017Sdim// Hardware registers 319224145Sdimdef HWRegs : RegisterClass<"Mips", [i32], 32, (add HWR29)>; 320234353Sdimdef HWRegs64 : RegisterClass<"Mips", [i64], 32, (add HWR29_64)>; 321234353Sdim 322