MipsRegisterInfo.td revision 226633
1212904Sdim//===- MipsRegisterInfo.td - Mips Register defs ------------*- tablegen -*-===// 2193323Sed// 3193323Sed// The LLVM Compiler Infrastructure 4193323Sed// 5193323Sed// This file is distributed under the University of Illinois Open Source 6193323Sed// License. See LICENSE.TXT for details. 7193323Sed// 8193323Sed//===----------------------------------------------------------------------===// 9193323Sed 10193323Sed//===----------------------------------------------------------------------===// 11193323Sed// Declarations that describe the MIPS register file 12193323Sed//===----------------------------------------------------------------------===// 13226633Sdimlet Namespace = "Mips" in { 14226633Sdimdef sub_fpeven : SubRegIndex; 15226633Sdimdef sub_fpodd : SubRegIndex; 16226633Sdimdef sub_32 : SubRegIndex; 17226633Sdim} 18193323Sed 19193323Sed// We have banks of 32 registers each. 20193323Sedclass MipsReg<string n> : Register<n> { 21193323Sed field bits<5> Num; 22193323Sed let Namespace = "Mips"; 23193323Sed} 24193323Sed 25221345Sdimclass MipsRegWithSubRegs<string n, list<Register> subregs> 26199511Srdivacky : RegisterWithSubRegs<n, subregs> { 27199511Srdivacky field bits<5> Num; 28199511Srdivacky let Namespace = "Mips"; 29199511Srdivacky} 30199511Srdivacky 31193323Sed// Mips CPU Registers 32193323Sedclass MipsGPRReg<bits<5> num, string n> : MipsReg<n> { 33193323Sed let Num = num; 34193323Sed} 35193323Sed 36226633Sdim// Mips 64-bit CPU Registers 37226633Sdimclass Mips64GPRReg<bits<5> num, string n, list<Register> subregs> 38226633Sdim : MipsRegWithSubRegs<n, subregs> { 39226633Sdim let Num = num; 40226633Sdim let SubRegIndices = [sub_32]; 41226633Sdim} 42226633Sdim 43193323Sed// Mips 32-bit FPU Registers 44193323Sedclass FPR<bits<5> num, string n> : MipsReg<n> { 45193323Sed let Num = num; 46193323Sed} 47193323Sed 48193323Sed// Mips 64-bit (aliased) FPU Registers 49208599Srdivackyclass AFPR<bits<5> num, string n, list<Register> subregs> 50199511Srdivacky : MipsRegWithSubRegs<n, subregs> { 51193323Sed let Num = num; 52208599Srdivacky let SubRegIndices = [sub_fpeven, sub_fpodd]; 53193323Sed} 54193323Sed 55226633Sdimclass AFPR64<bits<5> num, string n, list<Register> subregs> 56226633Sdim : MipsRegWithSubRegs<n, subregs> { 57226633Sdim let Num = num; 58226633Sdim let SubRegIndices = [sub_32]; 59226633Sdim} 60226633Sdim 61223017Sdim// Mips Hardware Registers 62223017Sdimclass HWR<bits<5> num, string n> : MipsReg<n> { 63223017Sdim let Num = num; 64223017Sdim} 65223017Sdim 66193323Sed//===----------------------------------------------------------------------===// 67193323Sed// Registers 68193323Sed//===----------------------------------------------------------------------===// 69193323Sed 70193323Sedlet Namespace = "Mips" in { 71226633Sdim // FIXME: Fix DwarfRegNum. 72193323Sed 73193323Sed // General Purpose Registers 74193323Sed def ZERO : MipsGPRReg< 0, "ZERO">, DwarfRegNum<[0]>; 75193323Sed def AT : MipsGPRReg< 1, "AT">, DwarfRegNum<[1]>; 76193323Sed def V0 : MipsGPRReg< 2, "2">, DwarfRegNum<[2]>; 77193323Sed def V1 : MipsGPRReg< 3, "3">, DwarfRegNum<[3]>; 78223017Sdim def A0 : MipsGPRReg< 4, "4">, DwarfRegNum<[4]>; 79193323Sed def A1 : MipsGPRReg< 5, "5">, DwarfRegNum<[5]>; 80193323Sed def A2 : MipsGPRReg< 6, "6">, DwarfRegNum<[6]>; 81193323Sed def A3 : MipsGPRReg< 7, "7">, DwarfRegNum<[7]>; 82193323Sed def T0 : MipsGPRReg< 8, "8">, DwarfRegNum<[8]>; 83193323Sed def T1 : MipsGPRReg< 9, "9">, DwarfRegNum<[9]>; 84193323Sed def T2 : MipsGPRReg< 10, "10">, DwarfRegNum<[10]>; 85193323Sed def T3 : MipsGPRReg< 11, "11">, DwarfRegNum<[11]>; 86193323Sed def T4 : MipsGPRReg< 12, "12">, DwarfRegNum<[12]>; 87193323Sed def T5 : MipsGPRReg< 13, "13">, DwarfRegNum<[13]>; 88193323Sed def T6 : MipsGPRReg< 14, "14">, DwarfRegNum<[14]>; 89193323Sed def T7 : MipsGPRReg< 15, "15">, DwarfRegNum<[15]>; 90193323Sed def S0 : MipsGPRReg< 16, "16">, DwarfRegNum<[16]>; 91193323Sed def S1 : MipsGPRReg< 17, "17">, DwarfRegNum<[17]>; 92193323Sed def S2 : MipsGPRReg< 18, "18">, DwarfRegNum<[18]>; 93193323Sed def S3 : MipsGPRReg< 19, "19">, DwarfRegNum<[19]>; 94193323Sed def S4 : MipsGPRReg< 20, "20">, DwarfRegNum<[20]>; 95193323Sed def S5 : MipsGPRReg< 21, "21">, DwarfRegNum<[21]>; 96193323Sed def S6 : MipsGPRReg< 22, "22">, DwarfRegNum<[22]>; 97193323Sed def S7 : MipsGPRReg< 23, "23">, DwarfRegNum<[23]>; 98193323Sed def T8 : MipsGPRReg< 24, "24">, DwarfRegNum<[24]>; 99193323Sed def T9 : MipsGPRReg< 25, "25">, DwarfRegNum<[25]>; 100193323Sed def K0 : MipsGPRReg< 26, "26">, DwarfRegNum<[26]>; 101193323Sed def K1 : MipsGPRReg< 27, "27">, DwarfRegNum<[27]>; 102193323Sed def GP : MipsGPRReg< 28, "GP">, DwarfRegNum<[28]>; 103193323Sed def SP : MipsGPRReg< 29, "SP">, DwarfRegNum<[29]>; 104193323Sed def FP : MipsGPRReg< 30, "FP">, DwarfRegNum<[30]>; 105193323Sed def RA : MipsGPRReg< 31, "RA">, DwarfRegNum<[31]>; 106221345Sdim 107226633Sdim // General Purpose 64-bit Registers 108226633Sdim def ZERO_64 : Mips64GPRReg< 0, "ZERO", [ZERO]>; 109226633Sdim def AT_64 : Mips64GPRReg< 1, "AT", [AT]>; 110226633Sdim def V0_64 : Mips64GPRReg< 2, "2", [V0]>; 111226633Sdim def V1_64 : Mips64GPRReg< 3, "3", [V1]>; 112226633Sdim def A0_64 : Mips64GPRReg< 4, "4", [A0]>; 113226633Sdim def A1_64 : Mips64GPRReg< 5, "5", [A1]>; 114226633Sdim def A2_64 : Mips64GPRReg< 6, "6", [A2]>; 115226633Sdim def A3_64 : Mips64GPRReg< 7, "7", [A3]>; 116226633Sdim def T0_64 : Mips64GPRReg< 8, "8", [T0]>; 117226633Sdim def T1_64 : Mips64GPRReg< 9, "9", [T1]>; 118226633Sdim def T2_64 : Mips64GPRReg< 10, "10", [T2]>; 119226633Sdim def T3_64 : Mips64GPRReg< 11, "11", [T3]>; 120226633Sdim def T4_64 : Mips64GPRReg< 12, "12", [T4]>; 121226633Sdim def T5_64 : Mips64GPRReg< 13, "13", [T5]>; 122226633Sdim def T6_64 : Mips64GPRReg< 14, "14", [T6]>; 123226633Sdim def T7_64 : Mips64GPRReg< 15, "15", [T7]>; 124226633Sdim def S0_64 : Mips64GPRReg< 16, "16", [S0]>; 125226633Sdim def S1_64 : Mips64GPRReg< 17, "17", [S1]>; 126226633Sdim def S2_64 : Mips64GPRReg< 18, "18", [S2]>; 127226633Sdim def S3_64 : Mips64GPRReg< 19, "19", [S3]>; 128226633Sdim def S4_64 : Mips64GPRReg< 20, "20", [S4]>; 129226633Sdim def S5_64 : Mips64GPRReg< 21, "21", [S5]>; 130226633Sdim def S6_64 : Mips64GPRReg< 22, "22", [S6]>; 131226633Sdim def S7_64 : Mips64GPRReg< 23, "23", [S7]>; 132226633Sdim def T8_64 : Mips64GPRReg< 24, "24", [T8]>; 133226633Sdim def T9_64 : Mips64GPRReg< 25, "25", [T9]>; 134226633Sdim def K0_64 : Mips64GPRReg< 26, "26", [K0]>; 135226633Sdim def K1_64 : Mips64GPRReg< 27, "27", [K1]>; 136226633Sdim def GP_64 : Mips64GPRReg< 28, "GP", [GP]>; 137226633Sdim def SP_64 : Mips64GPRReg< 29, "SP", [SP]>; 138226633Sdim def FP_64 : Mips64GPRReg< 30, "FP", [FP]>; 139226633Sdim def RA_64 : Mips64GPRReg< 31, "RA", [RA]>; 140226633Sdim 141193323Sed /// Mips Single point precision FPU Registers 142193323Sed def F0 : FPR< 0, "F0">, DwarfRegNum<[32]>; 143193323Sed def F1 : FPR< 1, "F1">, DwarfRegNum<[33]>; 144193323Sed def F2 : FPR< 2, "F2">, DwarfRegNum<[34]>; 145193323Sed def F3 : FPR< 3, "F3">, DwarfRegNum<[35]>; 146193323Sed def F4 : FPR< 4, "F4">, DwarfRegNum<[36]>; 147193323Sed def F5 : FPR< 5, "F5">, DwarfRegNum<[37]>; 148193323Sed def F6 : FPR< 6, "F6">, DwarfRegNum<[38]>; 149193323Sed def F7 : FPR< 7, "F7">, DwarfRegNum<[39]>; 150193323Sed def F8 : FPR< 8, "F8">, DwarfRegNum<[40]>; 151193323Sed def F9 : FPR< 9, "F9">, DwarfRegNum<[41]>; 152193323Sed def F10 : FPR<10, "F10">, DwarfRegNum<[42]>; 153193323Sed def F11 : FPR<11, "F11">, DwarfRegNum<[43]>; 154193323Sed def F12 : FPR<12, "F12">, DwarfRegNum<[44]>; 155193323Sed def F13 : FPR<13, "F13">, DwarfRegNum<[45]>; 156193323Sed def F14 : FPR<14, "F14">, DwarfRegNum<[46]>; 157193323Sed def F15 : FPR<15, "F15">, DwarfRegNum<[47]>; 158193323Sed def F16 : FPR<16, "F16">, DwarfRegNum<[48]>; 159193323Sed def F17 : FPR<17, "F17">, DwarfRegNum<[49]>; 160193323Sed def F18 : FPR<18, "F18">, DwarfRegNum<[50]>; 161193323Sed def F19 : FPR<19, "F19">, DwarfRegNum<[51]>; 162193323Sed def F20 : FPR<20, "F20">, DwarfRegNum<[52]>; 163193323Sed def F21 : FPR<21, "F21">, DwarfRegNum<[53]>; 164193323Sed def F22 : FPR<22, "F22">, DwarfRegNum<[54]>; 165193323Sed def F23 : FPR<23, "F23">, DwarfRegNum<[55]>; 166193323Sed def F24 : FPR<24, "F24">, DwarfRegNum<[56]>; 167193323Sed def F25 : FPR<25, "F25">, DwarfRegNum<[57]>; 168193323Sed def F26 : FPR<26, "F26">, DwarfRegNum<[58]>; 169193323Sed def F27 : FPR<27, "F27">, DwarfRegNum<[59]>; 170193323Sed def F28 : FPR<28, "F28">, DwarfRegNum<[60]>; 171193323Sed def F29 : FPR<29, "F29">, DwarfRegNum<[61]>; 172193323Sed def F30 : FPR<30, "F30">, DwarfRegNum<[62]>; 173193323Sed def F31 : FPR<31, "F31">, DwarfRegNum<[63]>; 174221345Sdim 175193323Sed /// Mips Double point precision FPU Registers (aliased 176193323Sed /// with the single precision to hold 64 bit values) 177223017Sdim def D0 : AFPR< 0, "F0", [F0, F1]>; 178223017Sdim def D1 : AFPR< 2, "F2", [F2, F3]>; 179223017Sdim def D2 : AFPR< 4, "F4", [F4, F5]>; 180223017Sdim def D3 : AFPR< 6, "F6", [F6, F7]>; 181223017Sdim def D4 : AFPR< 8, "F8", [F8, F9]>; 182223017Sdim def D5 : AFPR<10, "F10", [F10, F11]>; 183223017Sdim def D6 : AFPR<12, "F12", [F12, F13]>; 184223017Sdim def D7 : AFPR<14, "F14", [F14, F15]>; 185223017Sdim def D8 : AFPR<16, "F16", [F16, F17]>; 186223017Sdim def D9 : AFPR<18, "F18", [F18, F19]>; 187223017Sdim def D10 : AFPR<20, "F20", [F20, F21]>; 188223017Sdim def D11 : AFPR<22, "F22", [F22, F23]>; 189223017Sdim def D12 : AFPR<24, "F24", [F24, F25]>; 190223017Sdim def D13 : AFPR<26, "F26", [F26, F27]>; 191223017Sdim def D14 : AFPR<28, "F28", [F28, F29]>; 192223017Sdim def D15 : AFPR<30, "F30", [F30, F31]>; 193193323Sed 194226633Sdim /// Mips Double point precision FPU Registers in MFP64 mode. 195226633Sdim def D0_64 : AFPR64<0, "F0", [F0]>; 196226633Sdim def D1_64 : AFPR64<1, "F1", [F1]>; 197226633Sdim def D2_64 : AFPR64<2, "F2", [F2]>; 198226633Sdim def D3_64 : AFPR64<3, "F3", [F3]>; 199226633Sdim def D4_64 : AFPR64<4, "F4", [F4]>; 200226633Sdim def D5_64 : AFPR64<5, "F5", [F5]>; 201226633Sdim def D6_64 : AFPR64<6, "F6", [F6]>; 202226633Sdim def D7_64 : AFPR64<7, "F7", [F7]>; 203226633Sdim def D8_64 : AFPR64<8, "F8", [F8]>; 204226633Sdim def D9_64 : AFPR64<9, "F9", [F9]>; 205226633Sdim def D10_64 : AFPR64<10, "F10", [F10]>; 206226633Sdim def D11_64 : AFPR64<11, "F11", [F11]>; 207226633Sdim def D12_64 : AFPR64<12, "F12", [F12]>; 208226633Sdim def D13_64 : AFPR64<13, "F13", [F13]>; 209226633Sdim def D14_64 : AFPR64<14, "F14", [F14]>; 210226633Sdim def D15_64 : AFPR64<15, "F15", [F15]>; 211226633Sdim def D16_64 : AFPR64<16, "F16", [F16]>; 212226633Sdim def D17_64 : AFPR64<17, "F17", [F17]>; 213226633Sdim def D18_64 : AFPR64<18, "F18", [F18]>; 214226633Sdim def D19_64 : AFPR64<19, "F19", [F19]>; 215226633Sdim def D20_64 : AFPR64<20, "F20", [F20]>; 216226633Sdim def D21_64 : AFPR64<21, "F21", [F21]>; 217226633Sdim def D22_64 : AFPR64<22, "F22", [F22]>; 218226633Sdim def D23_64 : AFPR64<23, "F23", [F23]>; 219226633Sdim def D24_64 : AFPR64<24, "F24", [F24]>; 220226633Sdim def D25_64 : AFPR64<25, "F25", [F25]>; 221226633Sdim def D26_64 : AFPR64<26, "F26", [F26]>; 222226633Sdim def D27_64 : AFPR64<27, "F27", [F27]>; 223226633Sdim def D28_64 : AFPR64<28, "F28", [F28]>; 224226633Sdim def D29_64 : AFPR64<29, "F29", [F29]>; 225226633Sdim def D30_64 : AFPR64<30, "F30", [F30]>; 226226633Sdim def D31_64 : AFPR64<31, "F31", [F31]>; 227226633Sdim 228193323Sed // Hi/Lo registers 229193323Sed def HI : Register<"hi">, DwarfRegNum<[64]>; 230193323Sed def LO : Register<"lo">, DwarfRegNum<[65]>; 231193323Sed 232226633Sdim let SubRegIndices = [sub_32] in { 233226633Sdim def HI64 : RegisterWithSubRegs<"hi", [HI]>; 234226633Sdim def LO64 : RegisterWithSubRegs<"lo", [LO]>; 235226633Sdim } 236226633Sdim 237193323Sed // Status flags register 238193323Sed def FCR31 : Register<"31">; 239223017Sdim 240223017Sdim // Hardware register $29 241223017Sdim def HWR29 : Register<"29">; 242193323Sed} 243193323Sed 244193323Sed//===----------------------------------------------------------------------===// 245193323Sed// Register Classes 246193323Sed//===----------------------------------------------------------------------===// 247193323Sed 248224145Sdimdef CPURegs : RegisterClass<"Mips", [i32], 32, (add 249193323Sed // Return Values and Arguments 250224145Sdim V0, V1, A0, A1, A2, A3, 251193323Sed // Not preserved across procedure calls 252221345Sdim T0, T1, T2, T3, T4, T5, T6, T7, T8, T9, 253193323Sed // Callee save 254193323Sed S0, S1, S2, S3, S4, S5, S6, S7, 255193323Sed // Reserved 256224145Sdim ZERO, AT, K0, K1, GP, SP, FP, RA)>; 257193323Sed 258226633Sdimdef CPU64Regs : RegisterClass<"Mips", [i64], 64, (add 259226633Sdim // Return Values and Arguments 260226633Sdim V0_64, V1_64, A0_64, A1_64, A2_64, A3_64, 261226633Sdim // Not preserved across procedure calls 262226633Sdim T0_64, T1_64, T2_64, T3_64, T4_64, T5_64, T6_64, T7_64, T8_64, T9_64, 263226633Sdim // Callee save 264226633Sdim S0_64, S1_64, S2_64, S3_64, S4_64, S5_64, S6_64, S7_64, 265226633Sdim // Reserved 266226633Sdim ZERO_64, AT_64, K0_64, K1_64, GP_64, SP_64, FP_64, RA_64)> { 267226633Sdim let SubRegClasses = [(CPURegs sub_32)]; 268226633Sdim} 269226633Sdim 270193323Sed// 64bit fp: 271193323Sed// * FGR64 - 32 64-bit registers 272221345Sdim// * AFGR64 - 16 32-bit even registers (32-bit FP Mode) 273193323Sed// 274193323Sed// 32bit fp: 275193323Sed// * FGR32 - 16 32-bit even registers 276193323Sed// * FGR32 - 32 32-bit registers (single float only mode) 277224145Sdimdef FGR32 : RegisterClass<"Mips", [f32], 32, (sequence "F%u", 0, 31)>; 278193323Sed 279224145Sdimdef AFGR64 : RegisterClass<"Mips", [f64], 64, (add 280193323Sed // Return Values and Arguments 281224145Sdim D0, D1, D6, D7, 282193323Sed // Not preserved across procedure calls 283221345Sdim D2, D3, D4, D5, D8, D9, 284193323Sed // Callee save 285226633Sdim D10, D11, D12, D13, D14, D15)> { 286208599Srdivacky let SubRegClasses = [(FGR32 sub_fpeven, sub_fpodd)]; 287193323Sed} 288193323Sed 289226633Sdimdef FGR64 : RegisterClass<"Mips", [f64], 64, (sequence "D%u_64", 0, 31)> { 290226633Sdim let SubRegClasses = [(FGR32 sub_32)]; 291226633Sdim} 292226633Sdim 293193323Sed// Condition Register for floating point operations 294224145Sdimdef CCR : RegisterClass<"Mips", [i32], 32, (add FCR31)>; 295193323Sed 296193323Sed// Hi/Lo Registers 297224145Sdimdef HILO : RegisterClass<"Mips", [i32], 32, (add HI, LO)>; 298226633Sdimdef HILO64 : RegisterClass<"Mips", [i64], 64, (add HI64, LO64)> { 299226633Sdim let SubRegClasses = [(HILO sub_32)]; 300226633Sdim} 301193323Sed 302223017Sdim// Hardware registers 303224145Sdimdef HWRegs : RegisterClass<"Mips", [i32], 32, (add HWR29)>; 304