MipsRegisterInfo.td revision 224145
1212904Sdim//===- MipsRegisterInfo.td - Mips Register defs ------------*- tablegen -*-===// 2193323Sed// 3193323Sed// The LLVM Compiler Infrastructure 4193323Sed// 5193323Sed// This file is distributed under the University of Illinois Open Source 6193323Sed// License. See LICENSE.TXT for details. 7193323Sed// 8193323Sed//===----------------------------------------------------------------------===// 9193323Sed 10193323Sed//===----------------------------------------------------------------------===// 11193323Sed// Declarations that describe the MIPS register file 12193323Sed//===----------------------------------------------------------------------===// 13193323Sed 14193323Sed// We have banks of 32 registers each. 15193323Sedclass MipsReg<string n> : Register<n> { 16193323Sed field bits<5> Num; 17193323Sed let Namespace = "Mips"; 18193323Sed} 19193323Sed 20221345Sdimclass MipsRegWithSubRegs<string n, list<Register> subregs> 21199511Srdivacky : RegisterWithSubRegs<n, subregs> { 22199511Srdivacky field bits<5> Num; 23199511Srdivacky let Namespace = "Mips"; 24199511Srdivacky} 25199511Srdivacky 26193323Sed// Mips CPU Registers 27193323Sedclass MipsGPRReg<bits<5> num, string n> : MipsReg<n> { 28193323Sed let Num = num; 29193323Sed} 30193323Sed 31193323Sed// Mips 32-bit FPU Registers 32193323Sedclass FPR<bits<5> num, string n> : MipsReg<n> { 33193323Sed let Num = num; 34193323Sed} 35193323Sed 36193323Sed// Mips 64-bit (aliased) FPU Registers 37208599Srdivackylet Namespace = "Mips" in { 38208599Srdivackydef sub_fpeven : SubRegIndex; 39208599Srdivackydef sub_fpodd : SubRegIndex; 40208599Srdivacky} 41208599Srdivackyclass AFPR<bits<5> num, string n, list<Register> subregs> 42199511Srdivacky : MipsRegWithSubRegs<n, subregs> { 43193323Sed let Num = num; 44208599Srdivacky let SubRegIndices = [sub_fpeven, sub_fpodd]; 45193323Sed} 46193323Sed 47223017Sdim// Mips Hardware Registers 48223017Sdimclass HWR<bits<5> num, string n> : MipsReg<n> { 49223017Sdim let Num = num; 50223017Sdim} 51223017Sdim 52193323Sed//===----------------------------------------------------------------------===// 53193323Sed// Registers 54193323Sed//===----------------------------------------------------------------------===// 55193323Sed 56193323Sedlet Namespace = "Mips" in { 57193323Sed 58193323Sed // General Purpose Registers 59193323Sed def ZERO : MipsGPRReg< 0, "ZERO">, DwarfRegNum<[0]>; 60193323Sed def AT : MipsGPRReg< 1, "AT">, DwarfRegNum<[1]>; 61193323Sed def V0 : MipsGPRReg< 2, "2">, DwarfRegNum<[2]>; 62193323Sed def V1 : MipsGPRReg< 3, "3">, DwarfRegNum<[3]>; 63223017Sdim def A0 : MipsGPRReg< 4, "4">, DwarfRegNum<[4]>; 64193323Sed def A1 : MipsGPRReg< 5, "5">, DwarfRegNum<[5]>; 65193323Sed def A2 : MipsGPRReg< 6, "6">, DwarfRegNum<[6]>; 66193323Sed def A3 : MipsGPRReg< 7, "7">, DwarfRegNum<[7]>; 67193323Sed def T0 : MipsGPRReg< 8, "8">, DwarfRegNum<[8]>; 68193323Sed def T1 : MipsGPRReg< 9, "9">, DwarfRegNum<[9]>; 69193323Sed def T2 : MipsGPRReg< 10, "10">, DwarfRegNum<[10]>; 70193323Sed def T3 : MipsGPRReg< 11, "11">, DwarfRegNum<[11]>; 71193323Sed def T4 : MipsGPRReg< 12, "12">, DwarfRegNum<[12]>; 72193323Sed def T5 : MipsGPRReg< 13, "13">, DwarfRegNum<[13]>; 73193323Sed def T6 : MipsGPRReg< 14, "14">, DwarfRegNum<[14]>; 74193323Sed def T7 : MipsGPRReg< 15, "15">, DwarfRegNum<[15]>; 75193323Sed def S0 : MipsGPRReg< 16, "16">, DwarfRegNum<[16]>; 76193323Sed def S1 : MipsGPRReg< 17, "17">, DwarfRegNum<[17]>; 77193323Sed def S2 : MipsGPRReg< 18, "18">, DwarfRegNum<[18]>; 78193323Sed def S3 : MipsGPRReg< 19, "19">, DwarfRegNum<[19]>; 79193323Sed def S4 : MipsGPRReg< 20, "20">, DwarfRegNum<[20]>; 80193323Sed def S5 : MipsGPRReg< 21, "21">, DwarfRegNum<[21]>; 81193323Sed def S6 : MipsGPRReg< 22, "22">, DwarfRegNum<[22]>; 82193323Sed def S7 : MipsGPRReg< 23, "23">, DwarfRegNum<[23]>; 83193323Sed def T8 : MipsGPRReg< 24, "24">, DwarfRegNum<[24]>; 84193323Sed def T9 : MipsGPRReg< 25, "25">, DwarfRegNum<[25]>; 85193323Sed def K0 : MipsGPRReg< 26, "26">, DwarfRegNum<[26]>; 86193323Sed def K1 : MipsGPRReg< 27, "27">, DwarfRegNum<[27]>; 87193323Sed def GP : MipsGPRReg< 28, "GP">, DwarfRegNum<[28]>; 88193323Sed def SP : MipsGPRReg< 29, "SP">, DwarfRegNum<[29]>; 89193323Sed def FP : MipsGPRReg< 30, "FP">, DwarfRegNum<[30]>; 90193323Sed def RA : MipsGPRReg< 31, "RA">, DwarfRegNum<[31]>; 91221345Sdim 92193323Sed /// Mips Single point precision FPU Registers 93193323Sed def F0 : FPR< 0, "F0">, DwarfRegNum<[32]>; 94193323Sed def F1 : FPR< 1, "F1">, DwarfRegNum<[33]>; 95193323Sed def F2 : FPR< 2, "F2">, DwarfRegNum<[34]>; 96193323Sed def F3 : FPR< 3, "F3">, DwarfRegNum<[35]>; 97193323Sed def F4 : FPR< 4, "F4">, DwarfRegNum<[36]>; 98193323Sed def F5 : FPR< 5, "F5">, DwarfRegNum<[37]>; 99193323Sed def F6 : FPR< 6, "F6">, DwarfRegNum<[38]>; 100193323Sed def F7 : FPR< 7, "F7">, DwarfRegNum<[39]>; 101193323Sed def F8 : FPR< 8, "F8">, DwarfRegNum<[40]>; 102193323Sed def F9 : FPR< 9, "F9">, DwarfRegNum<[41]>; 103193323Sed def F10 : FPR<10, "F10">, DwarfRegNum<[42]>; 104193323Sed def F11 : FPR<11, "F11">, DwarfRegNum<[43]>; 105193323Sed def F12 : FPR<12, "F12">, DwarfRegNum<[44]>; 106193323Sed def F13 : FPR<13, "F13">, DwarfRegNum<[45]>; 107193323Sed def F14 : FPR<14, "F14">, DwarfRegNum<[46]>; 108193323Sed def F15 : FPR<15, "F15">, DwarfRegNum<[47]>; 109193323Sed def F16 : FPR<16, "F16">, DwarfRegNum<[48]>; 110193323Sed def F17 : FPR<17, "F17">, DwarfRegNum<[49]>; 111193323Sed def F18 : FPR<18, "F18">, DwarfRegNum<[50]>; 112193323Sed def F19 : FPR<19, "F19">, DwarfRegNum<[51]>; 113193323Sed def F20 : FPR<20, "F20">, DwarfRegNum<[52]>; 114193323Sed def F21 : FPR<21, "F21">, DwarfRegNum<[53]>; 115193323Sed def F22 : FPR<22, "F22">, DwarfRegNum<[54]>; 116193323Sed def F23 : FPR<23, "F23">, DwarfRegNum<[55]>; 117193323Sed def F24 : FPR<24, "F24">, DwarfRegNum<[56]>; 118193323Sed def F25 : FPR<25, "F25">, DwarfRegNum<[57]>; 119193323Sed def F26 : FPR<26, "F26">, DwarfRegNum<[58]>; 120193323Sed def F27 : FPR<27, "F27">, DwarfRegNum<[59]>; 121193323Sed def F28 : FPR<28, "F28">, DwarfRegNum<[60]>; 122193323Sed def F29 : FPR<29, "F29">, DwarfRegNum<[61]>; 123193323Sed def F30 : FPR<30, "F30">, DwarfRegNum<[62]>; 124193323Sed def F31 : FPR<31, "F31">, DwarfRegNum<[63]>; 125221345Sdim 126193323Sed /// Mips Double point precision FPU Registers (aliased 127193323Sed /// with the single precision to hold 64 bit values) 128223017Sdim def D0 : AFPR< 0, "F0", [F0, F1]>; 129223017Sdim def D1 : AFPR< 2, "F2", [F2, F3]>; 130223017Sdim def D2 : AFPR< 4, "F4", [F4, F5]>; 131223017Sdim def D3 : AFPR< 6, "F6", [F6, F7]>; 132223017Sdim def D4 : AFPR< 8, "F8", [F8, F9]>; 133223017Sdim def D5 : AFPR<10, "F10", [F10, F11]>; 134223017Sdim def D6 : AFPR<12, "F12", [F12, F13]>; 135223017Sdim def D7 : AFPR<14, "F14", [F14, F15]>; 136223017Sdim def D8 : AFPR<16, "F16", [F16, F17]>; 137223017Sdim def D9 : AFPR<18, "F18", [F18, F19]>; 138223017Sdim def D10 : AFPR<20, "F20", [F20, F21]>; 139223017Sdim def D11 : AFPR<22, "F22", [F22, F23]>; 140223017Sdim def D12 : AFPR<24, "F24", [F24, F25]>; 141223017Sdim def D13 : AFPR<26, "F26", [F26, F27]>; 142223017Sdim def D14 : AFPR<28, "F28", [F28, F29]>; 143223017Sdim def D15 : AFPR<30, "F30", [F30, F31]>; 144193323Sed 145193323Sed // Hi/Lo registers 146193323Sed def HI : Register<"hi">, DwarfRegNum<[64]>; 147193323Sed def LO : Register<"lo">, DwarfRegNum<[65]>; 148193323Sed 149193323Sed // Status flags register 150193323Sed def FCR31 : Register<"31">; 151223017Sdim 152223017Sdim // Hardware register $29 153223017Sdim def HWR29 : Register<"29">; 154193323Sed} 155193323Sed 156193323Sed//===----------------------------------------------------------------------===// 157193323Sed// Register Classes 158193323Sed//===----------------------------------------------------------------------===// 159193323Sed 160224145Sdimdef CPURegs : RegisterClass<"Mips", [i32], 32, (add 161193323Sed // Return Values and Arguments 162224145Sdim V0, V1, A0, A1, A2, A3, 163193323Sed // Not preserved across procedure calls 164221345Sdim T0, T1, T2, T3, T4, T5, T6, T7, T8, T9, 165193323Sed // Callee save 166193323Sed S0, S1, S2, S3, S4, S5, S6, S7, 167193323Sed // Reserved 168224145Sdim ZERO, AT, K0, K1, GP, SP, FP, RA)>; 169193323Sed 170193323Sed// 64bit fp: 171193323Sed// * FGR64 - 32 64-bit registers 172221345Sdim// * AFGR64 - 16 32-bit even registers (32-bit FP Mode) 173193323Sed// 174193323Sed// 32bit fp: 175193323Sed// * FGR32 - 16 32-bit even registers 176193323Sed// * FGR32 - 32 32-bit registers (single float only mode) 177224145Sdimdef FGR32 : RegisterClass<"Mips", [f32], 32, (sequence "F%u", 0, 31)>; 178193323Sed 179224145Sdimdef AFGR64 : RegisterClass<"Mips", [f64], 64, (add 180193323Sed // Return Values and Arguments 181224145Sdim D0, D1, D6, D7, 182193323Sed // Not preserved across procedure calls 183221345Sdim D2, D3, D4, D5, D8, D9, 184193323Sed // Callee save 185193323Sed D10, D11, D12, D13, D14, 186193323Sed // Reserved 187224145Sdim D15)> { 188208599Srdivacky let SubRegClasses = [(FGR32 sub_fpeven, sub_fpodd)]; 189193323Sed} 190193323Sed 191193323Sed// Condition Register for floating point operations 192224145Sdimdef CCR : RegisterClass<"Mips", [i32], 32, (add FCR31)>; 193193323Sed 194193323Sed// Hi/Lo Registers 195224145Sdimdef HILO : RegisterClass<"Mips", [i32], 32, (add HI, LO)>; 196193323Sed 197223017Sdim// Hardware registers 198224145Sdimdef HWRegs : RegisterClass<"Mips", [i32], 32, (add HWR29)>; 199